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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.42 97.37 89.65 97.22 72.62 94.47 98.44 90.21


Total test records in report: 1862
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T1768 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.2458252115 Aug 27 07:33:53 AM UTC 24 Aug 27 07:33:55 AM UTC 24 195008585 ps
T1769 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.919307282 Aug 27 07:33:49 AM UTC 24 Aug 27 07:33:56 AM UTC 24 1293162404 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1017466184 Aug 27 07:33:54 AM UTC 24 Aug 27 07:33:56 AM UTC 24 15679719 ps
T1770 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.204407943 Aug 27 07:33:54 AM UTC 24 Aug 27 07:33:57 AM UTC 24 20783057 ps
T1771 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4164720087 Aug 27 07:33:54 AM UTC 24 Aug 27 07:33:57 AM UTC 24 99727396 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1642679448 Aug 27 07:33:53 AM UTC 24 Aug 27 07:33:57 AM UTC 24 237288204 ps
T1772 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.4212705745 Aug 27 07:33:54 AM UTC 24 Aug 27 07:33:58 AM UTC 24 80473137 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.479282206 Aug 27 07:33:56 AM UTC 24 Aug 27 07:33:58 AM UTC 24 48357225 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.4128398727 Aug 27 07:33:56 AM UTC 24 Aug 27 07:33:58 AM UTC 24 25292486 ps
T1773 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.506231831 Aug 27 07:33:56 AM UTC 24 Aug 27 07:33:58 AM UTC 24 23399009 ps
T1774 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2730114409 Aug 27 07:33:56 AM UTC 24 Aug 27 07:33:58 AM UTC 24 65887013 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3770102329 Aug 27 07:33:54 AM UTC 24 Aug 27 07:33:59 AM UTC 24 588789183 ps
T1775 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2451883206 Aug 27 07:33:57 AM UTC 24 Aug 27 07:34:00 AM UTC 24 22277397 ps
T1776 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.592486921 Aug 27 07:33:58 AM UTC 24 Aug 27 07:34:00 AM UTC 24 35641999 ps
T1777 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.3041623988 Aug 27 07:33:56 AM UTC 24 Aug 27 07:34:00 AM UTC 24 67509611 ps
T1778 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2596030457 Aug 27 07:33:58 AM UTC 24 Aug 27 07:34:00 AM UTC 24 34687975 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1894209325 Aug 27 07:33:56 AM UTC 24 Aug 27 07:34:00 AM UTC 24 155620098 ps
T1779 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.1139900713 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:01 AM UTC 24 21417849 ps
T1780 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.94216920 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:01 AM UTC 24 21855995 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.1867551382 Aug 27 07:33:58 AM UTC 24 Aug 27 07:34:01 AM UTC 24 286775699 ps
T1781 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2117348344 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:01 AM UTC 24 81497940 ps
T1782 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.420098468 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:02 AM UTC 24 65744584 ps
T1783 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.102482814 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:02 AM UTC 24 36109995 ps
T1784 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.439137696 Aug 27 07:33:59 AM UTC 24 Aug 27 07:34:03 AM UTC 24 270660849 ps
T1785 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2136185696 Aug 27 07:34:01 AM UTC 24 Aug 27 07:34:03 AM UTC 24 16532851 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2601153684 Aug 27 07:34:01 AM UTC 24 Aug 27 07:34:03 AM UTC 24 62384850 ps
T1786 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2158495393 Aug 27 07:34:01 AM UTC 24 Aug 27 07:34:03 AM UTC 24 40613555 ps
T1787 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.204672090 Aug 27 07:34:01 AM UTC 24 Aug 27 07:34:03 AM UTC 24 39341903 ps
T1788 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.503340346 Aug 27 07:34:02 AM UTC 24 Aug 27 07:34:04 AM UTC 24 17724896 ps
T1789 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3385917826 Aug 27 07:34:03 AM UTC 24 Aug 27 07:34:05 AM UTC 24 35373949 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1582489501 Aug 27 07:34:02 AM UTC 24 Aug 27 07:34:05 AM UTC 24 33336568 ps
T1790 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3598098074 Aug 27 07:34:03 AM UTC 24 Aug 27 07:34:05 AM UTC 24 60659340 ps
T1791 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3286891753 Aug 27 07:34:03 AM UTC 24 Aug 27 07:34:05 AM UTC 24 85579742 ps
T1792 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3434080031 Aug 27 07:34:01 AM UTC 24 Aug 27 07:34:05 AM UTC 24 110883999 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.1660285188 Aug 27 07:34:02 AM UTC 24 Aug 27 07:34:05 AM UTC 24 46155532 ps
T1793 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.444258217 Aug 27 07:34:03 AM UTC 24 Aug 27 07:34:05 AM UTC 24 27172683 ps
T1794 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.4264425084 Aug 27 07:34:03 AM UTC 24 Aug 27 07:34:06 AM UTC 24 492226672 ps
T1795 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1769982645 Aug 27 07:34:04 AM UTC 24 Aug 27 07:34:06 AM UTC 24 44037591 ps
T1796 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1253043500 Aug 27 07:34:04 AM UTC 24 Aug 27 07:34:07 AM UTC 24 44213433 ps
T1797 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3469213182 Aug 27 07:34:04 AM UTC 24 Aug 27 07:34:07 AM UTC 24 85444223 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1241823586 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:08 AM UTC 24 29455386 ps
T1798 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.768045248 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:08 AM UTC 24 21729009 ps
T1799 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2381542540 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:08 AM UTC 24 18530703 ps
T1800 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1200333714 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:08 AM UTC 24 97226227 ps
T1801 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2469079454 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:08 AM UTC 24 85219839 ps
T1802 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3834167523 Aug 27 07:34:04 AM UTC 24 Aug 27 07:34:08 AM UTC 24 158097537 ps
T1803 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2629066400 Aug 27 07:34:04 AM UTC 24 Aug 27 07:34:09 AM UTC 24 264846883 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.983929474 Aug 27 07:34:07 AM UTC 24 Aug 27 07:34:09 AM UTC 24 18610833 ps
T1804 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3388158585 Aug 27 07:34:08 AM UTC 24 Aug 27 07:34:10 AM UTC 24 37283991 ps
T1805 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3341355767 Aug 27 07:34:07 AM UTC 24 Aug 27 07:34:10 AM UTC 24 84650550 ps
T1806 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3243090318 Aug 27 07:34:08 AM UTC 24 Aug 27 07:34:10 AM UTC 24 164594732 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.3691411561 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:10 AM UTC 24 319627678 ps
T1807 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1910916853 Aug 27 07:34:06 AM UTC 24 Aug 27 07:34:10 AM UTC 24 51799810 ps
T1808 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2370331807 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:11 AM UTC 24 18854456 ps
T1809 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2609132069 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:11 AM UTC 24 19563928 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.3149636266 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:11 AM UTC 24 17769737 ps
T1810 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.851792248 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:11 AM UTC 24 32529831 ps
T1811 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1677322998 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:12 AM UTC 24 114514251 ps
T1812 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.1741338991 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:12 AM UTC 24 28747694 ps
T1813 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.2227959448 Aug 27 07:34:08 AM UTC 24 Aug 27 07:34:12 AM UTC 24 179291013 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1107336121 Aug 27 07:34:11 AM UTC 24 Aug 27 07:34:13 AM UTC 24 38292431 ps
T1814 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1264909039 Aug 27 07:34:11 AM UTC 24 Aug 27 07:34:13 AM UTC 24 34747822 ps
T1815 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2055225652 Aug 27 07:34:11 AM UTC 24 Aug 27 07:34:14 AM UTC 24 116685164 ps
T1816 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3632181883 Aug 27 07:34:11 AM UTC 24 Aug 27 07:34:14 AM UTC 24 32474461 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.900406806 Aug 27 07:34:09 AM UTC 24 Aug 27 07:34:14 AM UTC 24 1653308011 ps
T1817 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.2460721854 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:14 AM UTC 24 49508846 ps
T1818 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.2138037085 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:14 AM UTC 24 43921599 ps
T1819 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1271845542 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:15 AM UTC 24 70250848 ps
T1820 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1504308931 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:15 AM UTC 24 37302869 ps
T1821 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3695576665 Aug 27 07:34:11 AM UTC 24 Aug 27 07:34:15 AM UTC 24 228613947 ps
T1822 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.673504806 Aug 27 07:34:14 AM UTC 24 Aug 27 07:34:16 AM UTC 24 55650683 ps
T1823 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3875142389 Aug 27 07:34:14 AM UTC 24 Aug 27 07:34:16 AM UTC 24 36304674 ps
T1824 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2972573689 Aug 27 07:34:14 AM UTC 24 Aug 27 07:34:16 AM UTC 24 218557837 ps
T1825 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.2896702824 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:16 AM UTC 24 92797325 ps
T1826 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2709485656 Aug 27 07:34:14 AM UTC 24 Aug 27 07:34:16 AM UTC 24 27618275 ps
T1827 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.37727383 Aug 27 07:34:14 AM UTC 24 Aug 27 07:34:16 AM UTC 24 92939790 ps
T1828 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1400459337 Aug 27 07:34:12 AM UTC 24 Aug 27 07:34:16 AM UTC 24 256234464 ps
T1829 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.2478147503 Aug 27 07:34:15 AM UTC 24 Aug 27 07:34:17 AM UTC 24 28065681 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.4033969001 Aug 27 07:34:15 AM UTC 24 Aug 27 07:34:18 AM UTC 24 21176942 ps
T1830 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.1660561324 Aug 27 07:34:16 AM UTC 24 Aug 27 07:34:18 AM UTC 24 20747659 ps
T1831 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1897241859 Aug 27 07:34:16 AM UTC 24 Aug 27 07:34:18 AM UTC 24 20184512 ps
T1832 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3016294960 Aug 27 07:34:16 AM UTC 24 Aug 27 07:34:18 AM UTC 24 49305496 ps
T1833 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4106124282 Aug 27 07:34:16 AM UTC 24 Aug 27 07:34:18 AM UTC 24 95985975 ps
T1834 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2324115907 Aug 27 07:34:16 AM UTC 24 Aug 27 07:34:18 AM UTC 24 63033394 ps
T1835 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.905700063 Aug 27 07:34:15 AM UTC 24 Aug 27 07:34:19 AM UTC 24 73587299 ps
T1836 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.477683763 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:19 AM UTC 24 22743967 ps
T1837 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.1758867676 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:19 AM UTC 24 47701698 ps
T1838 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2361444774 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:19 AM UTC 24 25092584 ps
T1839 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.2538632029 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:19 AM UTC 24 32318633 ps
T1840 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.3101201555 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:20 AM UTC 24 17045181 ps
T1841 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2411120552 Aug 27 07:34:18 AM UTC 24 Aug 27 07:34:20 AM UTC 24 18008376 ps
T1842 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.251279071 Aug 27 07:34:17 AM UTC 24 Aug 27 07:34:20 AM UTC 24 21590910 ps
T1843 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.639321095 Aug 27 07:34:18 AM UTC 24 Aug 27 07:34:20 AM UTC 24 29075115 ps
T1844 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.761540097 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 17652107 ps
T1845 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.1620123374 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 109244034 ps
T1846 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.4014868319 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 14819335 ps
T1847 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.4143144882 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 31547393 ps
T1848 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.2563753846 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 31210339 ps
T1849 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.63701727 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:21 AM UTC 24 86776476 ps
T1850 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3975710 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:22 AM UTC 24 17617871 ps
T1851 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.2248414526 Aug 27 07:34:19 AM UTC 24 Aug 27 07:34:22 AM UTC 24 16966304 ps
T1852 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3936147868 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 16907797 ps
T1853 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1545725370 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 20083772 ps
T1854 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.3302253151 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 15379256 ps
T1855 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.2830967710 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 19785526 ps
T1856 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.97973332 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 43240189 ps
T1857 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.417493202 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 55044514 ps
T1858 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.2704396929 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 48030008 ps
T1859 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.506543988 Aug 27 07:34:21 AM UTC 24 Aug 27 07:34:23 AM UTC 24 15595995 ps
T1860 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.82473901 Aug 27 07:34:22 AM UTC 24 Aug 27 07:34:23 AM UTC 24 59300354 ps
T1861 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2335947856 Aug 27 07:34:22 AM UTC 24 Aug 27 07:34:23 AM UTC 24 55917743 ps
T1862 /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.1544285756 Aug 27 07:34:22 AM UTC 24 Aug 27 07:34:24 AM UTC 24 46503495 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.749963420
Short name T10
Test name
Test status
Simulation time 1905324282 ps
CPU time 4.98 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:00 AM UTC 24
Peak memory 232848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749963
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.749963420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.238997897
Short name T13
Test name
Test status
Simulation time 1654647339 ps
CPU time 14.56 seconds
Started Aug 27 07:03:49 AM UTC 24
Finished Aug 27 07:04:05 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238997897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.238997897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_stress_all.1965657943
Short name T21
Test name
Test status
Simulation time 10722279896 ps
CPU time 158.88 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:06:31 AM UTC 24
Peak memory 1200424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965657943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1965657943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.116982359
Short name T57
Test name
Test status
Simulation time 9114403265 ps
CPU time 10.59 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:01 AM UTC 24
Peak memory 227392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116982359 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.116982359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.406364991
Short name T119
Test name
Test status
Simulation time 879098654 ps
CPU time 3.3 seconds
Started Aug 27 07:33:40 AM UTC 24
Finished Aug 27 07:33:44 AM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406364991 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.406364991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3624124821
Short name T2
Test name
Test status
Simulation time 403806189 ps
CPU time 1.66 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:03:52 AM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624124821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3624124821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_nack_txstretch.930966778
Short name T68
Test name
Test status
Simulation time 758326379 ps
CPU time 1.4 seconds
Started Aug 27 07:03:58 AM UTC 24
Finished Aug 27 07:04:01 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9309667
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_txstretch.930966778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.3699024652
Short name T52
Test name
Test status
Simulation time 398182350 ps
CPU time 3.63 seconds
Started Aug 27 07:03:45 AM UTC 24
Finished Aug 27 07:04:07 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699024652 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.3699024652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_override.1013174733
Short name T79
Test name
Test status
Simulation time 34819230 ps
CPU time 0.58 seconds
Started Aug 27 07:03:42 AM UTC 24
Finished Aug 27 07:04:04 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013174733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1013174733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1975903101
Short name T83
Test name
Test status
Simulation time 142815594 ps
CPU time 0.8 seconds
Started Aug 27 07:03:58 AM UTC 24
Finished Aug 27 07:04:01 AM UTC 24
Peak memory 246748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975903101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1975903101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.2927240506
Short name T5
Test name
Test status
Simulation time 8151923647 ps
CPU time 24.18 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:20 AM UTC 24
Peak memory 248224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292724
0506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.2927240506
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2611946375
Short name T161
Test name
Test status
Simulation time 1300173570 ps
CPU time 5.67 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:17 AM UTC 24
Peak memory 262056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611946375 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.2611946375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.3802785179
Short name T54
Test name
Test status
Simulation time 986801818 ps
CPU time 2.99 seconds
Started Aug 27 07:15:41 AM UTC 24
Finished Aug 27 07:15:45 AM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802785
179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad
dr.3802785179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.2414050910
Short name T71
Test name
Test status
Simulation time 1022634160 ps
CPU time 2.53 seconds
Started Aug 27 07:03:57 AM UTC 24
Finished Aug 27 07:04:03 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414050
910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.2414050910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.3437785058
Short name T231
Test name
Test status
Simulation time 951993400 ps
CPU time 5.88 seconds
Started Aug 27 07:33:34 AM UTC 24
Finished Aug 27 07:33:41 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437785058 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3437785058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2854065880
Short name T209
Test name
Test status
Simulation time 287318262 ps
CPU time 2.63 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:51 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854065880 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2854065880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3354849427
Short name T63
Test name
Test status
Simulation time 8683417828 ps
CPU time 41.68 seconds
Started Aug 27 07:04:56 AM UTC 24
Finished Aug 27 07:05:39 AM UTC 24
Peak memory 614808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3354849427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress
_wr.3354849427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_stress_all.1758994848
Short name T138
Test name
Test status
Simulation time 22402571519 ps
CPU time 42.26 seconds
Started Aug 27 07:07:53 AM UTC 24
Finished Aug 27 07:08:36 AM UTC 24
Peak memory 366888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758994848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1758994848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.465352923
Short name T75
Test name
Test status
Simulation time 4121893069 ps
CPU time 5.93 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:13 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=465352923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.465352923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.2881000912
Short name T253
Test name
Test status
Simulation time 163501951 ps
CPU time 1.71 seconds
Started Aug 27 07:04:49 AM UTC 24
Finished Aug 27 07:04:52 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881000912 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.2881000912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.3664100962
Short name T60
Test name
Test status
Simulation time 1006993844 ps
CPU time 4.7 seconds
Started Aug 27 07:13:12 AM UTC 24
Finished Aug 27 07:13:18 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664100
962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.3664100962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.559289314
Short name T260
Test name
Test status
Simulation time 1058829016 ps
CPU time 7.13 seconds
Started Aug 27 07:04:44 AM UTC 24
Finished Aug 27 07:04:53 AM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559289314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.559289314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_stress_all.2389585105
Short name T44
Test name
Test status
Simulation time 15755383678 ps
CPU time 841.73 seconds
Started Aug 27 07:06:20 AM UTC 24
Finished Aug 27 07:20:31 AM UTC 24
Peak memory 1616356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389585105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2389585105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.1753152166
Short name T582
Test name
Test status
Simulation time 24435795350 ps
CPU time 114.6 seconds
Started Aug 27 07:07:22 AM UTC 24
Finished Aug 27 07:09:19 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753152166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.1753152166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.832850120
Short name T41
Test name
Test status
Simulation time 3459977656 ps
CPU time 68.65 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:05:45 AM UTC 24
Peak memory 381204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832850120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.832850120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_alert_test.3611424488
Short name T9
Test name
Test status
Simulation time 23643724 ps
CPU time 0.53 seconds
Started Aug 27 07:03:58 AM UTC 24
Finished Aug 27 07:04:00 AM UTC 24
Peak memory 215336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611424488 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3611424488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_stress_all.364412169
Short name T26
Test name
Test status
Simulation time 50009717800 ps
CPU time 553.67 seconds
Started Aug 27 07:06:58 AM UTC 24
Finished Aug 27 07:16:18 AM UTC 24
Peak memory 2244952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364412169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.364412169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.1145258727
Short name T88
Test name
Test status
Simulation time 2965374511 ps
CPU time 60.29 seconds
Started Aug 27 07:04:08 AM UTC 24
Finished Aug 27 07:05:10 AM UTC 24
Peak memory 973208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145258727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1145258727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.444342547
Short name T24
Test name
Test status
Simulation time 755937601 ps
CPU time 7.25 seconds
Started Aug 27 07:07:23 AM UTC 24
Finished Aug 27 07:07:31 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444342547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.444342547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.2465505688
Short name T233
Test name
Test status
Simulation time 31682839 ps
CPU time 1.14 seconds
Started Aug 27 07:33:41 AM UTC 24
Finished Aug 27 07:33:44 AM UTC 24
Peak memory 214312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465505688 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2465505688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.1495449618
Short name T33
Test name
Test status
Simulation time 2254441823 ps
CPU time 21.95 seconds
Started Aug 27 07:05:43 AM UTC 24
Finished Aug 27 07:06:06 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495449618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1495449618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.1758867676
Short name T1837
Test name
Test status
Simulation time 47701698 ps
CPU time 0.87 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:19 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758867676 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1758867676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.1575776880
Short name T288
Test name
Test status
Simulation time 1909220957 ps
CPU time 4.89 seconds
Started Aug 27 07:11:11 AM UTC 24
Finished Aug 27 07:11:17 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575776
880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.1575776880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1502414918
Short name T36
Test name
Test status
Simulation time 130829586 ps
CPU time 1.94 seconds
Started Aug 27 07:31:53 AM UTC 24
Finished Aug 27 07:31:56 AM UTC 24
Peak memory 228376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502414918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1502414918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_mode_toggle.2749084425
Short name T279
Test name
Test status
Simulation time 429927322 ps
CPU time 3.18 seconds
Started Aug 27 07:10:32 AM UTC 24
Finished Aug 27 07:10:37 AM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749084425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2749084425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.577921563
Short name T91
Test name
Test status
Simulation time 667663786 ps
CPU time 9.36 seconds
Started Aug 27 07:12:54 AM UTC 24
Finished Aug 27 07:13:04 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577921563 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.577921563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.1492878200
Short name T158
Test name
Test status
Simulation time 233005058 ps
CPU time 1.78 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:04 AM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492878
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.1492878200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.466740878
Short name T139
Test name
Test status
Simulation time 40717299031 ps
CPU time 258.28 seconds
Started Aug 27 07:09:44 AM UTC 24
Finished Aug 27 07:14:06 AM UTC 24
Peak memory 2294048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466740878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.466740878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.1801604777
Short name T264
Test name
Test status
Simulation time 423454384 ps
CPU time 5.93 seconds
Started Aug 27 07:11:06 AM UTC 24
Finished Aug 27 07:11:13 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801604777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1801604777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.1439735800
Short name T256
Test name
Test status
Simulation time 368120268 ps
CPU time 1.65 seconds
Started Aug 27 07:11:48 AM UTC 24
Finished Aug 27 07:11:51 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439735800 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.1439735800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3129777120
Short name T211
Test name
Test status
Simulation time 109315670 ps
CPU time 2.51 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:48 AM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129777120 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3129777120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.1355837867
Short name T14
Test name
Test status
Simulation time 344144380 ps
CPU time 13.75 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:21 AM UTC 24
Peak memory 216548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355837867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1355837867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3695576665
Short name T1821
Test name
Test status
Simulation time 228613947 ps
CPU time 3.11 seconds
Started Aug 27 07:34:11 AM UTC 24
Finished Aug 27 07:34:15 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695576665 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3695576665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.1753825908
Short name T192
Test name
Test status
Simulation time 9209593394 ps
CPU time 136.48 seconds
Started Aug 27 07:03:43 AM UTC 24
Finished Aug 27 07:06:09 AM UTC 24
Peak memory 780548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753825908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1753825908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.4094863346
Short name T140
Test name
Test status
Simulation time 30550260 ps
CPU time 1.07 seconds
Started Aug 27 07:33:33 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 214168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094863346 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4094863346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.2694420040
Short name T80
Test name
Test status
Simulation time 538743207 ps
CPU time 6.84 seconds
Started Aug 27 07:03:56 AM UTC 24
Finished Aug 27 07:04:07 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694420
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2694420040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.1713530284
Short name T277
Test name
Test status
Simulation time 5257708792 ps
CPU time 55.99 seconds
Started Aug 27 07:04:04 AM UTC 24
Finished Aug 27 07:05:02 AM UTC 24
Peak memory 228920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713530284 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.1713530284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.1097926331
Short name T265
Test name
Test status
Simulation time 2112103629 ps
CPU time 4.1 seconds
Started Aug 27 07:07:12 AM UTC 24
Finished Aug 27 07:07:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097926331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1097926331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.1626930909
Short name T479
Test name
Test status
Simulation time 817328117 ps
CPU time 28.3 seconds
Started Aug 27 07:06:56 AM UTC 24
Finished Aug 27 07:07:25 AM UTC 24
Peak memory 227068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626930909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1626930909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.3877628770
Short name T287
Test name
Test status
Simulation time 179987790 ps
CPU time 2.08 seconds
Started Aug 27 07:08:53 AM UTC 24
Finished Aug 27 07:08:56 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877628
770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.3877628770
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.1252362922
Short name T284
Test name
Test status
Simulation time 1681616027 ps
CPU time 17.1 seconds
Started Aug 27 07:10:17 AM UTC 24
Finished Aug 27 07:10:36 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252362922 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.1252362922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.3715227483
Short name T273
Test name
Test status
Simulation time 653781383 ps
CPU time 8.3 seconds
Started Aug 27 07:12:08 AM UTC 24
Finished Aug 27 07:12:18 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715227483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3715227483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.1808489976
Short name T65
Test name
Test status
Simulation time 39799004501 ps
CPU time 102.73 seconds
Started Aug 27 07:04:04 AM UTC 24
Finished Aug 27 07:05:49 AM UTC 24
Peak memory 1841304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808489976 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.1808489976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1773785817
Short name T202
Test name
Test status
Simulation time 815606359 ps
CPU time 3 seconds
Started Aug 27 07:33:32 AM UTC 24
Finished Aug 27 07:33:36 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773785817 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1773785817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3089368841
Short name T118
Test name
Test status
Simulation time 260313126 ps
CPU time 2.91 seconds
Started Aug 27 07:33:40 AM UTC 24
Finished Aug 27 07:33:44 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089368841 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3089368841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.4030953723
Short name T212
Test name
Test status
Simulation time 128142708 ps
CPU time 3.13 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:54 AM UTC 24
Peak memory 215164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030953723 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4030953723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.2760907670
Short name T159
Test name
Test status
Simulation time 237386124 ps
CPU time 1.78 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:04 AM UTC 24
Peak memory 226492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760907
670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.2760907670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_mode_toggle.2981132570
Short name T20
Test name
Test status
Simulation time 89276121 ps
CPU time 1.41 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:09 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981132570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2981132570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.3389864685
Short name T30
Test name
Test status
Simulation time 378973948 ps
CPU time 2.64 seconds
Started Aug 27 07:29:13 AM UTC 24
Finished Aug 27 07:29:16 AM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389864685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3389864685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1630990143
Short name T1757
Test name
Test status
Simulation time 54922566 ps
CPU time 1.58 seconds
Started Aug 27 07:33:35 AM UTC 24
Finished Aug 27 07:33:38 AM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630990143 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1630990143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1800642370
Short name T221
Test name
Test status
Simulation time 28008860 ps
CPU time 1.1 seconds
Started Aug 27 07:33:33 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800642370 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1800642370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3487552650
Short name T203
Test name
Test status
Simulation time 98082649 ps
CPU time 1.54 seconds
Started Aug 27 07:33:36 AM UTC 24
Finished Aug 27 07:33:39 AM UTC 24
Peak memory 224648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3487552650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3487552650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3427143775
Short name T222
Test name
Test status
Simulation time 61328712 ps
CPU time 1.14 seconds
Started Aug 27 07:33:33 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427143775 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3427143775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2612148076
Short name T113
Test name
Test status
Simulation time 280396991 ps
CPU time 1.82 seconds
Started Aug 27 07:33:35 AM UTC 24
Finished Aug 27 07:33:38 AM UTC 24
Peak memory 214732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612148076 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.2612148076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2097763281
Short name T112
Test name
Test status
Simulation time 438604917 ps
CPU time 2.24 seconds
Started Aug 27 07:33:32 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097763281 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2097763281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.69286167
Short name T117
Test name
Test status
Simulation time 226864024 ps
CPU time 2.81 seconds
Started Aug 27 07:33:39 AM UTC 24
Finished Aug 27 07:33:43 AM UTC 24
Peak memory 215152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69286167 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.69286167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4017198753
Short name T1758
Test name
Test status
Simulation time 722786071 ps
CPU time 2.95 seconds
Started Aug 27 07:33:39 AM UTC 24
Finished Aug 27 07:33:43 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017198753 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.4017198753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2639693841
Short name T114
Test name
Test status
Simulation time 29639918 ps
CPU time 1.22 seconds
Started Aug 27 07:33:37 AM UTC 24
Finished Aug 27 07:33:39 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639693841 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2639693841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3245206371
Short name T227
Test name
Test status
Simulation time 73643003 ps
CPU time 1.63 seconds
Started Aug 27 07:33:40 AM UTC 24
Finished Aug 27 07:33:43 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3245206371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3245206371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.292199553
Short name T230
Test name
Test status
Simulation time 19435339 ps
CPU time 1.16 seconds
Started Aug 27 07:33:37 AM UTC 24
Finished Aug 27 07:33:39 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292199553 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.292199553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.464021044
Short name T141
Test name
Test status
Simulation time 27288390 ps
CPU time 0.99 seconds
Started Aug 27 07:33:37 AM UTC 24
Finished Aug 27 07:33:39 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464021044 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.464021044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1771599804
Short name T116
Test name
Test status
Simulation time 68401309 ps
CPU time 1.39 seconds
Started Aug 27 07:33:40 AM UTC 24
Finished Aug 27 07:33:42 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771599804 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.1771599804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3246700331
Short name T208
Test name
Test status
Simulation time 82014418 ps
CPU time 2.4 seconds
Started Aug 27 07:33:36 AM UTC 24
Finished Aug 27 07:33:40 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246700331 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3246700331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.157548696
Short name T115
Test name
Test status
Simulation time 80106893 ps
CPU time 2.23 seconds
Started Aug 27 07:33:37 AM UTC 24
Finished Aug 27 07:33:40 AM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157548696 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.157548696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.204672090
Short name T1787
Test name
Test status
Simulation time 39341903 ps
CPU time 1.37 seconds
Started Aug 27 07:34:01 AM UTC 24
Finished Aug 27 07:34:03 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=204672090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.204672090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.2601153684
Short name T237
Test name
Test status
Simulation time 62384850 ps
CPU time 1.1 seconds
Started Aug 27 07:34:01 AM UTC 24
Finished Aug 27 07:34:03 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601153684 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2601153684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2136185696
Short name T1785
Test name
Test status
Simulation time 16532851 ps
CPU time 1.05 seconds
Started Aug 27 07:34:01 AM UTC 24
Finished Aug 27 07:34:03 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136185696 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2136185696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2158495393
Short name T1786
Test name
Test status
Simulation time 40613555 ps
CPU time 1.16 seconds
Started Aug 27 07:34:01 AM UTC 24
Finished Aug 27 07:34:03 AM UTC 24
Peak memory 214716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158495393 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.2158495393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.102482814
Short name T1783
Test name
Test status
Simulation time 36109995 ps
CPU time 1.6 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:02 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102482814 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.102482814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.439137696
Short name T1784
Test name
Test status
Simulation time 270660849 ps
CPU time 2.2 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:03 AM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439137696 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.439137696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3286891753
Short name T1791
Test name
Test status
Simulation time 85579742 ps
CPU time 1.23 seconds
Started Aug 27 07:34:03 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3286891753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3286891753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1582489501
Short name T239
Test name
Test status
Simulation time 33336568 ps
CPU time 1.12 seconds
Started Aug 27 07:34:02 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582489501 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1582489501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.503340346
Short name T1788
Test name
Test status
Simulation time 17724896 ps
CPU time 0.92 seconds
Started Aug 27 07:34:02 AM UTC 24
Finished Aug 27 07:34:04 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503340346 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.503340346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3598098074
Short name T1790
Test name
Test status
Simulation time 60659340 ps
CPU time 1.18 seconds
Started Aug 27 07:34:03 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598098074 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.3598098074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3434080031
Short name T1792
Test name
Test status
Simulation time 110883999 ps
CPU time 2.91 seconds
Started Aug 27 07:34:01 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 215184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434080031 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3434080031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.1660285188
Short name T216
Test name
Test status
Simulation time 46155532 ps
CPU time 1.8 seconds
Started Aug 27 07:34:02 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660285188 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1660285188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1253043500
Short name T1796
Test name
Test status
Simulation time 44213433 ps
CPU time 1.61 seconds
Started Aug 27 07:34:04 AM UTC 24
Finished Aug 27 07:34:07 AM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1253043500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1253043500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1769982645
Short name T1795
Test name
Test status
Simulation time 44037591 ps
CPU time 1.03 seconds
Started Aug 27 07:34:04 AM UTC 24
Finished Aug 27 07:34:06 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769982645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1769982645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3385917826
Short name T1789
Test name
Test status
Simulation time 35373949 ps
CPU time 0.83 seconds
Started Aug 27 07:34:03 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385917826 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3385917826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3469213182
Short name T1797
Test name
Test status
Simulation time 85444223 ps
CPU time 1.66 seconds
Started Aug 27 07:34:04 AM UTC 24
Finished Aug 27 07:34:07 AM UTC 24
Peak memory 214580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469213182 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.3469213182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.444258217
Short name T1793
Test name
Test status
Simulation time 27172683 ps
CPU time 1.58 seconds
Started Aug 27 07:34:03 AM UTC 24
Finished Aug 27 07:34:05 AM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444258217 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.444258217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.4264425084
Short name T1794
Test name
Test status
Simulation time 492226672 ps
CPU time 1.92 seconds
Started Aug 27 07:34:03 AM UTC 24
Finished Aug 27 07:34:06 AM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264425084 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.4264425084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2469079454
Short name T1801
Test name
Test status
Simulation time 85219839 ps
CPU time 1.31 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 214748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2469079454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2469079454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.768045248
Short name T1798
Test name
Test status
Simulation time 21729009 ps
CPU time 1.02 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768045248 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.768045248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1241823586
Short name T299
Test name
Test status
Simulation time 29455386 ps
CPU time 0.95 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241823586 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1241823586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1200333714
Short name T1800
Test name
Test status
Simulation time 97226227 ps
CPU time 1.32 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200333714 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.1200333714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2629066400
Short name T1803
Test name
Test status
Simulation time 264846883 ps
CPU time 3.8 seconds
Started Aug 27 07:34:04 AM UTC 24
Finished Aug 27 07:34:09 AM UTC 24
Peak memory 215184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629066400 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2629066400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3834167523
Short name T1802
Test name
Test status
Simulation time 158097537 ps
CPU time 3.06 seconds
Started Aug 27 07:34:04 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834167523 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3834167523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3388158585
Short name T1804
Test name
Test status
Simulation time 37283991 ps
CPU time 1.14 seconds
Started Aug 27 07:34:08 AM UTC 24
Finished Aug 27 07:34:10 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3388158585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3388158585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.983929474
Short name T240
Test name
Test status
Simulation time 18610833 ps
CPU time 1 seconds
Started Aug 27 07:34:07 AM UTC 24
Finished Aug 27 07:34:09 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983929474 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.983929474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.2381542540
Short name T1799
Test name
Test status
Simulation time 18530703 ps
CPU time 1 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381542540 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2381542540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3341355767
Short name T1805
Test name
Test status
Simulation time 84650550 ps
CPU time 1.59 seconds
Started Aug 27 07:34:07 AM UTC 24
Finished Aug 27 07:34:10 AM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341355767 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.3341355767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.1910916853
Short name T1807
Test name
Test status
Simulation time 51799810 ps
CPU time 3.46 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:10 AM UTC 24
Peak memory 215212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910916853 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1910916853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.3691411561
Short name T218
Test name
Test status
Simulation time 319627678 ps
CPU time 3.26 seconds
Started Aug 27 07:34:06 AM UTC 24
Finished Aug 27 07:34:10 AM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691411561 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3691411561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.851792248
Short name T1810
Test name
Test status
Simulation time 32529831 ps
CPU time 1.09 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:11 AM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=851792248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.851792248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.3149636266
Short name T241
Test name
Test status
Simulation time 17769737 ps
CPU time 1.05 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:11 AM UTC 24
Peak memory 214492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149636266 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3149636266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2370331807
Short name T1808
Test name
Test status
Simulation time 18854456 ps
CPU time 1.13 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:11 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370331807 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2370331807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1677322998
Short name T1811
Test name
Test status
Simulation time 114514251 ps
CPU time 1.46 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:12 AM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677322998 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.1677322998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.2227959448
Short name T1813
Test name
Test status
Simulation time 179291013 ps
CPU time 3.71 seconds
Started Aug 27 07:34:08 AM UTC 24
Finished Aug 27 07:34:12 AM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227959448 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2227959448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3243090318
Short name T1806
Test name
Test status
Simulation time 164594732 ps
CPU time 1.43 seconds
Started Aug 27 07:34:08 AM UTC 24
Finished Aug 27 07:34:10 AM UTC 24
Peak memory 214712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243090318 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3243090318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3632181883
Short name T1816
Test name
Test status
Simulation time 32474461 ps
CPU time 1.94 seconds
Started Aug 27 07:34:11 AM UTC 24
Finished Aug 27 07:34:14 AM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3632181883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3632181883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1107336121
Short name T242
Test name
Test status
Simulation time 38292431 ps
CPU time 0.98 seconds
Started Aug 27 07:34:11 AM UTC 24
Finished Aug 27 07:34:13 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107336121 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1107336121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2609132069
Short name T1809
Test name
Test status
Simulation time 19563928 ps
CPU time 0.89 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:11 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609132069 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2609132069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1264909039
Short name T1814
Test name
Test status
Simulation time 34747822 ps
CPU time 1.52 seconds
Started Aug 27 07:34:11 AM UTC 24
Finished Aug 27 07:34:13 AM UTC 24
Peak memory 214608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264909039 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.1264909039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.1741338991
Short name T1812
Test name
Test status
Simulation time 28747694 ps
CPU time 1.87 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:12 AM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741338991 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1741338991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.900406806
Short name T220
Test name
Test status
Simulation time 1653308011 ps
CPU time 3.25 seconds
Started Aug 27 07:34:09 AM UTC 24
Finished Aug 27 07:34:14 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900406806 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.900406806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1504308931
Short name T1820
Test name
Test status
Simulation time 37302869 ps
CPU time 1.57 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:15 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1504308931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1504308931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.2138037085
Short name T1818
Test name
Test status
Simulation time 43921599 ps
CPU time 1.04 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:14 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138037085 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2138037085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.2460721854
Short name T1817
Test name
Test status
Simulation time 49508846 ps
CPU time 0.95 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:14 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460721854 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2460721854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1271845542
Short name T1819
Test name
Test status
Simulation time 70250848 ps
CPU time 1.62 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:15 AM UTC 24
Peak memory 214580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271845542 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.1271845542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2055225652
Short name T1815
Test name
Test status
Simulation time 116685164 ps
CPU time 1.89 seconds
Started Aug 27 07:34:11 AM UTC 24
Finished Aug 27 07:34:14 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055225652 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2055225652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2709485656
Short name T1826
Test name
Test status
Simulation time 27618275 ps
CPU time 1.21 seconds
Started Aug 27 07:34:14 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2709485656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2709485656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.673504806
Short name T1822
Test name
Test status
Simulation time 55650683 ps
CPU time 0.93 seconds
Started Aug 27 07:34:14 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673504806 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.673504806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3875142389
Short name T1823
Test name
Test status
Simulation time 36304674 ps
CPU time 1.02 seconds
Started Aug 27 07:34:14 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875142389 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3875142389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2972573689
Short name T1824
Test name
Test status
Simulation time 218557837 ps
CPU time 1.11 seconds
Started Aug 27 07:34:14 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 213920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972573689 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.2972573689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.2896702824
Short name T1825
Test name
Test status
Simulation time 92797325 ps
CPU time 2.59 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 215308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896702824 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2896702824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1400459337
Short name T1828
Test name
Test status
Simulation time 256234464 ps
CPU time 3.05 seconds
Started Aug 27 07:34:12 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 215308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400459337 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1400459337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2324115907
Short name T1834
Test name
Test status
Simulation time 63033394 ps
CPU time 1.61 seconds
Started Aug 27 07:34:16 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2324115907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2324115907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.4033969001
Short name T243
Test name
Test status
Simulation time 21176942 ps
CPU time 1.07 seconds
Started Aug 27 07:34:15 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033969001 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.4033969001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.2478147503
Short name T1829
Test name
Test status
Simulation time 28065681 ps
CPU time 0.92 seconds
Started Aug 27 07:34:15 AM UTC 24
Finished Aug 27 07:34:17 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478147503 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2478147503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4106124282
Short name T1833
Test name
Test status
Simulation time 95985975 ps
CPU time 1.59 seconds
Started Aug 27 07:34:16 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106124282 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.4106124282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.37727383
Short name T1827
Test name
Test status
Simulation time 92939790 ps
CPU time 1.58 seconds
Started Aug 27 07:34:14 AM UTC 24
Finished Aug 27 07:34:16 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37727383 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.37727383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.905700063
Short name T1835
Test name
Test status
Simulation time 73587299 ps
CPU time 2.2 seconds
Started Aug 27 07:34:15 AM UTC 24
Finished Aug 27 07:34:19 AM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905700063 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
6/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.905700063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1228765694
Short name T1759
Test name
Test status
Simulation time 89173376 ps
CPU time 2.3 seconds
Started Aug 27 07:33:43 AM UTC 24
Finished Aug 27 07:33:46 AM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228765694 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1228765694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2389081774
Short name T238
Test name
Test status
Simulation time 63226896 ps
CPU time 3.35 seconds
Started Aug 27 07:33:42 AM UTC 24
Finished Aug 27 07:33:46 AM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389081774 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2389081774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1167123111
Short name T232
Test name
Test status
Simulation time 46322760 ps
CPU time 1.01 seconds
Started Aug 27 07:33:41 AM UTC 24
Finished Aug 27 07:33:43 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167123111 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1167123111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2067168198
Short name T228
Test name
Test status
Simulation time 48260145 ps
CPU time 1.91 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:47 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2067168198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2067168198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1332810839
Short name T294
Test name
Test status
Simulation time 19187142 ps
CPU time 1 seconds
Started Aug 27 07:33:40 AM UTC 24
Finished Aug 27 07:33:42 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332810839 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1332810839
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2572706013
Short name T244
Test name
Test status
Simulation time 291687540 ps
CPU time 1.5 seconds
Started Aug 27 07:33:43 AM UTC 24
Finished Aug 27 07:33:45 AM UTC 24
Peak memory 214724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572706013 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.2572706013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.3016294960
Short name T1832
Test name
Test status
Simulation time 49305496 ps
CPU time 1.08 seconds
Started Aug 27 07:34:16 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016294960 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3016294960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1897241859
Short name T1831
Test name
Test status
Simulation time 20184512 ps
CPU time 1.05 seconds
Started Aug 27 07:34:16 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897241859 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1897241859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.1660561324
Short name T1830
Test name
Test status
Simulation time 20747659 ps
CPU time 0.96 seconds
Started Aug 27 07:34:16 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660561324 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1660561324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.477683763
Short name T1836
Test name
Test status
Simulation time 22743967 ps
CPU time 0.93 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:19 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477683763 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.477683763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2361444774
Short name T1838
Test name
Test status
Simulation time 25092584 ps
CPU time 0.96 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:19 AM UTC 24
Peak memory 214556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361444774 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2361444774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.2538632029
Short name T1839
Test name
Test status
Simulation time 32318633 ps
CPU time 1.05 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:19 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538632029 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2538632029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.3101201555
Short name T1840
Test name
Test status
Simulation time 17045181 ps
CPU time 1.02 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101201555 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3101201555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.251279071
Short name T1842
Test name
Test status
Simulation time 21590910 ps
CPU time 1.09 seconds
Started Aug 27 07:34:17 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251279071 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.251279071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.2411120552
Short name T1841
Test name
Test status
Simulation time 18008376 ps
CPU time 0.99 seconds
Started Aug 27 07:34:18 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411120552 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2411120552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.2066218447
Short name T1761
Test name
Test status
Simulation time 83186599 ps
CPU time 1.61 seconds
Started Aug 27 07:33:46 AM UTC 24
Finished Aug 27 07:33:48 AM UTC 24
Peak memory 214576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066218447 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2066218447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1551881045
Short name T1763
Test name
Test status
Simulation time 404343507 ps
CPU time 5.81 seconds
Started Aug 27 07:33:46 AM UTC 24
Finished Aug 27 07:33:53 AM UTC 24
Peak memory 215312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551881045 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1551881045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.3659869691
Short name T1760
Test name
Test status
Simulation time 17311840 ps
CPU time 1.09 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:46 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659869691 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3659869691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1525989650
Short name T121
Test name
Test status
Simulation time 38946504 ps
CPU time 1.11 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:49 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1525989650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1525989650
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.4294151249
Short name T120
Test name
Test status
Simulation time 21761021 ps
CPU time 1.1 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:47 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294151249 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.4294151249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.4275390700
Short name T298
Test name
Test status
Simulation time 17084692 ps
CPU time 0.91 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:46 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275390700 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4275390700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2889578482
Short name T245
Test name
Test status
Simulation time 20585450 ps
CPU time 1.35 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:49 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889578482 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.2889578482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.1544534250
Short name T214
Test name
Test status
Simulation time 82122123 ps
CPU time 3 seconds
Started Aug 27 07:33:44 AM UTC 24
Finished Aug 27 07:33:48 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544534250 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1544534250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.639321095
Short name T1843
Test name
Test status
Simulation time 29075115 ps
CPU time 1.01 seconds
Started Aug 27 07:34:18 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639321095 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.639321095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.4014868319
Short name T1846
Test name
Test status
Simulation time 14819335 ps
CPU time 0.99 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014868319 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4014868319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.761540097
Short name T1844
Test name
Test status
Simulation time 17652107 ps
CPU time 0.82 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761540097 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.761540097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.2563753846
Short name T1848
Test name
Test status
Simulation time 31210339 ps
CPU time 1.03 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563753846 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2563753846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.1620123374
Short name T1845
Test name
Test status
Simulation time 109244034 ps
CPU time 0.81 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620123374 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1620123374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.4143144882
Short name T1847
Test name
Test status
Simulation time 31547393 ps
CPU time 0.8 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143144882 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4143144882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.63701727
Short name T1849
Test name
Test status
Simulation time 86776476 ps
CPU time 0.88 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:21 AM UTC 24
Peak memory 214540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63701727 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.63701727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3975710
Short name T1850
Test name
Test status
Simulation time 17617871 ps
CPU time 1.04 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:22 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975710 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3975710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.2248414526
Short name T1851
Test name
Test status
Simulation time 16966304 ps
CPU time 1.07 seconds
Started Aug 27 07:34:19 AM UTC 24
Finished Aug 27 07:34:22 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248414526 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2248414526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.1545725370
Short name T1853
Test name
Test status
Simulation time 20083772 ps
CPU time 0.81 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545725370 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1545725370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3531680056
Short name T235
Test name
Test status
Simulation time 680828802 ps
CPU time 1.79 seconds
Started Aug 27 07:33:49 AM UTC 24
Finished Aug 27 07:33:51 AM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531680056 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3531680056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.919307282
Short name T1769
Test name
Test status
Simulation time 1293162404 ps
CPU time 5.82 seconds
Started Aug 27 07:33:49 AM UTC 24
Finished Aug 27 07:33:56 AM UTC 24
Peak memory 215220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919307282 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.919307282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.330863869
Short name T1762
Test name
Test status
Simulation time 23219131 ps
CPU time 1.09 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:50 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330863869 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.330863869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1004476159
Short name T160
Test name
Test status
Simulation time 75420960 ps
CPU time 1.27 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:52 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1004476159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1004476159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.3363068492
Short name T234
Test name
Test status
Simulation time 44890720 ps
CPU time 1.05 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:50 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363068492 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3363068492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.3538700727
Short name T300
Test name
Test status
Simulation time 18692859 ps
CPU time 0.97 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:49 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538700727 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3538700727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3358453542
Short name T246
Test name
Test status
Simulation time 86671878 ps
CPU time 1.59 seconds
Started Aug 27 07:33:49 AM UTC 24
Finished Aug 27 07:33:51 AM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358453542 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.3358453542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.2206468200
Short name T137
Test name
Test status
Simulation time 135364170 ps
CPU time 3.33 seconds
Started Aug 27 07:33:47 AM UTC 24
Finished Aug 27 07:33:52 AM UTC 24
Peak memory 225480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206468200 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2206468200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.2830967710
Short name T1855
Test name
Test status
Simulation time 19785526 ps
CPU time 1.07 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830967710 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2830967710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.3302253151
Short name T1854
Test name
Test status
Simulation time 15379256 ps
CPU time 0.85 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302253151 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3302253151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3936147868
Short name T1852
Test name
Test status
Simulation time 16907797 ps
CPU time 0.76 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936147868 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3936147868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.2704396929
Short name T1858
Test name
Test status
Simulation time 48030008 ps
CPU time 1 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704396929 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2704396929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.506543988
Short name T1859
Test name
Test status
Simulation time 15595995 ps
CPU time 0.94 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506543988 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.506543988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.417493202
Short name T1857
Test name
Test status
Simulation time 55044514 ps
CPU time 0.89 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417493202 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.417493202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.97973332
Short name T1856
Test name
Test status
Simulation time 43240189 ps
CPU time 0.78 seconds
Started Aug 27 07:34:21 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97973332 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.97973332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.82473901
Short name T1860
Test name
Test status
Simulation time 59300354 ps
CPU time 0.87 seconds
Started Aug 27 07:34:22 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82473901 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.82473901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.1544285756
Short name T1862
Test name
Test status
Simulation time 46503495 ps
CPU time 0.91 seconds
Started Aug 27 07:34:22 AM UTC 24
Finished Aug 27 07:34:24 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544285756 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1544285756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2335947856
Short name T1861
Test name
Test status
Simulation time 55917743 ps
CPU time 0.82 seconds
Started Aug 27 07:34:22 AM UTC 24
Finished Aug 27 07:34:23 AM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335947856 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2335947856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2855170758
Short name T1766
Test name
Test status
Simulation time 32189041 ps
CPU time 1.7 seconds
Started Aug 27 07:33:51 AM UTC 24
Finished Aug 27 07:33:54 AM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2855170758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2855170758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.457386152
Short name T247
Test name
Test status
Simulation time 17942838 ps
CPU time 1.22 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:53 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457386152 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.457386152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2542240723
Short name T292
Test name
Test status
Simulation time 21446110 ps
CPU time 0.95 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:52 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542240723 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2542240723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.352912351
Short name T1764
Test name
Test status
Simulation time 27631618 ps
CPU time 1.69 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:53 AM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352912351 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.352912351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.792821241
Short name T1765
Test name
Test status
Simulation time 67743539 ps
CPU time 2.19 seconds
Started Aug 27 07:33:50 AM UTC 24
Finished Aug 27 07:33:53 AM UTC 24
Peak memory 215304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792821241 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.792821241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4164720087
Short name T1771
Test name
Test status
Simulation time 99727396 ps
CPU time 1.27 seconds
Started Aug 27 07:33:54 AM UTC 24
Finished Aug 27 07:33:57 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4164720087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4164720087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3827602786
Short name T1767
Test name
Test status
Simulation time 59317262 ps
CPU time 0.96 seconds
Started Aug 27 07:33:53 AM UTC 24
Finished Aug 27 07:33:55 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827602786 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3827602786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2720380594
Short name T301
Test name
Test status
Simulation time 45696384 ps
CPU time 0.82 seconds
Started Aug 27 07:33:53 AM UTC 24
Finished Aug 27 07:33:55 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720380594 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2720380594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.204407943
Short name T1770
Test name
Test status
Simulation time 20783057 ps
CPU time 1.26 seconds
Started Aug 27 07:33:54 AM UTC 24
Finished Aug 27 07:33:57 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204407943 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.204407943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.2458252115
Short name T1768
Test name
Test status
Simulation time 195008585 ps
CPU time 1.66 seconds
Started Aug 27 07:33:53 AM UTC 24
Finished Aug 27 07:33:55 AM UTC 24
Peak memory 214760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458252115 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2458252115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1642679448
Short name T219
Test name
Test status
Simulation time 237288204 ps
CPU time 3.35 seconds
Started Aug 27 07:33:53 AM UTC 24
Finished Aug 27 07:33:57 AM UTC 24
Peak memory 215292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642679448 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1642679448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.506231831
Short name T1773
Test name
Test status
Simulation time 23399009 ps
CPU time 1.18 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:33:58 AM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=506231831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.506231831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.479282206
Short name T236
Test name
Test status
Simulation time 48357225 ps
CPU time 0.98 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:33:58 AM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479282206 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.479282206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1017466184
Short name T295
Test name
Test status
Simulation time 15679719 ps
CPU time 0.92 seconds
Started Aug 27 07:33:54 AM UTC 24
Finished Aug 27 07:33:56 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017466184 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1017466184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2730114409
Short name T1774
Test name
Test status
Simulation time 65887013 ps
CPU time 1.17 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:33:58 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730114409 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.2730114409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.4212705745
Short name T1772
Test name
Test status
Simulation time 80473137 ps
CPU time 2.47 seconds
Started Aug 27 07:33:54 AM UTC 24
Finished Aug 27 07:33:58 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212705745 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.4212705745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3770102329
Short name T215
Test name
Test status
Simulation time 588789183 ps
CPU time 3.63 seconds
Started Aug 27 07:33:54 AM UTC 24
Finished Aug 27 07:33:59 AM UTC 24
Peak memory 215296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770102329 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3770102329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2596030457
Short name T1778
Test name
Test status
Simulation time 34687975 ps
CPU time 1.55 seconds
Started Aug 27 07:33:58 AM UTC 24
Finished Aug 27 07:34:00 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2596030457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2596030457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2451883206
Short name T1775
Test name
Test status
Simulation time 22277397 ps
CPU time 1.08 seconds
Started Aug 27 07:33:57 AM UTC 24
Finished Aug 27 07:34:00 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451883206 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2451883206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.4128398727
Short name T296
Test name
Test status
Simulation time 25292486 ps
CPU time 1.01 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:33:58 AM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128398727 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4128398727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.592486921
Short name T1776
Test name
Test status
Simulation time 35641999 ps
CPU time 1.22 seconds
Started Aug 27 07:33:58 AM UTC 24
Finished Aug 27 07:34:00 AM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592486921 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.592486921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.3041623988
Short name T1777
Test name
Test status
Simulation time 67509611 ps
CPU time 2.81 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:34:00 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041623988 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3041623988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1894209325
Short name T217
Test name
Test status
Simulation time 155620098 ps
CPU time 3.26 seconds
Started Aug 27 07:33:56 AM UTC 24
Finished Aug 27 07:34:00 AM UTC 24
Peak memory 215244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894209325 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1894209325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2117348344
Short name T1781
Test name
Test status
Simulation time 81497940 ps
CPU time 1.17 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:01 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2117348344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2117348344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.1139900713
Short name T1779
Test name
Test status
Simulation time 21417849 ps
CPU time 1.13 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:01 AM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139900713 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1139900713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.94216920
Short name T1780
Test name
Test status
Simulation time 21855995 ps
CPU time 1.11 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:01 AM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94216920 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.94216920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.420098468
Short name T1782
Test name
Test status
Simulation time 65744584 ps
CPU time 1.5 seconds
Started Aug 27 07:33:59 AM UTC 24
Finished Aug 27 07:34:02 AM UTC 24
Peak memory 214732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420098468 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.420098468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.232750114
Short name T210
Test name
Test status
Simulation time 50358180 ps
CPU time 2.98 seconds
Started Aug 27 07:33:58 AM UTC 24
Finished Aug 27 07:34:02 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232750114 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.232750114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.1867551382
Short name T213
Test name
Test status
Simulation time 286775699 ps
CPU time 2.63 seconds
Started Aug 27 07:33:58 AM UTC 24
Finished Aug 27 07:34:01 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867551382 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
26/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1867551382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.452283860
Short name T174
Test name
Test status
Simulation time 701438039 ps
CPU time 6.15 seconds
Started Aug 27 07:03:45 AM UTC 24
Finished Aug 27 07:04:10 AM UTC 24
Peak memory 288864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452283860 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.452283860
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.267343794
Short name T166
Test name
Test status
Simulation time 2825071890 ps
CPU time 66.63 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:57 AM UTC 24
Peak memory 633240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267343794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.267343794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.3678405339
Short name T11
Test name
Test status
Simulation time 606001634 ps
CPU time 1.01 seconds
Started Aug 27 07:03:43 AM UTC 24
Finished Aug 27 07:04:02 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678405339 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.3678405339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.633665058
Short name T193
Test name
Test status
Simulation time 6621806022 ps
CPU time 174.08 seconds
Started Aug 27 07:03:43 AM UTC 24
Finished Aug 27 07:06:47 AM UTC 24
Peak memory 1044728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633665058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.633665058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_perf.279332872
Short name T17
Test name
Test status
Simulation time 12740345801 ps
CPU time 29.73 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:20 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279332872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.279332872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.3264810877
Short name T1
Test name
Test status
Simulation time 148173904 ps
CPU time 0.96 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:03:51 AM UTC 24
Peak memory 215984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264810877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3264810877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2007088112
Short name T366
Test name
Test status
Simulation time 1224245711 ps
CPU time 51.05 seconds
Started Aug 27 07:03:42 AM UTC 24
Finished Aug 27 07:04:55 AM UTC 24
Peak memory 340124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007088112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2007088112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.3987883794
Short name T259
Test name
Test status
Simulation time 694515065 ps
CPU time 29.61 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:20 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987883794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3987883794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.281430457
Short name T8
Test name
Test status
Simulation time 3886257607 ps
CPU time 4.34 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:00 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=281430457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.281430457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.1649752759
Short name T4
Test name
Test status
Simulation time 571646893 ps
CPU time 0.98 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:03:56 AM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649752
759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.1649752759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.3620026660
Short name T195
Test name
Test status
Simulation time 3300112662 ps
CPU time 2.83 seconds
Started Aug 27 07:03:52 AM UTC 24
Finished Aug 27 07:04:06 AM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620026
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark
s_acq.3620026660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2728146431
Short name T81
Test name
Test status
Simulation time 95973014 ps
CPU time 0.95 seconds
Started Aug 27 07:03:53 AM UTC 24
Finished Aug 27 07:04:02 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728146
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_tx.2728146431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.2300218247
Short name T229
Test name
Test status
Simulation time 12920324305 ps
CPU time 17.21 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:13 AM UTC 24
Peak memory 704400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2300218247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress
_wr.2300218247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2003234171
Short name T72
Test name
Test status
Simulation time 7004484322 ps
CPU time 2.95 seconds
Started Aug 27 07:03:57 AM UTC 24
Finished Aug 27 07:04:04 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003234
171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.2003234171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_perf.326348856
Short name T7
Test name
Test status
Simulation time 541806020 ps
CPU time 4.27 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:00 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263488
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.326348856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.2905948672
Short name T171
Test name
Test status
Simulation time 1911798658 ps
CPU time 2.05 seconds
Started Aug 27 07:03:56 AM UTC 24
Finished Aug 27 07:04:02 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905948
672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.2905948672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.2145624814
Short name T157
Test name
Test status
Simulation time 4130130369 ps
CPU time 12.29 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:03 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145624814 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.2145624814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.1110310801
Short name T6
Test name
Test status
Simulation time 4741748124 ps
CPU time 7.15 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:03:57 AM UTC 24
Peak memory 231144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110310801 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.1110310801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.148049547
Short name T317
Test name
Test status
Simulation time 14473037250 ps
CPU time 26.02 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:04:17 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148049547 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.148049547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.1262003811
Short name T3
Test name
Test status
Simulation time 259319808 ps
CPU time 4.23 seconds
Started Aug 27 07:03:46 AM UTC 24
Finished Aug 27 07:03:55 AM UTC 24
Peak memory 225344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262003811 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.1262003811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.264616565
Short name T82
Test name
Test status
Simulation time 1363348974 ps
CPU time 6.63 seconds
Started Aug 27 07:03:47 AM UTC 24
Finished Aug 27 07:04:02 AM UTC 24
Peak memory 247920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646165
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.264616565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_alert_test.2780684848
Short name T107
Test name
Test status
Simulation time 17345582 ps
CPU time 0.93 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780684848 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2780684848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.4264551408
Short name T16
Test name
Test status
Simulation time 111086465 ps
CPU time 1.94 seconds
Started Aug 27 07:04:03 AM UTC 24
Finished Aug 27 07:04:06 AM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264551408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.4264551408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.3978857623
Short name T49
Test name
Test status
Simulation time 917897080 ps
CPU time 21.4 seconds
Started Aug 27 07:04:01 AM UTC 24
Finished Aug 27 07:04:24 AM UTC 24
Peak memory 321824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978857623 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.3978857623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.2334296686
Short name T482
Test name
Test status
Simulation time 15126266438 ps
CPU time 204.19 seconds
Started Aug 27 07:04:02 AM UTC 24
Finished Aug 27 07:07:30 AM UTC 24
Peak memory 555276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334296686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2334296686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.1564279392
Short name T149
Test name
Test status
Simulation time 2563778092 ps
CPU time 159.63 seconds
Started Aug 27 07:04:01 AM UTC 24
Finished Aug 27 07:06:43 AM UTC 24
Peak memory 735504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564279392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1564279392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.836127763
Short name T42
Test name
Test status
Simulation time 213642612 ps
CPU time 0.8 seconds
Started Aug 27 07:04:01 AM UTC 24
Finished Aug 27 07:04:03 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836127763 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.836127763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.3306827022
Short name T53
Test name
Test status
Simulation time 384775205 ps
CPU time 4.38 seconds
Started Aug 27 07:04:02 AM UTC 24
Finished Aug 27 07:04:08 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306827022 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.3306827022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.2260974069
Short name T568
Test name
Test status
Simulation time 4765533973 ps
CPU time 277.05 seconds
Started Aug 27 07:04:01 AM UTC 24
Finished Aug 27 07:08:42 AM UTC 24
Peak memory 1435756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260974069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2260974069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_override.1684651880
Short name T78
Test name
Test status
Simulation time 30025101 ps
CPU time 0.61 seconds
Started Aug 27 07:04:01 AM UTC 24
Finished Aug 27 07:04:03 AM UTC 24
Peak memory 215192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684651880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1684651880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_perf.642672852
Short name T678
Test name
Test status
Simulation time 26924099092 ps
CPU time 391.45 seconds
Started Aug 27 07:04:02 AM UTC 24
Finished Aug 27 07:10:39 AM UTC 24
Peak memory 1640664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642672852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.642672852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.2710900250
Short name T12
Test name
Test status
Simulation time 142252038 ps
CPU time 1.37 seconds
Started Aug 27 07:04:02 AM UTC 24
Finished Aug 27 07:04:05 AM UTC 24
Peak memory 238456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710900250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2710900250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.3392137681
Short name T50
Test name
Test status
Simulation time 23507766864 ps
CPU time 24.55 seconds
Started Aug 27 07:03:58 AM UTC 24
Finished Aug 27 07:04:25 AM UTC 24
Peak memory 348584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392137681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3392137681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_stress_all.824562669
Short name T124
Test name
Test status
Simulation time 11600920798 ps
CPU time 267.5 seconds
Started Aug 27 07:04:03 AM UTC 24
Finished Aug 27 07:08:35 AM UTC 24
Peak memory 1364248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824562669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.824562669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.3004499858
Short name T177
Test name
Test status
Simulation time 652627678 ps
CPU time 9.56 seconds
Started Aug 27 07:04:03 AM UTC 24
Finished Aug 27 07:04:14 AM UTC 24
Peak memory 233176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004499858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3004499858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.24806848
Short name T175
Test name
Test status
Simulation time 335861404 ps
CPU time 1.35 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:10 AM UTC 24
Peak memory 246468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24806848 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.24806848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.246731153
Short name T173
Test name
Test status
Simulation time 319425186 ps
CPU time 2.68 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:09 AM UTC 24
Peak memory 216180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467311
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.246731153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.1744418136
Short name T172
Test name
Test status
Simulation time 219307222 ps
CPU time 1.63 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:08 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744418
136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.1744418136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.859227535
Short name T289
Test name
Test status
Simulation time 498090363 ps
CPU time 4.46 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:12 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8592275
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_acq.859227535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.808928340
Short name T176
Test name
Test status
Simulation time 707951449 ps
CPU time 1.81 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:10 AM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8089283
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.808928340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.3444196414
Short name T58
Test name
Test status
Simulation time 6921463325 ps
CPU time 10.67 seconds
Started Aug 27 07:04:03 AM UTC 24
Finished Aug 27 07:04:15 AM UTC 24
Peak memory 227392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444196414 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3444196414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.3901591847
Short name T313
Test name
Test status
Simulation time 893803769 ps
CPU time 6.28 seconds
Started Aug 27 07:04:05 AM UTC 24
Finished Aug 27 07:04:12 AM UTC 24
Peak memory 233164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390159
1847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.3901591847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.252408908
Short name T480
Test name
Test status
Simulation time 16549084382 ps
CPU time 201.5 seconds
Started Aug 27 07:04:05 AM UTC 24
Finished Aug 27 07:07:29 AM UTC 24
Peak memory 3987680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=252408908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.252408908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.2768708880
Short name T73
Test name
Test status
Simulation time 528778638 ps
CPU time 4.07 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:12 AM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768708
880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.2768708880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.3131648595
Short name T76
Test name
Test status
Simulation time 4140356747 ps
CPU time 4.07 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:12 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131648
595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.3131648595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.3920416975
Short name T69
Test name
Test status
Simulation time 346815138 ps
CPU time 1.68 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:10 AM UTC 24
Peak memory 232424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920416
975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_txstretch.3920416975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_perf.1110679400
Short name T312
Test name
Test status
Simulation time 385608103 ps
CPU time 4.9 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:04:12 AM UTC 24
Peak memory 233804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110679
400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.1110679400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.3203779365
Short name T310
Test name
Test status
Simulation time 513441191 ps
CPU time 2.47 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:11 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203779
365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.3203779365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1980709493
Short name T311
Test name
Test status
Simulation time 926351565 ps
CPU time 6.85 seconds
Started Aug 27 07:04:03 AM UTC 24
Finished Aug 27 07:04:11 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980709493 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.1980709493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.422234932
Short name T705
Test name
Test status
Simulation time 29957435708 ps
CPU time 453.77 seconds
Started Aug 27 07:04:06 AM UTC 24
Finished Aug 27 07:11:45 AM UTC 24
Peak memory 4616420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422234
932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.422234932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.1765114123
Short name T84
Test name
Test status
Simulation time 3597707406 ps
CPU time 13.33 seconds
Started Aug 27 07:04:05 AM UTC 24
Finished Aug 27 07:04:19 AM UTC 24
Peak memory 244164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765114
123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.1765114123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.3991029928
Short name T306
Test name
Test status
Simulation time 492574003 ps
CPU time 7.93 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:16 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991029
928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.3991029928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_alert_test.231205870
Short name T437
Test name
Test status
Simulation time 20113412 ps
CPU time 0.94 seconds
Started Aug 27 07:07:17 AM UTC 24
Finished Aug 27 07:07:19 AM UTC 24
Peak memory 213980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231205870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.231205870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.2405658727
Short name T452
Test name
Test status
Simulation time 245593940 ps
CPU time 2.63 seconds
Started Aug 27 07:06:56 AM UTC 24
Finished Aug 27 07:06:59 AM UTC 24
Peak memory 227164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405658727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2405658727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.3433627748
Short name T466
Test name
Test status
Simulation time 331247197 ps
CPU time 19.31 seconds
Started Aug 27 07:06:54 AM UTC 24
Finished Aug 27 07:07:15 AM UTC 24
Peak memory 282648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433627748 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.3433627748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.2719816987
Short name T545
Test name
Test status
Simulation time 11625413672 ps
CPU time 89.13 seconds
Started Aug 27 07:06:54 AM UTC 24
Finished Aug 27 07:08:25 AM UTC 24
Peak memory 299472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719816987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2719816987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2517393414
Short name T543
Test name
Test status
Simulation time 11015123962 ps
CPU time 87.44 seconds
Started Aug 27 07:06:53 AM UTC 24
Finished Aug 27 07:08:23 AM UTC 24
Peak memory 784844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517393414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2517393414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.3978246637
Short name T451
Test name
Test status
Simulation time 336233736 ps
CPU time 1.65 seconds
Started Aug 27 07:06:54 AM UTC 24
Finished Aug 27 07:06:57 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978246637 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.3978246637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.1050925825
Short name T459
Test name
Test status
Simulation time 1406881276 ps
CPU time 14.14 seconds
Started Aug 27 07:06:54 AM UTC 24
Finished Aug 27 07:07:10 AM UTC 24
Peak memory 258084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050925825 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.1050925825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.2022286765
Short name T123
Test name
Test status
Simulation time 10895221755 ps
CPU time 55.76 seconds
Started Aug 27 07:06:53 AM UTC 24
Finished Aug 27 07:07:50 AM UTC 24
Peak memory 911508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022286765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2022286765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_mode_toggle.2040205585
Short name T465
Test name
Test status
Simulation time 254032133 ps
CPU time 1.53 seconds
Started Aug 27 07:07:12 AM UTC 24
Finished Aug 27 07:07:15 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040205585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2040205585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_override.2652280695
Short name T446
Test name
Test status
Simulation time 47901349 ps
CPU time 1.01 seconds
Started Aug 27 07:06:52 AM UTC 24
Finished Aug 27 07:06:54 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652280695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2652280695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_perf.3899714123
Short name T457
Test name
Test status
Simulation time 711497044 ps
CPU time 11.07 seconds
Started Aug 27 07:06:55 AM UTC 24
Finished Aug 27 07:07:07 AM UTC 24
Peak memory 309332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899714123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.3899714123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.3931284135
Short name T455
Test name
Test status
Simulation time 134797866 ps
CPU time 4.13 seconds
Started Aug 27 07:06:56 AM UTC 24
Finished Aug 27 07:07:01 AM UTC 24
Peak memory 232836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931284135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3931284135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.569956555
Short name T477
Test name
Test status
Simulation time 4253920866 ps
CPU time 28.84 seconds
Started Aug 27 07:06:52 AM UTC 24
Finished Aug 27 07:07:22 AM UTC 24
Peak memory 326052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569956555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.569956555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.2982269183
Short name T467
Test name
Test status
Simulation time 561030279 ps
CPU time 3.8 seconds
Started Aug 27 07:07:11 AM UTC 24
Finished Aug 27 07:07:16 AM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2982269183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.2982269183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.3080784946
Short name T460
Test name
Test status
Simulation time 204232716 ps
CPU time 1.13 seconds
Started Aug 27 07:07:08 AM UTC 24
Finished Aug 27 07:07:10 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080784
946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.3080784946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.2586659204
Short name T461
Test name
Test status
Simulation time 137025502 ps
CPU time 1.76 seconds
Started Aug 27 07:07:08 AM UTC 24
Finished Aug 27 07:07:10 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586659
204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.2586659204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.257914226
Short name T471
Test name
Test status
Simulation time 3623097601 ps
CPU time 5.58 seconds
Started Aug 27 07:07:12 AM UTC 24
Finished Aug 27 07:07:19 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579142
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_acq.257914226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.3681052925
Short name T470
Test name
Test status
Simulation time 558917618 ps
CPU time 2.32 seconds
Started Aug 27 07:07:13 AM UTC 24
Finished Aug 27 07:07:17 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681052
925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_tx.3681052925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.2239143565
Short name T444
Test name
Test status
Simulation time 912397957 ps
CPU time 8.22 seconds
Started Aug 27 07:07:01 AM UTC 24
Finished Aug 27 07:07:11 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223914
3565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.2239143565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.491550554
Short name T503
Test name
Test status
Simulation time 14517605991 ps
CPU time 44.51 seconds
Started Aug 27 07:07:02 AM UTC 24
Finished Aug 27 07:07:48 AM UTC 24
Peak memory 915608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=491550554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stress
_wr.491550554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.3921972603
Short name T475
Test name
Test status
Simulation time 427285233 ps
CPU time 4.31 seconds
Started Aug 27 07:07:15 AM UTC 24
Finished Aug 27 07:07:21 AM UTC 24
Peak memory 227076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921972
603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.3921972603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.2861991357
Short name T473
Test name
Test status
Simulation time 547866121 ps
CPU time 3 seconds
Started Aug 27 07:07:16 AM UTC 24
Finished Aug 27 07:07:19 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861991
357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad
dr.2861991357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_perf.2534660303
Short name T468
Test name
Test status
Simulation time 5381087545 ps
CPU time 6.08 seconds
Started Aug 27 07:07:09 AM UTC 24
Finished Aug 27 07:07:16 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534660
303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.2534660303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.1850235169
Short name T474
Test name
Test status
Simulation time 4513889024 ps
CPU time 4 seconds
Started Aug 27 07:07:14 AM UTC 24
Finished Aug 27 07:07:20 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850235
169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.1850235169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.4203983295
Short name T463
Test name
Test status
Simulation time 1603172473 ps
CPU time 12.33 seconds
Started Aug 27 07:06:58 AM UTC 24
Finished Aug 27 07:07:11 AM UTC 24
Peak memory 218740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203983295 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.4203983295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.4186326423
Short name T1249
Test name
Test status
Simulation time 53076055038 ps
CPU time 880.32 seconds
Started Aug 27 07:07:11 AM UTC 24
Finished Aug 27 07:22:00 AM UTC 24
Peak memory 10230028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418632
6423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.4186326423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.3335582993
Short name T469
Test name
Test status
Simulation time 3531584402 ps
CPU time 15.82 seconds
Started Aug 27 07:06:59 AM UTC 24
Finished Aug 27 07:07:16 AM UTC 24
Peak memory 233072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335582993 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.3335582993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.1936921563
Short name T759
Test name
Test status
Simulation time 46868136154 ps
CPU time 290.88 seconds
Started Aug 27 07:06:59 AM UTC 24
Finished Aug 27 07:11:54 AM UTC 24
Peak memory 3551316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936921563 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.1936921563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.2157313801
Short name T476
Test name
Test status
Simulation time 3345449168 ps
CPU time 19.45 seconds
Started Aug 27 07:07:00 AM UTC 24
Finished Aug 27 07:07:21 AM UTC 24
Peak memory 301472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157313801 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.2157313801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.1423472297
Short name T464
Test name
Test status
Simulation time 2021803840 ps
CPU time 9.5 seconds
Started Aug 27 07:07:02 AM UTC 24
Finished Aug 27 07:07:13 AM UTC 24
Peak memory 233536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423472
297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.1423472297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.2409436841
Short name T472
Test name
Test status
Simulation time 138900673 ps
CPU time 3.77 seconds
Started Aug 27 07:07:14 AM UTC 24
Finished Aug 27 07:07:19 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409436
841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2409436841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_alert_test.2256524535
Short name T501
Test name
Test status
Simulation time 47251159 ps
CPU time 0.95 seconds
Started Aug 27 07:07:46 AM UTC 24
Finished Aug 27 07:07:48 AM UTC 24
Peak memory 214072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256524535 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2256524535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.1704057642
Short name T490
Test name
Test status
Simulation time 285027623 ps
CPU time 16 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:07:38 AM UTC 24
Peak memory 272228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704057642 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.1704057642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.2991894221
Short name T564
Test name
Test status
Simulation time 13632760780 ps
CPU time 77.55 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:08:40 AM UTC 24
Peak memory 544972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991894221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2991894221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.2271734210
Short name T645
Test name
Test status
Simulation time 9579625299 ps
CPU time 162.58 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:10:06 AM UTC 24
Peak memory 831192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271734210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2271734210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.1204960947
Short name T478
Test name
Test status
Simulation time 384172595 ps
CPU time 1.58 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:07:23 AM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204960947 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.1204960947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.1881971671
Short name T485
Test name
Test status
Simulation time 200679541 ps
CPU time 13.83 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:07:36 AM UTC 24
Peak memory 252216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881971671 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.1881971671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.3453548997
Short name T597
Test name
Test status
Simulation time 4374584500 ps
CPU time 111.32 seconds
Started Aug 27 07:07:18 AM UTC 24
Finished Aug 27 07:09:11 AM UTC 24
Peak memory 1335372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453548997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3453548997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.2139734597
Short name T499
Test name
Test status
Simulation time 1510174755 ps
CPU time 5.67 seconds
Started Aug 27 07:07:39 AM UTC 24
Finished Aug 27 07:07:46 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139734597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2139734597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_override.192812169
Short name T153
Test name
Test status
Simulation time 63942297 ps
CPU time 1.04 seconds
Started Aug 27 07:07:18 AM UTC 24
Finished Aug 27 07:07:20 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192812169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.192812169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_perf.2925837604
Short name T500
Test name
Test status
Simulation time 6211930131 ps
CPU time 24.48 seconds
Started Aug 27 07:07:20 AM UTC 24
Finished Aug 27 07:07:46 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925837604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2925837604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.1632505342
Short name T560
Test name
Test status
Simulation time 2201704117 ps
CPU time 78.79 seconds
Started Aug 27 07:07:17 AM UTC 24
Finished Aug 27 07:08:38 AM UTC 24
Peak memory 397416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632505342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1632505342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.2986157841
Short name T484
Test name
Test status
Simulation time 650401240 ps
CPU time 12.23 seconds
Started Aug 27 07:07:22 AM UTC 24
Finished Aug 27 07:07:35 AM UTC 24
Peak memory 228816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986157841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2986157841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.1080913711
Short name T303
Test name
Test status
Simulation time 625240623 ps
CPU time 5.6 seconds
Started Aug 27 07:07:38 AM UTC 24
Finished Aug 27 07:07:44 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1080913711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_ad
dr.1080913711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.305848961
Short name T492
Test name
Test status
Simulation time 182463114 ps
CPU time 2.04 seconds
Started Aug 27 07:07:35 AM UTC 24
Finished Aug 27 07:07:38 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058489
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.305848961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.3989431271
Short name T493
Test name
Test status
Simulation time 230639920 ps
CPU time 1.38 seconds
Started Aug 27 07:07:37 AM UTC 24
Finished Aug 27 07:07:39 AM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989431
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.3989431271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.1448690833
Short name T497
Test name
Test status
Simulation time 1305226170 ps
CPU time 3.75 seconds
Started Aug 27 07:07:39 AM UTC 24
Finished Aug 27 07:07:44 AM UTC 24
Peak memory 216680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448690
833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.1448690833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.3329300315
Short name T496
Test name
Test status
Simulation time 550732788 ps
CPU time 2.18 seconds
Started Aug 27 07:07:40 AM UTC 24
Finished Aug 27 07:07:43 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329300
315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermark
s_tx.3329300315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_hrst.159663361
Short name T495
Test name
Test status
Simulation time 3158672399 ps
CPU time 3.4 seconds
Started Aug 27 07:07:39 AM UTC 24
Finished Aug 27 07:07:43 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596633
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.159663361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.3205005461
Short name T486
Test name
Test status
Simulation time 441728303 ps
CPU time 4.99 seconds
Started Aug 27 07:07:30 AM UTC 24
Finished Aug 27 07:07:36 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320500
5461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.3205005461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.3978747108
Short name T764
Test name
Test status
Simulation time 17895334319 ps
CPU time 263.44 seconds
Started Aug 27 07:07:31 AM UTC 24
Finished Aug 27 07:11:58 AM UTC 24
Peak memory 4264348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3978747108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres
s_wr.3978747108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.3053798766
Short name T511
Test name
Test status
Simulation time 2267147568 ps
CPU time 5.21 seconds
Started Aug 27 07:07:44 AM UTC 24
Finished Aug 27 07:07:51 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053798
766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.3053798766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.3670879513
Short name T509
Test name
Test status
Simulation time 597960713 ps
CPU time 5.1 seconds
Started Aug 27 07:07:44 AM UTC 24
Finished Aug 27 07:07:51 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670879
513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.3670879513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_nack_txstretch.3708775280
Short name T505
Test name
Test status
Simulation time 139225929 ps
CPU time 2.04 seconds
Started Aug 27 07:07:46 AM UTC 24
Finished Aug 27 07:07:49 AM UTC 24
Peak memory 233244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708775
280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_txstretch.3708775280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_perf.3827417553
Short name T498
Test name
Test status
Simulation time 1045652485 ps
CPU time 6.21 seconds
Started Aug 27 07:07:38 AM UTC 24
Finished Aug 27 07:07:45 AM UTC 24
Peak memory 228872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827417
553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.3827417553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.374832365
Short name T506
Test name
Test status
Simulation time 465567592 ps
CPU time 3.69 seconds
Started Aug 27 07:07:44 AM UTC 24
Finished Aug 27 07:07:49 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748323
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.374832365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.1904227233
Short name T519
Test name
Test status
Simulation time 3663608578 ps
CPU time 32.62 seconds
Started Aug 27 07:07:24 AM UTC 24
Finished Aug 27 07:07:58 AM UTC 24
Peak memory 233736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904227233 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.1904227233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.4247939186
Short name T540
Test name
Test status
Simulation time 54960951937 ps
CPU time 38.56 seconds
Started Aug 27 07:07:38 AM UTC 24
Finished Aug 27 07:08:18 AM UTC 24
Peak memory 473248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424793
9186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.4247939186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.3591206776
Short name T520
Test name
Test status
Simulation time 870615346 ps
CPU time 29.28 seconds
Started Aug 27 07:07:28 AM UTC 24
Finished Aug 27 07:07:59 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591206776 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.3591206776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.2657219168
Short name T556
Test name
Test status
Simulation time 42542263781 ps
CPU time 68.46 seconds
Started Aug 27 07:07:26 AM UTC 24
Finished Aug 27 07:08:36 AM UTC 24
Peak memory 1376476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657219168 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.2657219168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.2473203243
Short name T488
Test name
Test status
Simulation time 1665111421 ps
CPU time 6.5 seconds
Started Aug 27 07:07:29 AM UTC 24
Finished Aug 27 07:07:37 AM UTC 24
Peak memory 292960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473203243 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.2473203243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.3776470083
Short name T494
Test name
Test status
Simulation time 1269250227 ps
CPU time 8.6 seconds
Started Aug 27 07:07:32 AM UTC 24
Finished Aug 27 07:07:42 AM UTC 24
Peak memory 233264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776470
083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.3776470083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.2840894451
Short name T512
Test name
Test status
Simulation time 402956337 ps
CPU time 7.28 seconds
Started Aug 27 07:07:43 AM UTC 24
Finished Aug 27 07:07:52 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840894
451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.2840894451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_alert_test.3514313898
Short name T487
Test name
Test status
Simulation time 42838089 ps
CPU time 0.89 seconds
Started Aug 27 07:08:11 AM UTC 24
Finished Aug 27 07:08:13 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514313898 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3514313898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.1847089141
Short name T517
Test name
Test status
Simulation time 469290827 ps
CPU time 2.41 seconds
Started Aug 27 07:07:53 AM UTC 24
Finished Aug 27 07:07:56 AM UTC 24
Peak memory 230936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847089141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1847089141
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.3984743842
Short name T516
Test name
Test status
Simulation time 771274769 ps
CPU time 5.64 seconds
Started Aug 27 07:07:49 AM UTC 24
Finished Aug 27 07:07:56 AM UTC 24
Peak memory 244036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984743842 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.3984743842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2841092185
Short name T693
Test name
Test status
Simulation time 8427165268 ps
CPU time 175.91 seconds
Started Aug 27 07:07:50 AM UTC 24
Finished Aug 27 07:10:49 AM UTC 24
Peak memory 624880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841092185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2841092185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.657977477
Short name T649
Test name
Test status
Simulation time 15737349505 ps
CPU time 137.75 seconds
Started Aug 27 07:07:49 AM UTC 24
Finished Aug 27 07:10:09 AM UTC 24
Peak memory 759952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657977477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.657977477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.3330289473
Short name T513
Test name
Test status
Simulation time 236774522 ps
CPU time 1.74 seconds
Started Aug 27 07:07:49 AM UTC 24
Finished Aug 27 07:07:52 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330289473 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.3330289473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.871680095
Short name T518
Test name
Test status
Simulation time 403022318 ps
CPU time 5.7 seconds
Started Aug 27 07:07:50 AM UTC 24
Finished Aug 27 07:07:57 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871680095 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.871680095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.3874586068
Short name T810
Test name
Test status
Simulation time 5314164040 ps
CPU time 287.54 seconds
Started Aug 27 07:07:49 AM UTC 24
Finished Aug 27 07:12:40 AM UTC 24
Peak memory 1423776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874586068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3874586068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.1669202579
Short name T557
Test name
Test status
Simulation time 684585671 ps
CPU time 28 seconds
Started Aug 27 07:08:07 AM UTC 24
Finished Aug 27 07:08:36 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669202579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1669202579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_mode_toggle.151885771
Short name T508
Test name
Test status
Simulation time 379848278 ps
CPU time 3.58 seconds
Started Aug 27 07:08:07 AM UTC 24
Finished Aug 27 07:08:12 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151885771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.151885771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_override.2947590868
Short name T507
Test name
Test status
Simulation time 55386870 ps
CPU time 1.02 seconds
Started Aug 27 07:07:48 AM UTC 24
Finished Aug 27 07:07:50 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947590868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2947590868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_perf.789872533
Short name T1031
Test name
Test status
Simulation time 27040418391 ps
CPU time 530.35 seconds
Started Aug 27 07:07:51 AM UTC 24
Finished Aug 27 07:16:48 AM UTC 24
Peak memory 268492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789872533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.789872533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.2800896852
Short name T515
Test name
Test status
Simulation time 85541068 ps
CPU time 2.93 seconds
Started Aug 27 07:07:51 AM UTC 24
Finished Aug 27 07:07:55 AM UTC 24
Peak memory 233268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800896852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2800896852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.2410121826
Short name T502
Test name
Test status
Simulation time 1527510881 ps
CPU time 29.29 seconds
Started Aug 27 07:07:47 AM UTC 24
Finished Aug 27 07:08:17 AM UTC 24
Peak memory 348256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410121826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2410121826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.1190680819
Short name T491
Test name
Test status
Simulation time 864554679 ps
CPU time 18.11 seconds
Started Aug 27 07:07:51 AM UTC 24
Finished Aug 27 07:08:11 AM UTC 24
Peak memory 232848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190680819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1190680819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.1764258960
Short name T504
Test name
Test status
Simulation time 1107006972 ps
CPU time 9.96 seconds
Started Aug 27 07:08:05 AM UTC 24
Finished Aug 27 07:08:16 AM UTC 24
Peak memory 233468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1764258960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.1764258960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.1138913646
Short name T523
Test name
Test status
Simulation time 341347494 ps
CPU time 1.19 seconds
Started Aug 27 07:08:01 AM UTC 24
Finished Aug 27 07:08:03 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138913
646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.1138913646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.3004164648
Short name T525
Test name
Test status
Simulation time 406316838 ps
CPU time 1.7 seconds
Started Aug 27 07:08:03 AM UTC 24
Finished Aug 27 07:08:05 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004164
648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.3004164648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.2662459122
Short name T533
Test name
Test status
Simulation time 2884723734 ps
CPU time 3.17 seconds
Started Aug 27 07:08:09 AM UTC 24
Finished Aug 27 07:08:13 AM UTC 24
Peak memory 216948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662459
122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermar
ks_acq.2662459122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.2767045887
Short name T510
Test name
Test status
Simulation time 81655538 ps
CPU time 1.34 seconds
Started Aug 27 07:08:09 AM UTC 24
Finished Aug 27 07:08:11 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767045
887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_tx.2767045887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.2650377572
Short name T530
Test name
Test status
Simulation time 204336980 ps
CPU time 2.36 seconds
Started Aug 27 07:08:06 AM UTC 24
Finished Aug 27 07:08:09 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650377
572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.2650377572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.43581321
Short name T524
Test name
Test status
Simulation time 2778870463 ps
CPU time 5.96 seconds
Started Aug 27 07:07:57 AM UTC 24
Finished Aug 27 07:08:04 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435813
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.43581321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.3928399743
Short name T748
Test name
Test status
Simulation time 19061005154 ps
CPU time 222.96 seconds
Started Aug 27 07:07:58 AM UTC 24
Finished Aug 27 07:11:44 AM UTC 24
Peak memory 3102940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3928399743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.3928399743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2203306752
Short name T537
Test name
Test status
Simulation time 1926072194 ps
CPU time 4.2 seconds
Started Aug 27 07:08:10 AM UTC 24
Finished Aug 27 07:08:15 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203306
752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.2203306752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.769708461
Short name T536
Test name
Test status
Simulation time 449181214 ps
CPU time 2.97 seconds
Started Aug 27 07:08:11 AM UTC 24
Finished Aug 27 07:08:15 AM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7697084
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_addr.769708461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_nack_txstretch.884949737
Short name T534
Test name
Test status
Simulation time 1520956660 ps
CPU time 1.66 seconds
Started Aug 27 07:08:11 AM UTC 24
Finished Aug 27 07:08:14 AM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8849497
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_txstretch.884949737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_perf.1861661784
Short name T531
Test name
Test status
Simulation time 6256215861 ps
CPU time 6.12 seconds
Started Aug 27 07:08:03 AM UTC 24
Finished Aug 27 07:08:10 AM UTC 24
Peak memory 233276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861661
784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.1861661784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.3204432242
Short name T535
Test name
Test status
Simulation time 458614348 ps
CPU time 4.36 seconds
Started Aug 27 07:08:09 AM UTC 24
Finished Aug 27 07:08:14 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204432
242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.3204432242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.3315321808
Short name T526
Test name
Test status
Simulation time 4776910157 ps
CPU time 11.8 seconds
Started Aug 27 07:07:53 AM UTC 24
Finished Aug 27 07:08:06 AM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315321808 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.3315321808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.1543753176
Short name T611
Test name
Test status
Simulation time 40694766718 ps
CPU time 89.73 seconds
Started Aug 27 07:08:04 AM UTC 24
Finished Aug 27 07:09:35 AM UTC 24
Peak memory 752076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154375
3176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.1543753176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.3858264772
Short name T527
Test name
Test status
Simulation time 350460927 ps
CPU time 8.65 seconds
Started Aug 27 07:07:56 AM UTC 24
Finished Aug 27 07:08:06 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858264772 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.3858264772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.2750144415
Short name T489
Test name
Test status
Simulation time 23215143503 ps
CPU time 21.78 seconds
Started Aug 27 07:07:53 AM UTC 24
Finished Aug 27 07:08:16 AM UTC 24
Peak memory 237728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750144415 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.2750144415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.335591213
Short name T522
Test name
Test status
Simulation time 5696269919 ps
CPU time 3.35 seconds
Started Aug 27 07:07:57 AM UTC 24
Finished Aug 27 07:08:01 AM UTC 24
Peak memory 264592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335591213 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.335591213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3478084010
Short name T304
Test name
Test status
Simulation time 1370346865 ps
CPU time 10.09 seconds
Started Aug 27 07:07:59 AM UTC 24
Finished Aug 27 07:08:10 AM UTC 24
Peak memory 226920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478084
010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.3478084010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.3629732702
Short name T538
Test name
Test status
Simulation time 142274551 ps
CPU time 5.67 seconds
Started Aug 27 07:08:09 AM UTC 24
Finished Aug 27 07:08:16 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629732
702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3629732702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_alert_test.4174195007
Short name T563
Test name
Test status
Simulation time 46871936 ps
CPU time 0.91 seconds
Started Aug 27 07:08:37 AM UTC 24
Finished Aug 27 07:08:39 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174195007 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.4174195007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.2235733470
Short name T544
Test name
Test status
Simulation time 423413206 ps
CPU time 9.58 seconds
Started Aug 27 07:08:15 AM UTC 24
Finished Aug 27 07:08:25 AM UTC 24
Peak memory 256088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235733470 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.2235733470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.2143765747
Short name T639
Test name
Test status
Simulation time 3583364615 ps
CPU time 99.79 seconds
Started Aug 27 07:08:16 AM UTC 24
Finished Aug 27 07:09:58 AM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143765747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2143765747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.1632165271
Short name T581
Test name
Test status
Simulation time 3967724392 ps
CPU time 46.97 seconds
Started Aug 27 07:08:14 AM UTC 24
Finished Aug 27 07:09:02 AM UTC 24
Peak memory 700640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632165271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1632165271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.1976227793
Short name T539
Test name
Test status
Simulation time 74638670 ps
CPU time 1.53 seconds
Started Aug 27 07:08:15 AM UTC 24
Finished Aug 27 07:08:17 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976227793 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.1976227793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.1847889797
Short name T547
Test name
Test status
Simulation time 182415600 ps
CPU time 11.26 seconds
Started Aug 27 07:08:15 AM UTC 24
Finished Aug 27 07:08:27 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847889797 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.1847889797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.1835921459
Short name T653
Test name
Test status
Simulation time 9328294343 ps
CPU time 115.25 seconds
Started Aug 27 07:08:14 AM UTC 24
Finished Aug 27 07:10:11 AM UTC 24
Peak memory 1384708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835921459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1835921459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.1350250059
Short name T263
Test name
Test status
Simulation time 1274706117 ps
CPU time 25.64 seconds
Started Aug 27 07:08:31 AM UTC 24
Finished Aug 27 07:08:58 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350250059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1350250059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_override.2078449176
Short name T152
Test name
Test status
Simulation time 113108434 ps
CPU time 0.95 seconds
Started Aug 27 07:08:13 AM UTC 24
Finished Aug 27 07:08:14 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078449176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2078449176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_perf.1791653914
Short name T532
Test name
Test status
Simulation time 527861024 ps
CPU time 5.5 seconds
Started Aug 27 07:08:16 AM UTC 24
Finished Aug 27 07:08:22 AM UTC 24
Peak memory 243840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791653914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1791653914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.3605011979
Short name T542
Test name
Test status
Simulation time 33323538 ps
CPU time 1.9 seconds
Started Aug 27 07:08:17 AM UTC 24
Finished Aug 27 07:08:20 AM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605011979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.3605011979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.949772369
Short name T623
Test name
Test status
Simulation time 2458330061 ps
CPU time 87.05 seconds
Started Aug 27 07:08:12 AM UTC 24
Finished Aug 27 07:09:41 AM UTC 24
Peak memory 311756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949772369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.949772369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1625576220
Short name T546
Test name
Test status
Simulation time 387736185 ps
CPU time 8.81 seconds
Started Aug 27 07:08:17 AM UTC 24
Finished Aug 27 07:08:27 AM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625576220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1625576220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.3046783469
Short name T555
Test name
Test status
Simulation time 2368450151 ps
CPU time 6.29 seconds
Started Aug 27 07:08:28 AM UTC 24
Finished Aug 27 07:08:36 AM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3046783469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_ad
dr.3046783469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.3736218711
Short name T550
Test name
Test status
Simulation time 235462441 ps
CPU time 2.37 seconds
Started Aug 27 07:08:26 AM UTC 24
Finished Aug 27 07:08:30 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736218
711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.3736218711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.1811651842
Short name T548
Test name
Test status
Simulation time 303654232 ps
CPU time 1.8 seconds
Started Aug 27 07:08:26 AM UTC 24
Finished Aug 27 07:08:29 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811651
842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.1811651842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.608869763
Short name T561
Test name
Test status
Simulation time 496977826 ps
CPU time 4.58 seconds
Started Aug 27 07:08:33 AM UTC 24
Finished Aug 27 07:08:38 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6088697
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_acq.608869763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.3722043212
Short name T558
Test name
Test status
Simulation time 148637525 ps
CPU time 2.01 seconds
Started Aug 27 07:08:34 AM UTC 24
Finished Aug 27 07:08:37 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722043
212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_tx.3722043212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.4159232834
Short name T551
Test name
Test status
Simulation time 1120234565 ps
CPU time 10.14 seconds
Started Aug 27 07:08:21 AM UTC 24
Finished Aug 27 07:08:32 AM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415923
2834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.4159232834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.1104747406
Short name T603
Test name
Test status
Simulation time 23437881035 ps
CPU time 60.3 seconds
Started Aug 27 07:08:23 AM UTC 24
Finished Aug 27 07:09:25 AM UTC 24
Peak memory 1366164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1104747406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stres
s_wr.1104747406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.1756889100
Short name T567
Test name
Test status
Simulation time 2120605615 ps
CPU time 4.34 seconds
Started Aug 27 07:08:36 AM UTC 24
Finished Aug 27 07:08:41 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756889
100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.1756889100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.1249579316
Short name T570
Test name
Test status
Simulation time 1112861307 ps
CPU time 5.79 seconds
Started Aug 27 07:08:37 AM UTC 24
Finished Aug 27 07:08:44 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249579
316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.1249579316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_perf.3724651689
Short name T559
Test name
Test status
Simulation time 2641583257 ps
CPU time 7.6 seconds
Started Aug 27 07:08:28 AM UTC 24
Finished Aug 27 07:08:37 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724651
689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.3724651689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.659304085
Short name T562
Test name
Test status
Simulation time 1701551464 ps
CPU time 2.42 seconds
Started Aug 27 07:08:36 AM UTC 24
Finished Aug 27 07:08:39 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6593040
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.659304085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.482996789
Short name T552
Test name
Test status
Simulation time 618733362 ps
CPU time 13.43 seconds
Started Aug 27 07:08:18 AM UTC 24
Finished Aug 27 07:08:33 AM UTC 24
Peak memory 233508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482996789 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.482996789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.1078649869
Short name T609
Test name
Test status
Simulation time 32212950867 ps
CPU time 63.05 seconds
Started Aug 27 07:08:28 AM UTC 24
Finished Aug 27 07:09:33 AM UTC 24
Peak memory 293276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107864
9869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.1078649869
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.2198216299
Short name T574
Test name
Test status
Simulation time 1483997290 ps
CPU time 27.55 seconds
Started Aug 27 07:08:20 AM UTC 24
Finished Aug 27 07:08:48 AM UTC 24
Peak memory 245932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198216299 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.2198216299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.1105774084
Short name T1166
Test name
Test status
Simulation time 50025367900 ps
CPU time 710.51 seconds
Started Aug 27 07:08:19 AM UTC 24
Finished Aug 27 07:20:16 AM UTC 24
Peak memory 7667804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105774084 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.1105774084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.3072439977
Short name T553
Test name
Test status
Simulation time 5061370223 ps
CPU time 13.9 seconds
Started Aug 27 07:08:20 AM UTC 24
Finished Aug 27 07:08:35 AM UTC 24
Peak memory 446612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072439977 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.3072439977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.2621705613
Short name T554
Test name
Test status
Simulation time 1143675842 ps
CPU time 9.9 seconds
Started Aug 27 07:08:24 AM UTC 24
Finished Aug 27 07:08:35 AM UTC 24
Peak memory 227112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621705
613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.2621705613
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.2774506853
Short name T571
Test name
Test status
Simulation time 479113227 ps
CPU time 8.14 seconds
Started Aug 27 07:08:35 AM UTC 24
Finished Aug 27 07:08:44 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774506
853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2774506853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_alert_test.2757613075
Short name T593
Test name
Test status
Simulation time 17728475 ps
CPU time 0.89 seconds
Started Aug 27 07:09:07 AM UTC 24
Finished Aug 27 07:09:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757613075 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2757613075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1613956400
Short name T573
Test name
Test status
Simulation time 633465381 ps
CPU time 4.07 seconds
Started Aug 27 07:08:42 AM UTC 24
Finished Aug 27 07:08:47 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613956400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1613956400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.3925180718
Short name T586
Test name
Test status
Simulation time 1214812189 ps
CPU time 22.49 seconds
Started Aug 27 07:08:41 AM UTC 24
Finished Aug 27 07:09:05 AM UTC 24
Peak memory 297248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925180718 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.3925180718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.3921268788
Short name T613
Test name
Test status
Simulation time 3272056335 ps
CPU time 107.22 seconds
Started Aug 27 07:08:41 AM UTC 24
Finished Aug 27 07:10:31 AM UTC 24
Peak memory 596240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921268788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3921268788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.3499955791
Short name T607
Test name
Test status
Simulation time 23653300940 ps
CPU time 51.09 seconds
Started Aug 27 07:08:39 AM UTC 24
Finished Aug 27 07:09:31 AM UTC 24
Peak memory 718992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499955791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3499955791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.3581609145
Short name T569
Test name
Test status
Simulation time 593002043 ps
CPU time 2.02 seconds
Started Aug 27 07:08:40 AM UTC 24
Finished Aug 27 07:08:43 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581609145 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.3581609145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.129161281
Short name T579
Test name
Test status
Simulation time 1109372582 ps
CPU time 14.69 seconds
Started Aug 27 07:08:41 AM UTC 24
Finished Aug 27 07:08:57 AM UTC 24
Peak memory 249988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129161281 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.129161281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.1559788281
Short name T665
Test name
Test status
Simulation time 10422289938 ps
CPU time 95.13 seconds
Started Aug 27 07:08:38 AM UTC 24
Finished Aug 27 07:10:16 AM UTC 24
Peak memory 1149072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559788281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1559788281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.1019160096
Short name T269
Test name
Test status
Simulation time 476606311 ps
CPU time 11.52 seconds
Started Aug 27 07:09:03 AM UTC 24
Finished Aug 27 07:09:15 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019160096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1019160096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_override.2551801237
Short name T275
Test name
Test status
Simulation time 17225723 ps
CPU time 0.99 seconds
Started Aug 27 07:08:37 AM UTC 24
Finished Aug 27 07:08:39 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551801237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2551801237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_perf.3593413136
Short name T615
Test name
Test status
Simulation time 2843458362 ps
CPU time 55.34 seconds
Started Aug 27 07:08:41 AM UTC 24
Finished Aug 27 07:09:38 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593413136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3593413136
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.721868177
Short name T601
Test name
Test status
Simulation time 6463725142 ps
CPU time 32.49 seconds
Started Aug 27 07:08:42 AM UTC 24
Finished Aug 27 07:09:16 AM UTC 24
Peak memory 608196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721868177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.721868177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.2275684596
Short name T585
Test name
Test status
Simulation time 2625718316 ps
CPU time 25.51 seconds
Started Aug 27 07:08:37 AM UTC 24
Finished Aug 27 07:09:04 AM UTC 24
Peak memory 282752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275684596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2275684596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.1107717186
Short name T577
Test name
Test status
Simulation time 479319821 ps
CPU time 8.76 seconds
Started Aug 27 07:08:42 AM UTC 24
Finished Aug 27 07:08:52 AM UTC 24
Peak memory 233388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107717186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1107717186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.194135531
Short name T587
Test name
Test status
Simulation time 4039264757 ps
CPU time 7.43 seconds
Started Aug 27 07:08:57 AM UTC 24
Finished Aug 27 07:09:06 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=194135531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.194135531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.2526576729
Short name T308
Test name
Test status
Simulation time 348387545 ps
CPU time 4.21 seconds
Started Aug 27 07:08:55 AM UTC 24
Finished Aug 27 07:09:00 AM UTC 24
Peak memory 225268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526576
729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.2526576729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.1378909023
Short name T592
Test name
Test status
Simulation time 4725378372 ps
CPU time 4.61 seconds
Started Aug 27 07:09:03 AM UTC 24
Finished Aug 27 07:09:08 AM UTC 24
Peak memory 216948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378909
023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.1378909023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.396021676
Short name T590
Test name
Test status
Simulation time 105091314 ps
CPU time 1.74 seconds
Started Aug 27 07:09:05 AM UTC 24
Finished Aug 27 07:09:08 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960216
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks
_tx.396021676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.1745502696
Short name T578
Test name
Test status
Simulation time 2216314560 ps
CPU time 6.63 seconds
Started Aug 27 07:08:49 AM UTC 24
Finished Aug 27 07:08:56 AM UTC 24
Peak memory 233208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174550
2696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.1745502696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.1579879665
Short name T728
Test name
Test status
Simulation time 16515450367 ps
CPU time 148.15 seconds
Started Aug 27 07:08:49 AM UTC 24
Finished Aug 27 07:11:19 AM UTC 24
Peak memory 2500820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1579879665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.1579879665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.3122075922
Short name T595
Test name
Test status
Simulation time 604307774 ps
CPU time 3.98 seconds
Started Aug 27 07:09:05 AM UTC 24
Finished Aug 27 07:09:10 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122075
922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.3122075922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.1713440558
Short name T599
Test name
Test status
Simulation time 514887046 ps
CPU time 4.9 seconds
Started Aug 27 07:09:06 AM UTC 24
Finished Aug 27 07:09:12 AM UTC 24
Peak memory 216400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713440
558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_ad
dr.1713440558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.2871841921
Short name T596
Test name
Test status
Simulation time 358083821 ps
CPU time 2.65 seconds
Started Aug 27 07:09:07 AM UTC 24
Finished Aug 27 07:09:11 AM UTC 24
Peak memory 233488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871841
921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.2871841921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_perf.2860741392
Short name T584
Test name
Test status
Simulation time 8439169601 ps
CPU time 6.05 seconds
Started Aug 27 07:08:57 AM UTC 24
Finished Aug 27 07:09:04 AM UTC 24
Peak memory 232968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860741
392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.2860741392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.4065903383
Short name T594
Test name
Test status
Simulation time 424191480 ps
CPU time 3.8 seconds
Started Aug 27 07:09:05 AM UTC 24
Finished Aug 27 07:09:10 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065903
383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.4065903383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.3396166971
Short name T591
Test name
Test status
Simulation time 5370164745 ps
CPU time 22.24 seconds
Started Aug 27 07:08:44 AM UTC 24
Finished Aug 27 07:09:08 AM UTC 24
Peak memory 220788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396166971 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.3396166971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.1994656850
Short name T305
Test name
Test status
Simulation time 27186958996 ps
CPU time 34.9 seconds
Started Aug 27 07:08:57 AM UTC 24
Finished Aug 27 07:09:34 AM UTC 24
Peak memory 266440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199465
6850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.1994656850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.3079376435
Short name T588
Test name
Test status
Simulation time 6610392483 ps
CPU time 34.02 seconds
Started Aug 27 07:08:46 AM UTC 24
Finished Aug 27 07:09:21 AM UTC 24
Peak memory 250048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079376435 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.3079376435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.3754311890
Short name T1745
Test name
Test status
Simulation time 67576270350 ps
CPU time 1719.53 seconds
Started Aug 27 07:08:45 AM UTC 24
Finished Aug 27 07:37:42 AM UTC 24
Peak memory 11870368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754311890 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.3754311890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.3971329747
Short name T576
Test name
Test status
Simulation time 333982939 ps
CPU time 2.5 seconds
Started Aug 27 07:08:48 AM UTC 24
Finished Aug 27 07:08:51 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971329747 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.3971329747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.591506754
Short name T580
Test name
Test status
Simulation time 2512814980 ps
CPU time 9.58 seconds
Started Aug 27 07:08:51 AM UTC 24
Finished Aug 27 07:09:01 AM UTC 24
Peak memory 233092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5915067
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.591506754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.2884936469
Short name T602
Test name
Test status
Simulation time 606022749 ps
CPU time 13.63 seconds
Started Aug 27 07:09:05 AM UTC 24
Finished Aug 27 07:09:20 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884936
469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2884936469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_alert_test.1051574464
Short name T622
Test name
Test status
Simulation time 17612795 ps
CPU time 1.01 seconds
Started Aug 27 07:09:39 AM UTC 24
Finished Aug 27 07:09:41 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051574464 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1051574464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.3295045115
Short name T583
Test name
Test status
Simulation time 272647854 ps
CPU time 5.14 seconds
Started Aug 27 07:09:16 AM UTC 24
Finished Aug 27 07:09:22 AM UTC 24
Peak memory 243808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295045115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3295045115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.2858765192
Short name T566
Test name
Test status
Simulation time 2257153381 ps
CPU time 9.51 seconds
Started Aug 27 07:09:11 AM UTC 24
Finished Aug 27 07:09:21 AM UTC 24
Peak memory 338268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858765192 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.2858765192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.1013912422
Short name T681
Test name
Test status
Simulation time 18593468178 ps
CPU time 85.67 seconds
Started Aug 27 07:09:13 AM UTC 24
Finished Aug 27 07:10:41 AM UTC 24
Peak memory 487632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013912422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1013912422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.1453033735
Short name T667
Test name
Test status
Simulation time 2296215064 ps
CPU time 68.96 seconds
Started Aug 27 07:09:11 AM UTC 24
Finished Aug 27 07:10:21 AM UTC 24
Peak memory 770328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453033735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1453033735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.741466075
Short name T600
Test name
Test status
Simulation time 1821511186 ps
CPU time 1.7 seconds
Started Aug 27 07:09:11 AM UTC 24
Finished Aug 27 07:09:13 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741466075 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.741466075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.504802378
Short name T604
Test name
Test status
Simulation time 171633138 ps
CPU time 13.01 seconds
Started Aug 27 07:09:12 AM UTC 24
Finished Aug 27 07:09:26 AM UTC 24
Peak memory 247904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504802378 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.504802378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.2846660877
Short name T859
Test name
Test status
Simulation time 4690420523 ps
CPU time 256.45 seconds
Started Aug 27 07:09:09 AM UTC 24
Finished Aug 27 07:13:29 AM UTC 24
Peak memory 1327620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846660877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2846660877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.2843327435
Short name T619
Test name
Test status
Simulation time 354909839 ps
CPU time 4.87 seconds
Started Aug 27 07:09:35 AM UTC 24
Finished Aug 27 07:09:40 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843327435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2843327435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_override.3874257291
Short name T598
Test name
Test status
Simulation time 32336324 ps
CPU time 1.07 seconds
Started Aug 27 07:09:09 AM UTC 24
Finished Aug 27 07:09:12 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874257291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3874257291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_perf.61947371
Short name T702
Test name
Test status
Simulation time 7410467523 ps
CPU time 103.65 seconds
Started Aug 27 07:09:13 AM UTC 24
Finished Aug 27 07:10:59 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61947371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.61947371
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.1504230593
Short name T565
Test name
Test status
Simulation time 216242862 ps
CPU time 3.19 seconds
Started Aug 27 07:09:13 AM UTC 24
Finished Aug 27 07:09:17 AM UTC 24
Peak memory 226732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504230593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.1504230593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.1541668010
Short name T691
Test name
Test status
Simulation time 2391280226 ps
CPU time 95.51 seconds
Started Aug 27 07:09:08 AM UTC 24
Finished Aug 27 07:10:46 AM UTC 24
Peak memory 379164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541668010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1541668010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.3569141234
Short name T628
Test name
Test status
Simulation time 670080777 ps
CPU time 28.23 seconds
Started Aug 27 07:09:14 AM UTC 24
Finished Aug 27 07:09:44 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569141234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3569141234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.3651466307
Short name T630
Test name
Test status
Simulation time 7222818449 ps
CPU time 10.27 seconds
Started Aug 27 07:09:32 AM UTC 24
Finished Aug 27 07:09:44 AM UTC 24
Peak memory 227256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3651466307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.3651466307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.2182400147
Short name T605
Test name
Test status
Simulation time 189127559 ps
CPU time 1.33 seconds
Started Aug 27 07:09:27 AM UTC 24
Finished Aug 27 07:09:29 AM UTC 24
Peak memory 226612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182400
147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.2182400147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.1810709708
Short name T608
Test name
Test status
Simulation time 250147191 ps
CPU time 1.05 seconds
Started Aug 27 07:09:30 AM UTC 24
Finished Aug 27 07:09:32 AM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810709
708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.1810709708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.1974054966
Short name T616
Test name
Test status
Simulation time 259539675 ps
CPU time 3 seconds
Started Aug 27 07:09:35 AM UTC 24
Finished Aug 27 07:09:39 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974054
966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar
ks_acq.1974054966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.3891351148
Short name T617
Test name
Test status
Simulation time 267368541 ps
CPU time 2.07 seconds
Started Aug 27 07:09:36 AM UTC 24
Finished Aug 27 07:09:39 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891351
148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_tx.3891351148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_hrst.100848627
Short name T614
Test name
Test status
Simulation time 268400310 ps
CPU time 3.17 seconds
Started Aug 27 07:09:33 AM UTC 24
Finished Aug 27 07:09:38 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008486
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_hrst.100848627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.2042042976
Short name T606
Test name
Test status
Simulation time 755191089 ps
CPU time 6.96 seconds
Started Aug 27 07:09:22 AM UTC 24
Finished Aug 27 07:09:30 AM UTC 24
Peak memory 233772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204204
2976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.2042042976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.1996629311
Short name T643
Test name
Test status
Simulation time 6113317802 ps
CPU time 39.96 seconds
Started Aug 27 07:09:22 AM UTC 24
Finished Aug 27 07:10:03 AM UTC 24
Peak memory 977304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1996629311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stres
s_wr.1996629311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.1953538239
Short name T626
Test name
Test status
Simulation time 766776899 ps
CPU time 4.04 seconds
Started Aug 27 07:09:38 AM UTC 24
Finished Aug 27 07:09:43 AM UTC 24
Peak memory 227072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953538
239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.1953538239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.1347072866
Short name T631
Test name
Test status
Simulation time 1699929290 ps
CPU time 3.89 seconds
Started Aug 27 07:09:39 AM UTC 24
Finished Aug 27 07:09:44 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347072
866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad
dr.1347072866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.1105303695
Short name T625
Test name
Test status
Simulation time 134011420 ps
CPU time 2.45 seconds
Started Aug 27 07:09:39 AM UTC 24
Finished Aug 27 07:09:43 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105303
695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.1105303695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_perf.1598799075
Short name T618
Test name
Test status
Simulation time 640296814 ps
CPU time 8.09 seconds
Started Aug 27 07:09:30 AM UTC 24
Finished Aug 27 07:09:39 AM UTC 24
Peak memory 232968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598799
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.1598799075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.41931882
Short name T627
Test name
Test status
Simulation time 500435438 ps
CPU time 4.28 seconds
Started Aug 27 07:09:38 AM UTC 24
Finished Aug 27 07:09:43 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193188
2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.41931882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.3809700557
Short name T612
Test name
Test status
Simulation time 7085602103 ps
CPU time 18.34 seconds
Started Aug 27 07:09:17 AM UTC 24
Finished Aug 27 07:09:37 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809700557 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.3809700557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.1312145906
Short name T856
Test name
Test status
Simulation time 36705112596 ps
CPU time 232.62 seconds
Started Aug 27 07:09:30 AM UTC 24
Finished Aug 27 07:13:26 AM UTC 24
Peak memory 2791576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131214
5906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.1312145906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.2237934885
Short name T661
Test name
Test status
Simulation time 1940600359 ps
CPU time 53.92 seconds
Started Aug 27 07:09:20 AM UTC 24
Finished Aug 27 07:10:15 AM UTC 24
Peak memory 228920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237934885 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.2237934885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.3739743412
Short name T760
Test name
Test status
Simulation time 52825056328 ps
CPU time 154.6 seconds
Started Aug 27 07:09:18 AM UTC 24
Finished Aug 27 07:11:56 AM UTC 24
Peak memory 2185304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739743412 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.3739743412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1793164962
Short name T621
Test name
Test status
Simulation time 1708833266 ps
CPU time 19.19 seconds
Started Aug 27 07:09:21 AM UTC 24
Finished Aug 27 07:09:41 AM UTC 24
Peak memory 288832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793164962 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1793164962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.2560372808
Short name T610
Test name
Test status
Simulation time 7451720363 ps
CPU time 9.63 seconds
Started Aug 27 07:09:23 AM UTC 24
Finished Aug 27 07:09:34 AM UTC 24
Peak memory 227184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560372
808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.2560372808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.303155896
Short name T620
Test name
Test status
Simulation time 49277431 ps
CPU time 2 seconds
Started Aug 27 07:09:38 AM UTC 24
Finished Aug 27 07:09:41 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031558
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.303155896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_alert_test.3006528572
Short name T656
Test name
Test status
Simulation time 23491461 ps
CPU time 0.91 seconds
Started Aug 27 07:10:10 AM UTC 24
Finished Aug 27 07:10:12 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006528572 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3006528572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.3047542290
Short name T633
Test name
Test status
Simulation time 109523235 ps
CPU time 2.83 seconds
Started Aug 27 07:09:44 AM UTC 24
Finished Aug 27 07:09:48 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047542290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.3047542290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.576524278
Short name T636
Test name
Test status
Simulation time 1703969046 ps
CPU time 9.26 seconds
Started Aug 27 07:09:43 AM UTC 24
Finished Aug 27 07:09:53 AM UTC 24
Peak memory 278548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576524278 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.576524278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.1568292532
Short name T704
Test name
Test status
Simulation time 2717219490 ps
CPU time 75.86 seconds
Started Aug 27 07:09:43 AM UTC 24
Finished Aug 27 07:11:01 AM UTC 24
Peak memory 561628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568292532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1568292532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.1414952312
Short name T743
Test name
Test status
Simulation time 1942096274 ps
CPU time 115.56 seconds
Started Aug 27 07:09:42 AM UTC 24
Finished Aug 27 07:11:40 AM UTC 24
Peak memory 651356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414952312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1414952312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.3458301120
Short name T629
Test name
Test status
Simulation time 243479436 ps
CPU time 1.04 seconds
Started Aug 27 07:09:42 AM UTC 24
Finished Aug 27 07:09:44 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458301120 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.3458301120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.1450126652
Short name T635
Test name
Test status
Simulation time 103852290 ps
CPU time 5.63 seconds
Started Aug 27 07:09:43 AM UTC 24
Finished Aug 27 07:09:50 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450126652 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.1450126652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.3880110284
Short name T125
Test name
Test status
Simulation time 4839358555 ps
CPU time 109.86 seconds
Started Aug 27 07:09:42 AM UTC 24
Finished Aug 27 07:11:34 AM UTC 24
Peak memory 1284624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880110284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3880110284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.2663797358
Short name T654
Test name
Test status
Simulation time 705900007 ps
CPU time 5.84 seconds
Started Aug 27 07:10:05 AM UTC 24
Finished Aug 27 07:10:12 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663797358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2663797358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_override.2464488274
Short name T624
Test name
Test status
Simulation time 115501436 ps
CPU time 1.02 seconds
Started Aug 27 07:09:40 AM UTC 24
Finished Aug 27 07:09:42 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464488274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2464488274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_perf.3892047885
Short name T634
Test name
Test status
Simulation time 277535233 ps
CPU time 3.66 seconds
Started Aug 27 07:09:44 AM UTC 24
Finished Aug 27 07:09:49 AM UTC 24
Peak memory 229076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892047885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3892047885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.3829768417
Short name T632
Test name
Test status
Simulation time 147075702 ps
CPU time 1.68 seconds
Started Aug 27 07:09:44 AM UTC 24
Finished Aug 27 07:09:47 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829768417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.3829768417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.3248708672
Short name T720
Test name
Test status
Simulation time 8676980115 ps
CPU time 94.59 seconds
Started Aug 27 07:09:39 AM UTC 24
Finished Aug 27 07:11:16 AM UTC 24
Peak memory 364768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248708672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3248708672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.3776155387
Short name T664
Test name
Test status
Simulation time 530354316 ps
CPU time 30.37 seconds
Started Aug 27 07:09:44 AM UTC 24
Finished Aug 27 07:10:16 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776155387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3776155387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.551981415
Short name T648
Test name
Test status
Simulation time 1030255961 ps
CPU time 6.02 seconds
Started Aug 27 07:10:01 AM UTC 24
Finished Aug 27 07:10:09 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=551981415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.551981415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.2456080749
Short name T642
Test name
Test status
Simulation time 405503187 ps
CPU time 1.6 seconds
Started Aug 27 07:09:58 AM UTC 24
Finished Aug 27 07:10:01 AM UTC 24
Peak memory 214508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456080
749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.2456080749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.3012166810
Short name T644
Test name
Test status
Simulation time 298161792 ps
CPU time 3 seconds
Started Aug 27 07:09:59 AM UTC 24
Finished Aug 27 07:10:03 AM UTC 24
Peak memory 232904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012166
810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.3012166810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.4176898425
Short name T652
Test name
Test status
Simulation time 355450798 ps
CPU time 3.41 seconds
Started Aug 27 07:10:06 AM UTC 24
Finished Aug 27 07:10:10 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176898
425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.4176898425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.83906721
Short name T651
Test name
Test status
Simulation time 64270088 ps
CPU time 1.46 seconds
Started Aug 27 07:10:07 AM UTC 24
Finished Aug 27 07:10:10 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8390672
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.83906721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.2277469062
Short name T638
Test name
Test status
Simulation time 1186824118 ps
CPU time 6.28 seconds
Started Aug 27 07:09:50 AM UTC 24
Finished Aug 27 07:09:57 AM UTC 24
Peak memory 226740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227746
9062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.2277469062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.646665447
Short name T971
Test name
Test status
Simulation time 22630310489 ps
CPU time 347.52 seconds
Started Aug 27 07:09:51 AM UTC 24
Finished Aug 27 07:15:42 AM UTC 24
Peak memory 5470432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=646665447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stress
_wr.646665447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.2372039986
Short name T663
Test name
Test status
Simulation time 575011913 ps
CPU time 5.19 seconds
Started Aug 27 07:10:09 AM UTC 24
Finished Aug 27 07:10:16 AM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372039
986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.2372039986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.3165213914
Short name T662
Test name
Test status
Simulation time 522184178 ps
CPU time 3.77 seconds
Started Aug 27 07:10:10 AM UTC 24
Finished Aug 27 07:10:15 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165213
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.3165213914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.1165631971
Short name T659
Test name
Test status
Simulation time 246624908 ps
CPU time 2.14 seconds
Started Aug 27 07:10:10 AM UTC 24
Finished Aug 27 07:10:14 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165631
971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_txstretch.1165631971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_perf.1498215292
Short name T650
Test name
Test status
Simulation time 719983471 ps
CPU time 7.64 seconds
Started Aug 27 07:10:00 AM UTC 24
Finished Aug 27 07:10:09 AM UTC 24
Peak memory 232952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498215
292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.1498215292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.2890069663
Short name T658
Test name
Test status
Simulation time 6246909289 ps
CPU time 3.15 seconds
Started Aug 27 07:10:09 AM UTC 24
Finished Aug 27 07:10:14 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890069
663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.2890069663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.533570206
Short name T647
Test name
Test status
Simulation time 1256192622 ps
CPU time 21.87 seconds
Started Aug 27 07:09:45 AM UTC 24
Finished Aug 27 07:10:08 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533570206 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.533570206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.1689433771
Short name T1086
Test name
Test status
Simulation time 38030031183 ps
CPU time 492.24 seconds
Started Aug 27 07:10:01 AM UTC 24
Finished Aug 27 07:18:19 AM UTC 24
Peak memory 6111456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168943
3771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.1689433771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.3983228767
Short name T676
Test name
Test status
Simulation time 1852151739 ps
CPU time 46.94 seconds
Started Aug 27 07:09:48 AM UTC 24
Finished Aug 27 07:10:36 AM UTC 24
Peak memory 250008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983228767 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.3983228767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.1230662716
Short name T1637
Test name
Test status
Simulation time 59575461437 ps
CPU time 1281.72 seconds
Started Aug 27 07:09:45 AM UTC 24
Finished Aug 27 07:31:20 AM UTC 24
Peak memory 10008992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230662716 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.1230662716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2538978581
Short name T641
Test name
Test status
Simulation time 2011983605 ps
CPU time 10.55 seconds
Started Aug 27 07:09:49 AM UTC 24
Finished Aug 27 07:10:00 AM UTC 24
Peak memory 311552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538978581 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.2538978581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.2840901704
Short name T646
Test name
Test status
Simulation time 4909836129 ps
CPU time 11.33 seconds
Started Aug 27 07:09:54 AM UTC 24
Finished Aug 27 07:10:06 AM UTC 24
Peak memory 231028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840901
704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.2840901704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.1321236881
Short name T655
Test name
Test status
Simulation time 102628028 ps
CPU time 3.69 seconds
Started Aug 27 07:10:07 AM UTC 24
Finished Aug 27 07:10:12 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321236
881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.1321236881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_alert_test.2742327693
Short name T685
Test name
Test status
Simulation time 25812561 ps
CPU time 0.87 seconds
Started Aug 27 07:10:41 AM UTC 24
Finished Aug 27 07:10:43 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742327693 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2742327693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.3052577748
Short name T669
Test name
Test status
Simulation time 323068093 ps
CPU time 6.15 seconds
Started Aug 27 07:10:16 AM UTC 24
Finished Aug 27 07:10:24 AM UTC 24
Peak memory 226600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052577748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3052577748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.1859331267
Short name T666
Test name
Test status
Simulation time 404400841 ps
CPU time 4.66 seconds
Started Aug 27 07:10:14 AM UTC 24
Finished Aug 27 07:10:19 AM UTC 24
Peak memory 254276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859331267 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.1859331267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.1165486838
Short name T745
Test name
Test status
Simulation time 14095707952 ps
CPU time 86.13 seconds
Started Aug 27 07:10:15 AM UTC 24
Finished Aug 27 07:11:43 AM UTC 24
Peak memory 508132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165486838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.1165486838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.2727077546
Short name T742
Test name
Test status
Simulation time 1408148399 ps
CPU time 84.45 seconds
Started Aug 27 07:10:13 AM UTC 24
Finished Aug 27 07:11:39 AM UTC 24
Peak memory 559180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727077546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2727077546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.2616631157
Short name T660
Test name
Test status
Simulation time 668632797 ps
CPU time 1.39 seconds
Started Aug 27 07:10:13 AM UTC 24
Finished Aug 27 07:10:15 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616631157 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.2616631157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.237815602
Short name T668
Test name
Test status
Simulation time 212716046 ps
CPU time 7.03 seconds
Started Aug 27 07:10:14 AM UTC 24
Finished Aug 27 07:10:22 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237815602 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.237815602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.1168071082
Short name T832
Test name
Test status
Simulation time 20087681006 ps
CPU time 161.35 seconds
Started Aug 27 07:10:13 AM UTC 24
Finished Aug 27 07:12:56 AM UTC 24
Peak memory 1003612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168071082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1168071082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.3976033522
Short name T700
Test name
Test status
Simulation time 1647001922 ps
CPU time 20.93 seconds
Started Aug 27 07:10:35 AM UTC 24
Finished Aug 27 07:10:57 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976033522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3976033522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_override.1111849665
Short name T657
Test name
Test status
Simulation time 44255669 ps
CPU time 0.9 seconds
Started Aug 27 07:10:11 AM UTC 24
Finished Aug 27 07:10:13 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111849665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1111849665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_perf.764657959
Short name T836
Test name
Test status
Simulation time 12404645015 ps
CPU time 165.31 seconds
Started Aug 27 07:10:15 AM UTC 24
Finished Aug 27 07:13:03 AM UTC 24
Peak memory 231036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764657959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.764657959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.270127198
Short name T38
Test name
Test status
Simulation time 6246900820 ps
CPU time 6.63 seconds
Started Aug 27 07:10:16 AM UTC 24
Finished Aug 27 07:10:24 AM UTC 24
Peak memory 216940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270127198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.270127198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.218322234
Short name T724
Test name
Test status
Simulation time 1365814747 ps
CPU time 64.02 seconds
Started Aug 27 07:10:11 AM UTC 24
Finished Aug 27 07:11:17 AM UTC 24
Peak memory 378956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218322234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.218322234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.436852135
Short name T258
Test name
Test status
Simulation time 169569519801 ps
CPU time 1248.62 seconds
Started Aug 27 07:10:16 AM UTC 24
Finished Aug 27 07:31:19 AM UTC 24
Peak memory 2515188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436852135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.436852135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.4165810664
Short name T698
Test name
Test status
Simulation time 1385429882 ps
CPU time 36.53 seconds
Started Aug 27 07:10:16 AM UTC 24
Finished Aug 27 07:10:55 AM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165810664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.4165810664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.1912367672
Short name T682
Test name
Test status
Simulation time 3573601966 ps
CPU time 8.54 seconds
Started Aug 27 07:10:31 AM UTC 24
Finished Aug 27 07:10:41 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1912367672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.1912367672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.1823995821
Short name T671
Test name
Test status
Simulation time 860347808 ps
CPU time 2.63 seconds
Started Aug 27 07:10:25 AM UTC 24
Finished Aug 27 07:10:29 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823995
821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.1823995821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.1687844408
Short name T674
Test name
Test status
Simulation time 307903944 ps
CPU time 3.41 seconds
Started Aug 27 07:10:29 AM UTC 24
Finished Aug 27 07:10:34 AM UTC 24
Peak memory 227416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687844
408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.1687844408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.396810131
Short name T683
Test name
Test status
Simulation time 467751764 ps
CPU time 4.92 seconds
Started Aug 27 07:10:36 AM UTC 24
Finished Aug 27 07:10:42 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968101
31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_acq.396810131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.185702027
Short name T680
Test name
Test status
Simulation time 188982222 ps
CPU time 2.66 seconds
Started Aug 27 07:10:37 AM UTC 24
Finished Aug 27 07:10:40 AM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857020
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermarks
_tx.185702027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_hrst.1264549537
Short name T675
Test name
Test status
Simulation time 795258447 ps
CPU time 2.69 seconds
Started Aug 27 07:10:31 AM UTC 24
Finished Aug 27 07:10:35 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264549
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.1264549537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.1671116094
Short name T672
Test name
Test status
Simulation time 4450953183 ps
CPU time 7.24 seconds
Started Aug 27 07:10:22 AM UTC 24
Finished Aug 27 07:10:30 AM UTC 24
Peak memory 233488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167111
6094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.1671116094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.3628912356
Short name T766
Test name
Test status
Simulation time 9105586186 ps
CPU time 95.45 seconds
Started Aug 27 07:10:23 AM UTC 24
Finished Aug 27 07:12:00 AM UTC 24
Peak memory 2392344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3628912356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.3628912356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.748633970
Short name T690
Test name
Test status
Simulation time 2309172617 ps
CPU time 5.35 seconds
Started Aug 27 07:10:39 AM UTC 24
Finished Aug 27 07:10:45 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7486339
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.748633970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.2352963666
Short name T687
Test name
Test status
Simulation time 1617038361 ps
CPU time 3.65 seconds
Started Aug 27 07:10:39 AM UTC 24
Finished Aug 27 07:10:44 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352963
666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.2352963666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_nack_txstretch.2053888787
Short name T686
Test name
Test status
Simulation time 220816842 ps
CPU time 2 seconds
Started Aug 27 07:10:40 AM UTC 24
Finished Aug 27 07:10:43 AM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053888
787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_txstretch.2053888787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_perf.2268201932
Short name T677
Test name
Test status
Simulation time 557587777 ps
CPU time 7.72 seconds
Started Aug 27 07:10:29 AM UTC 24
Finished Aug 27 07:10:38 AM UTC 24
Peak memory 227036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268201
932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.2268201932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.1836941645
Short name T684
Test name
Test status
Simulation time 921051096 ps
CPU time 4.11 seconds
Started Aug 27 07:10:38 AM UTC 24
Finished Aug 27 07:10:43 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836941
645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.1836941645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.3648493400
Short name T1626
Test name
Test status
Simulation time 62999997878 ps
CPU time 1203.62 seconds
Started Aug 27 07:10:30 AM UTC 24
Finished Aug 27 07:30:46 AM UTC 24
Peak memory 8153308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364849
3400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.3648493400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.1959788864
Short name T670
Test name
Test status
Simulation time 1471037872 ps
CPU time 9.83 seconds
Started Aug 27 07:10:17 AM UTC 24
Finished Aug 27 07:10:29 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959788864 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.1959788864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.2023354917
Short name T782
Test name
Test status
Simulation time 34064659578 ps
CPU time 114.45 seconds
Started Aug 27 07:10:17 AM UTC 24
Finished Aug 27 07:12:14 AM UTC 24
Peak memory 1960084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023354917 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.2023354917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.1545201990
Short name T695
Test name
Test status
Simulation time 2632365542 ps
CPU time 28.41 seconds
Started Aug 27 07:10:21 AM UTC 24
Finished Aug 27 07:10:51 AM UTC 24
Peak memory 338436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545201990 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.1545201990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.1240475223
Short name T679
Test name
Test status
Simulation time 1428533887 ps
CPU time 13.11 seconds
Started Aug 27 07:10:24 AM UTC 24
Finished Aug 27 07:10:39 AM UTC 24
Peak memory 233548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240475
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.1240475223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.713135637
Short name T689
Test name
Test status
Simulation time 330243154 ps
CPU time 7.17 seconds
Started Aug 27 07:10:37 AM UTC 24
Finished Aug 27 07:10:45 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7131356
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.713135637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_alert_test.3241530692
Short name T719
Test name
Test status
Simulation time 17073379 ps
CPU time 1.01 seconds
Started Aug 27 07:11:13 AM UTC 24
Finished Aug 27 07:11:15 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241530692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3241530692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.1751583958
Short name T696
Test name
Test status
Simulation time 530289809 ps
CPU time 2.96 seconds
Started Aug 27 07:10:47 AM UTC 24
Finished Aug 27 07:10:51 AM UTC 24
Peak memory 231288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751583958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1751583958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.2686212720
Short name T697
Test name
Test status
Simulation time 627267363 ps
CPU time 6.9 seconds
Started Aug 27 07:10:44 AM UTC 24
Finished Aug 27 07:10:52 AM UTC 24
Peak memory 287004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686212720 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.2686212720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.2846854851
Short name T789
Test name
Test status
Simulation time 3407524666 ps
CPU time 92.82 seconds
Started Aug 27 07:10:45 AM UTC 24
Finished Aug 27 07:12:20 AM UTC 24
Peak memory 590044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846854851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2846854851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.2013936378
Short name T800
Test name
Test status
Simulation time 21854612504 ps
CPU time 104 seconds
Started Aug 27 07:10:44 AM UTC 24
Finished Aug 27 07:12:30 AM UTC 24
Peak memory 606364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013936378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2013936378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.3460624992
Short name T692
Test name
Test status
Simulation time 100872585 ps
CPU time 1.24 seconds
Started Aug 27 07:10:44 AM UTC 24
Finished Aug 27 07:10:46 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460624992 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.3460624992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.3000973805
Short name T699
Test name
Test status
Simulation time 604346991 ps
CPU time 9.95 seconds
Started Aug 27 07:10:45 AM UTC 24
Finished Aug 27 07:10:56 AM UTC 24
Peak memory 243780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000973805 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.3000973805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.4219048696
Short name T769
Test name
Test status
Simulation time 2871454935 ps
CPU time 80.67 seconds
Started Aug 27 07:10:43 AM UTC 24
Finished Aug 27 07:12:05 AM UTC 24
Peak memory 934108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219048696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.4219048696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_mode_toggle.3975899933
Short name T280
Test name
Test status
Simulation time 77406196 ps
CPU time 2.61 seconds
Started Aug 27 07:11:06 AM UTC 24
Finished Aug 27 07:11:10 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975899933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3975899933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_override.2663566821
Short name T688
Test name
Test status
Simulation time 17778282 ps
CPU time 0.95 seconds
Started Aug 27 07:10:42 AM UTC 24
Finished Aug 27 07:10:44 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663566821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2663566821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_perf.4259095881
Short name T709
Test name
Test status
Simulation time 8020497784 ps
CPU time 17.54 seconds
Started Aug 27 07:10:46 AM UTC 24
Finished Aug 27 07:11:05 AM UTC 24
Peak memory 247968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259095881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.4259095881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.502714822
Short name T694
Test name
Test status
Simulation time 113168544 ps
CPU time 2.49 seconds
Started Aug 27 07:10:46 AM UTC 24
Finished Aug 27 07:10:50 AM UTC 24
Peak memory 237108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502714822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.502714822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.1366669252
Short name T707
Test name
Test status
Simulation time 4308663064 ps
CPU time 20.59 seconds
Started Aug 27 07:10:41 AM UTC 24
Finished Aug 27 07:11:03 AM UTC 24
Peak memory 348440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366669252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1366669252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.759870440
Short name T727
Test name
Test status
Simulation time 12667095844 ps
CPU time 30.41 seconds
Started Aug 27 07:10:47 AM UTC 24
Finished Aug 27 07:11:19 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759870440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.759870440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.3013024865
Short name T717
Test name
Test status
Simulation time 880058082 ps
CPU time 7.8 seconds
Started Aug 27 07:11:04 AM UTC 24
Finished Aug 27 07:11:13 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3013024865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_ad
dr.3013024865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.1122654199
Short name T706
Test name
Test status
Simulation time 178926837 ps
CPU time 2.04 seconds
Started Aug 27 07:11:00 AM UTC 24
Finished Aug 27 07:11:03 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122654
199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.1122654199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.2429460360
Short name T710
Test name
Test status
Simulation time 188255906 ps
CPU time 2.05 seconds
Started Aug 27 07:11:02 AM UTC 24
Finished Aug 27 07:11:05 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429460
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.2429460360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.1522369223
Short name T715
Test name
Test status
Simulation time 813989346 ps
CPU time 4.02 seconds
Started Aug 27 07:11:06 AM UTC 24
Finished Aug 27 07:11:11 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522369
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar
ks_acq.1522369223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.2421450187
Short name T716
Test name
Test status
Simulation time 320991866 ps
CPU time 2.85 seconds
Started Aug 27 07:11:08 AM UTC 24
Finished Aug 27 07:11:12 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421450
187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark
s_tx.2421450187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.373563733
Short name T712
Test name
Test status
Simulation time 341515116 ps
CPU time 2.95 seconds
Started Aug 27 07:11:04 AM UTC 24
Finished Aug 27 07:11:08 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735637
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.373563733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.2114994101
Short name T708
Test name
Test status
Simulation time 747377650 ps
CPU time 7.19 seconds
Started Aug 27 07:10:55 AM UTC 24
Finished Aug 27 07:11:04 AM UTC 24
Peak memory 233812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211499
4101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.2114994101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.642985536
Short name T881
Test name
Test status
Simulation time 12400022033 ps
CPU time 167.14 seconds
Started Aug 27 07:10:57 AM UTC 24
Finished Aug 27 07:13:47 AM UTC 24
Peak memory 3119516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=642985536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stress
_wr.642985536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.1287740959
Short name T725
Test name
Test status
Simulation time 488189741 ps
CPU time 4.77 seconds
Started Aug 27 07:11:13 AM UTC 24
Finished Aug 27 07:11:19 AM UTC 24
Peak memory 216332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287740
959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.1287740959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_perf.439586161
Short name T714
Test name
Test status
Simulation time 796631870 ps
CPU time 7.43 seconds
Started Aug 27 07:11:02 AM UTC 24
Finished Aug 27 07:11:10 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4395861
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.439586161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.3502225895
Short name T722
Test name
Test status
Simulation time 5688737892 ps
CPU time 4.49 seconds
Started Aug 27 07:11:11 AM UTC 24
Finished Aug 27 07:11:16 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502225
895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.3502225895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.3666967139
Short name T732
Test name
Test status
Simulation time 6437985013 ps
CPU time 29.34 seconds
Started Aug 27 07:10:52 AM UTC 24
Finished Aug 27 07:11:23 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666967139 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.3666967139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.1134006414
Short name T757
Test name
Test status
Simulation time 8022191696 ps
CPU time 45.47 seconds
Started Aug 27 07:11:04 AM UTC 24
Finished Aug 27 07:11:51 AM UTC 24
Peak memory 240112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113400
6414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.1134006414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.3113853247
Short name T750
Test name
Test status
Simulation time 2333906639 ps
CPU time 52.84 seconds
Started Aug 27 07:10:53 AM UTC 24
Finished Aug 27 07:11:48 AM UTC 24
Peak memory 231308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113853247 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.3113853247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.3753788830
Short name T1712
Test name
Test status
Simulation time 62210456637 ps
CPU time 1342.3 seconds
Started Aug 27 07:10:52 AM UTC 24
Finished Aug 27 07:33:27 AM UTC 24
Peak memory 10600604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753788830 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.3753788830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.669231612
Short name T701
Test name
Test status
Simulation time 4885796249 ps
CPU time 2.87 seconds
Started Aug 27 07:10:53 AM UTC 24
Finished Aug 27 07:10:57 AM UTC 24
Peak memory 227044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669231612 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.669231612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3289384309
Short name T713
Test name
Test status
Simulation time 2431052450 ps
CPU time 9.9 seconds
Started Aug 27 07:10:58 AM UTC 24
Finished Aug 27 07:11:09 AM UTC 24
Peak memory 231048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289384
309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3289384309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.27693850
Short name T718
Test name
Test status
Simulation time 165245464 ps
CPU time 3.81 seconds
Started Aug 27 07:11:08 AM UTC 24
Finished Aug 27 07:11:13 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769385
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.27693850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_alert_test.2228306104
Short name T751
Test name
Test status
Simulation time 18855732 ps
CPU time 0.88 seconds
Started Aug 27 07:11:46 AM UTC 24
Finished Aug 27 07:11:48 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228306104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2228306104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.1170521629
Short name T734
Test name
Test status
Simulation time 107235205 ps
CPU time 2.39 seconds
Started Aug 27 07:11:21 AM UTC 24
Finished Aug 27 07:11:24 AM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170521629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1170521629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.2252577238
Short name T733
Test name
Test status
Simulation time 204971376 ps
CPU time 5.62 seconds
Started Aug 27 07:11:17 AM UTC 24
Finished Aug 27 07:11:24 AM UTC 24
Peak memory 252120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252577238 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.2252577238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.300395213
Short name T835
Test name
Test status
Simulation time 10689149299 ps
CPU time 103.3 seconds
Started Aug 27 07:11:17 AM UTC 24
Finished Aug 27 07:13:03 AM UTC 24
Peak memory 796944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300395213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.300395213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.1326549393
Short name T798
Test name
Test status
Simulation time 10912913775 ps
CPU time 68.87 seconds
Started Aug 27 07:11:17 AM UTC 24
Finished Aug 27 07:12:28 AM UTC 24
Peak memory 846008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326549393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1326549393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.2822025020
Short name T729
Test name
Test status
Simulation time 538450507 ps
CPU time 1.8 seconds
Started Aug 27 07:11:17 AM UTC 24
Finished Aug 27 07:11:20 AM UTC 24
Peak memory 216280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822025020 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.2822025020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.784312155
Short name T730
Test name
Test status
Simulation time 173229862 ps
CPU time 3.36 seconds
Started Aug 27 07:11:17 AM UTC 24
Finished Aug 27 07:11:22 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784312155 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.784312155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.2845221445
Short name T864
Test name
Test status
Simulation time 41637135012 ps
CPU time 139.46 seconds
Started Aug 27 07:11:15 AM UTC 24
Finished Aug 27 07:13:37 AM UTC 24
Peak memory 1413632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845221445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2845221445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.972204572
Short name T758
Test name
Test status
Simulation time 4881445505 ps
CPU time 11 seconds
Started Aug 27 07:11:40 AM UTC 24
Finished Aug 27 07:11:52 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972204572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.972204572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_mode_toggle.1605587791
Short name T746
Test name
Test status
Simulation time 77910725 ps
CPU time 3.15 seconds
Started Aug 27 07:11:39 AM UTC 24
Finished Aug 27 07:11:43 AM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605587791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1605587791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_override.2239025659
Short name T723
Test name
Test status
Simulation time 79880980 ps
CPU time 1.03 seconds
Started Aug 27 07:11:15 AM UTC 24
Finished Aug 27 07:11:17 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239025659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2239025659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_perf.103848958
Short name T861
Test name
Test status
Simulation time 12983665182 ps
CPU time 130.9 seconds
Started Aug 27 07:11:20 AM UTC 24
Finished Aug 27 07:13:33 AM UTC 24
Peak memory 291144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103848958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.103848958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.2031408796
Short name T731
Test name
Test status
Simulation time 146930022 ps
CPU time 1.66 seconds
Started Aug 27 07:11:20 AM UTC 24
Finished Aug 27 07:11:22 AM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031408796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2031408796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.2350333003
Short name T747
Test name
Test status
Simulation time 1223876550 ps
CPU time 27.51 seconds
Started Aug 27 07:11:15 AM UTC 24
Finished Aug 27 07:11:44 AM UTC 24
Peak memory 313636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350333003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2350333003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.2676190789
Short name T739
Test name
Test status
Simulation time 5662266963 ps
CPU time 14.94 seconds
Started Aug 27 07:11:21 AM UTC 24
Finished Aug 27 07:11:37 AM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676190789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2676190789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.2250031012
Short name T721
Test name
Test status
Simulation time 10716833159 ps
CPU time 5.03 seconds
Started Aug 27 07:11:38 AM UTC 24
Finished Aug 27 07:11:44 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2250031012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad
dr.2250031012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.534461827
Short name T740
Test name
Test status
Simulation time 248993121 ps
CPU time 1.85 seconds
Started Aug 27 07:11:35 AM UTC 24
Finished Aug 27 07:11:38 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5344618
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.534461827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.3711903394
Short name T741
Test name
Test status
Simulation time 1308922818 ps
CPU time 1.91 seconds
Started Aug 27 07:11:36 AM UTC 24
Finished Aug 27 07:11:39 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711903
394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.3711903394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.1626142239
Short name T749
Test name
Test status
Simulation time 638104768 ps
CPU time 5.8 seconds
Started Aug 27 07:11:40 AM UTC 24
Finished Aug 27 07:11:47 AM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626142
239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermar
ks_acq.1626142239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.3572401537
Short name T726
Test name
Test status
Simulation time 217267580 ps
CPU time 1.92 seconds
Started Aug 27 07:11:41 AM UTC 24
Finished Aug 27 07:11:44 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572401
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark
s_tx.3572401537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.975535742
Short name T744
Test name
Test status
Simulation time 500855978 ps
CPU time 2.02 seconds
Started Aug 27 07:11:38 AM UTC 24
Finished Aug 27 07:11:41 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9755357
42 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.975535742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.1067270721
Short name T735
Test name
Test status
Simulation time 2304780555 ps
CPU time 7.2 seconds
Started Aug 27 07:11:24 AM UTC 24
Finished Aug 27 07:11:33 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106727
0721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.1067270721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.1253217855
Short name T736
Test name
Test status
Simulation time 3917793113 ps
CPU time 9.81 seconds
Started Aug 27 07:11:24 AM UTC 24
Finished Aug 27 07:11:35 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1253217855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.1253217855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.3212853462
Short name T756
Test name
Test status
Simulation time 998350476 ps
CPU time 4.43 seconds
Started Aug 27 07:11:45 AM UTC 24
Finished Aug 27 07:11:50 AM UTC 24
Peak memory 227124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212853
462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.3212853462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.3066932103
Short name T754
Test name
Test status
Simulation time 2317602696 ps
CPU time 3.27 seconds
Started Aug 27 07:11:45 AM UTC 24
Finished Aug 27 07:11:49 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066932
103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_ad
dr.3066932103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.3000940052
Short name T752
Test name
Test status
Simulation time 151860735 ps
CPU time 1.72 seconds
Started Aug 27 07:11:46 AM UTC 24
Finished Aug 27 07:11:49 AM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000940
052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_txstretch.3000940052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_perf.3233427148
Short name T737
Test name
Test status
Simulation time 3569401099 ps
CPU time 8.79 seconds
Started Aug 27 07:11:37 AM UTC 24
Finished Aug 27 07:11:47 AM UTC 24
Peak memory 233696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233427
148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.3233427148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.3047238272
Short name T755
Test name
Test status
Simulation time 448312258 ps
CPU time 3.96 seconds
Started Aug 27 07:11:45 AM UTC 24
Finished Aug 27 07:11:50 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047238
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.3047238272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.452740124
Short name T775
Test name
Test status
Simulation time 2015651362 ps
CPU time 45.79 seconds
Started Aug 27 07:11:21 AM UTC 24
Finished Aug 27 07:12:08 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452740124 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.452740124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.3690054519
Short name T955
Test name
Test status
Simulation time 49888259486 ps
CPU time 223.81 seconds
Started Aug 27 07:11:37 AM UTC 24
Finished Aug 27 07:15:24 AM UTC 24
Peak memory 2119904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369005
4519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.3690054519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.514742175
Short name T811
Test name
Test status
Simulation time 2996571933 ps
CPU time 75.63 seconds
Started Aug 27 07:11:23 AM UTC 24
Finished Aug 27 07:12:41 AM UTC 24
Peak memory 228868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514742175 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.514742175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.1152492468
Short name T1737
Test name
Test status
Simulation time 63757543935 ps
CPU time 1411.76 seconds
Started Aug 27 07:11:23 AM UTC 24
Finished Aug 27 07:35:08 AM UTC 24
Peak memory 11071896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152492468 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.1152492468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.3882865996
Short name T772
Test name
Test status
Simulation time 2131350889 ps
CPU time 42.28 seconds
Started Aug 27 07:11:23 AM UTC 24
Finished Aug 27 07:12:07 AM UTC 24
Peak memory 430112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882865996 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.3882865996
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.1542553628
Short name T738
Test name
Test status
Simulation time 4062676289 ps
CPU time 10 seconds
Started Aug 27 07:11:25 AM UTC 24
Finished Aug 27 07:11:36 AM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542553
628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.1542553628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.3725662133
Short name T753
Test name
Test status
Simulation time 133005936 ps
CPU time 4.26 seconds
Started Aug 27 07:11:43 AM UTC 24
Finished Aug 27 07:11:49 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725662
133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.3725662133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_alert_test.219009433
Short name T108
Test name
Test status
Simulation time 17153406 ps
CPU time 0.93 seconds
Started Aug 27 07:04:20 AM UTC 24
Finished Aug 27 07:04:21 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219009433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.219009433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.2313042638
Short name T25
Test name
Test status
Simulation time 254875983 ps
CPU time 3.28 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:15 AM UTC 24
Peak memory 230172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313042638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2313042638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.194621162
Short name T302
Test name
Test status
Simulation time 377319710 ps
CPU time 5.93 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:17 AM UTC 24
Peak memory 252036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194621162 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.194621162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.324186020
Short name T169
Test name
Test status
Simulation time 11763073716 ps
CPU time 109.09 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:06:02 AM UTC 24
Peak memory 581772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324186020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.324186020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.37733831
Short name T110
Test name
Test status
Simulation time 2774730061 ps
CPU time 70.63 seconds
Started Aug 27 07:04:09 AM UTC 24
Finished Aug 27 07:05:21 AM UTC 24
Peak memory 491748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37733831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.37733831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.361322591
Short name T43
Test name
Test status
Simulation time 426092369 ps
CPU time 1.49 seconds
Started Aug 27 07:04:09 AM UTC 24
Finished Aug 27 07:04:11 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361322591 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.361322591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.4227979075
Short name T15
Test name
Test status
Simulation time 495669319 ps
CPU time 19.09 seconds
Started Aug 27 07:04:16 AM UTC 24
Finished Aug 27 07:04:36 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227979075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.4227979075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_override.1030169999
Short name T109
Test name
Test status
Simulation time 34663674 ps
CPU time 1.03 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:04:10 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030169999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1030169999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_perf.162340626
Short name T197
Test name
Test status
Simulation time 1876698018 ps
CPU time 6.19 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:18 AM UTC 24
Peak memory 243720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162340626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.162340626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.3137021600
Short name T196
Test name
Test status
Simulation time 174914472 ps
CPU time 1.84 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:13 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137021600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.3137021600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.55398990
Short name T281
Test name
Test status
Simulation time 1323512361 ps
CPU time 62.02 seconds
Started Aug 27 07:04:07 AM UTC 24
Finished Aug 27 07:05:11 AM UTC 24
Peak memory 397456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55398990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.55398990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.1725420491
Short name T35
Test name
Test status
Simulation time 663733252 ps
CPU time 10.85 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 228924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725420491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1725420491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.2073856360
Short name T205
Test name
Test status
Simulation time 124910268 ps
CPU time 1.25 seconds
Started Aug 27 07:04:18 AM UTC 24
Finished Aug 27 07:04:21 AM UTC 24
Peak memory 246852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073856360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2073856360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3459825763
Short name T74
Test name
Test status
Simulation time 7287248808 ps
CPU time 8.02 seconds
Started Aug 27 07:04:14 AM UTC 24
Finished Aug 27 07:04:23 AM UTC 24
Peak memory 227112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3459825763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3459825763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.3081413667
Short name T316
Test name
Test status
Simulation time 454906034 ps
CPU time 2.65 seconds
Started Aug 27 07:04:13 AM UTC 24
Finished Aug 27 07:04:16 AM UTC 24
Peak memory 220620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081413
667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.3081413667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1735728786
Short name T315
Test name
Test status
Simulation time 398034221 ps
CPU time 1.47 seconds
Started Aug 27 07:04:14 AM UTC 24
Finished Aug 27 07:04:16 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735728
786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.1735728786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.2362628448
Short name T290
Test name
Test status
Simulation time 2057414409 ps
CPU time 3.51 seconds
Started Aug 27 07:04:16 AM UTC 24
Finished Aug 27 07:04:21 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362628
448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermark
s_acq.2362628448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.2323958535
Short name T314
Test name
Test status
Simulation time 795161504 ps
CPU time 1.35 seconds
Started Aug 27 07:04:17 AM UTC 24
Finished Aug 27 07:04:20 AM UTC 24
Peak memory 214224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323958
535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks
_tx.2323958535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_hrst.4056504138
Short name T200
Test name
Test status
Simulation time 1020790997 ps
CPU time 3.21 seconds
Started Aug 27 07:04:14 AM UTC 24
Finished Aug 27 07:04:18 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056504
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_hrst.4056504138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.2456704844
Short name T318
Test name
Test status
Simulation time 2114730240 ps
CPU time 5.91 seconds
Started Aug 27 07:04:11 AM UTC 24
Finished Aug 27 07:04:18 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245670
4844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.2456704844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.3865203603
Short name T589
Test name
Test status
Simulation time 18899284281 ps
CPU time 290.34 seconds
Started Aug 27 07:04:13 AM UTC 24
Finished Aug 27 07:09:07 AM UTC 24
Peak memory 4649364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3865203603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress
_wr.3865203603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.2938156659
Short name T162
Test name
Test status
Simulation time 2262743683 ps
CPU time 3.54 seconds
Started Aug 27 07:04:17 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938156
659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.2938156659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.79577443
Short name T77
Test name
Test status
Simulation time 6515848636 ps
CPU time 4.53 seconds
Started Aug 27 07:04:18 AM UTC 24
Finished Aug 27 07:04:24 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7957744
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.79577443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.1447058482
Short name T70
Test name
Test status
Simulation time 683080878 ps
CPU time 2.53 seconds
Started Aug 27 07:04:18 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 233500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447058
482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.1447058482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_perf.1378366290
Short name T320
Test name
Test status
Simulation time 946732579 ps
CPU time 9.34 seconds
Started Aug 27 07:04:14 AM UTC 24
Finished Aug 27 07:04:24 AM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378366
290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.1378366290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.2122886806
Short name T321
Test name
Test status
Simulation time 512500353 ps
CPU time 3.03 seconds
Started Aug 27 07:04:17 AM UTC 24
Finished Aug 27 07:04:21 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122886
806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.2122886806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.1377347319
Short name T323
Test name
Test status
Simulation time 683924979 ps
CPU time 10.05 seconds
Started Aug 27 07:04:10 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 226360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377347319 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.1377347319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.3833491904
Short name T225
Test name
Test status
Simulation time 53605532916 ps
CPU time 298.01 seconds
Started Aug 27 07:04:14 AM UTC 24
Finished Aug 27 07:09:15 AM UTC 24
Peak memory 2101656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383349
1904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.3833491904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.15902491
Short name T328
Test name
Test status
Simulation time 4180658070 ps
CPU time 15 seconds
Started Aug 27 07:04:11 AM UTC 24
Finished Aug 27 07:04:28 AM UTC 24
Peak memory 244132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15902491 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.15902491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.1015970993
Short name T322
Test name
Test status
Simulation time 12402928573 ps
CPU time 9 seconds
Started Aug 27 07:04:11 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 216740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015970993 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.1015970993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.3037515515
Short name T326
Test name
Test status
Simulation time 1053781667 ps
CPU time 12.52 seconds
Started Aug 27 07:04:11 AM UTC 24
Finished Aug 27 07:04:25 AM UTC 24
Peak memory 419920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037515515 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.3037515515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.2541399749
Short name T319
Test name
Test status
Simulation time 964518149 ps
CPU time 9.49 seconds
Started Aug 27 07:04:13 AM UTC 24
Finished Aug 27 07:04:23 AM UTC 24
Peak memory 232892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541399
749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.2541399749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3555453152
Short name T307
Test name
Test status
Simulation time 450148765 ps
CPU time 7 seconds
Started Aug 27 07:04:17 AM UTC 24
Finished Aug 27 07:04:25 AM UTC 24
Peak memory 216320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555453
152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3555453152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_alert_test.3381437447
Short name T784
Test name
Test status
Simulation time 15558566 ps
CPU time 0.92 seconds
Started Aug 27 07:12:14 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381437447 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3381437447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.350764720
Short name T765
Test name
Test status
Simulation time 189752396 ps
CPU time 7.2 seconds
Started Aug 27 07:11:52 AM UTC 24
Finished Aug 27 07:12:00 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350764720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.350764720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.3723471481
Short name T762
Test name
Test status
Simulation time 3225210938 ps
CPU time 6.21 seconds
Started Aug 27 07:11:49 AM UTC 24
Finished Aug 27 07:11:57 AM UTC 24
Peak memory 258204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723471481 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.3723471481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.2897004180
Short name T824
Test name
Test status
Simulation time 10754597030 ps
CPU time 57.16 seconds
Started Aug 27 07:11:49 AM UTC 24
Finished Aug 27 07:12:48 AM UTC 24
Peak memory 508172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897004180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2897004180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.4154743084
Short name T804
Test name
Test status
Simulation time 3606226739 ps
CPU time 43.71 seconds
Started Aug 27 07:11:48 AM UTC 24
Finished Aug 27 07:12:33 AM UTC 24
Peak memory 655636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154743084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.4154743084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.2734929993
Short name T763
Test name
Test status
Simulation time 1281504052 ps
CPU time 7.21 seconds
Started Aug 27 07:11:49 AM UTC 24
Finished Aug 27 07:11:58 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734929993 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.2734929993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.1514057740
Short name T126
Test name
Test status
Simulation time 3544002454 ps
CPU time 69.8 seconds
Started Aug 27 07:11:48 AM UTC 24
Finished Aug 27 07:13:00 AM UTC 24
Peak memory 1102032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514057740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1514057740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_mode_toggle.3848321834
Short name T776
Test name
Test status
Simulation time 234397905 ps
CPU time 1.26 seconds
Started Aug 27 07:12:07 AM UTC 24
Finished Aug 27 07:12:09 AM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848321834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3848321834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_override.2892172530
Short name T154
Test name
Test status
Simulation time 364256535 ps
CPU time 1.08 seconds
Started Aug 27 07:11:48 AM UTC 24
Finished Aug 27 07:11:50 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892172530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2892172530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_perf.3626869575
Short name T1236
Test name
Test status
Simulation time 12712461074 ps
CPU time 590.36 seconds
Started Aug 27 07:11:51 AM UTC 24
Finished Aug 27 07:21:48 AM UTC 24
Peak memory 1218892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626869575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3626869575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.2603216432
Short name T761
Test name
Test status
Simulation time 303845700 ps
CPU time 4.53 seconds
Started Aug 27 07:11:51 AM UTC 24
Finished Aug 27 07:11:56 AM UTC 24
Peak memory 239100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603216432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2603216432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.1527024778
Short name T827
Test name
Test status
Simulation time 2880612282 ps
CPU time 64.61 seconds
Started Aug 27 07:11:46 AM UTC 24
Finished Aug 27 07:12:52 AM UTC 24
Peak memory 315592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527024778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1527024778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.2870118795
Short name T771
Test name
Test status
Simulation time 2713475513 ps
CPU time 13.86 seconds
Started Aug 27 07:11:51 AM UTC 24
Finished Aug 27 07:12:06 AM UTC 24
Peak memory 228988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870118795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2870118795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.3558171832
Short name T791
Test name
Test status
Simulation time 2480270516 ps
CPU time 12.39 seconds
Started Aug 27 07:12:06 AM UTC 24
Finished Aug 27 07:12:20 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3558171832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.3558171832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.1942514741
Short name T768
Test name
Test status
Simulation time 221063709 ps
CPU time 2.31 seconds
Started Aug 27 07:12:02 AM UTC 24
Finished Aug 27 07:12:05 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942514
741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.1942514741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.886012517
Short name T773
Test name
Test status
Simulation time 251235687 ps
CPU time 2.96 seconds
Started Aug 27 07:12:03 AM UTC 24
Finished Aug 27 07:12:07 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8860125
17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.886012517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.57475917
Short name T781
Test name
Test status
Simulation time 6666939199 ps
CPU time 3.79 seconds
Started Aug 27 07:12:08 AM UTC 24
Finished Aug 27 07:12:13 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5747591
7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermarks
_acq.57475917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.926760641
Short name T779
Test name
Test status
Simulation time 317061330 ps
CPU time 1.78 seconds
Started Aug 27 07:12:08 AM UTC 24
Finished Aug 27 07:12:11 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9267606
41 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermarks
_tx.926760641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_hrst.2044230040
Short name T777
Test name
Test status
Simulation time 612247587 ps
CPU time 2.4 seconds
Started Aug 27 07:12:06 AM UTC 24
Finished Aug 27 07:12:10 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044230
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_hrst.2044230040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.4277679323
Short name T770
Test name
Test status
Simulation time 3151258220 ps
CPU time 6.67 seconds
Started Aug 27 07:11:57 AM UTC 24
Finished Aug 27 07:12:05 AM UTC 24
Peak memory 233836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427767
9323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.4277679323
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.4166952674
Short name T778
Test name
Test status
Simulation time 4011428130 ps
CPU time 11.5 seconds
Started Aug 27 07:11:58 AM UTC 24
Finished Aug 27 07:12:11 AM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4166952674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres
s_wr.4166952674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.2210208888
Short name T788
Test name
Test status
Simulation time 1236259077 ps
CPU time 4.9 seconds
Started Aug 27 07:12:11 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210208
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.2210208888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.1317124212
Short name T787
Test name
Test status
Simulation time 915385553 ps
CPU time 3.43 seconds
Started Aug 27 07:12:12 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317124
212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_ad
dr.1317124212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.3061022199
Short name T785
Test name
Test status
Simulation time 150281351 ps
CPU time 2.3 seconds
Started Aug 27 07:12:13 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 233476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061022
199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.3061022199
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_perf.3474377542
Short name T780
Test name
Test status
Simulation time 5304973530 ps
CPU time 6.73 seconds
Started Aug 27 07:12:05 AM UTC 24
Finished Aug 27 07:12:13 AM UTC 24
Peak memory 231280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474377
542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.3474377542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.343882271
Short name T783
Test name
Test status
Simulation time 624002042 ps
CPU time 4.01 seconds
Started Aug 27 07:12:11 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438822
71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.343882271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.743968989
Short name T796
Test name
Test status
Simulation time 7560944597 ps
CPU time 31.17 seconds
Started Aug 27 07:11:53 AM UTC 24
Finished Aug 27 07:12:26 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743968989 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.743968989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.1400493265
Short name T839
Test name
Test status
Simulation time 34182630902 ps
CPU time 65.01 seconds
Started Aug 27 07:12:06 AM UTC 24
Finished Aug 27 07:13:13 AM UTC 24
Peak memory 637340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140049
3265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.1400493265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.3467722977
Short name T828
Test name
Test status
Simulation time 5320128633 ps
CPU time 54.79 seconds
Started Aug 27 07:11:56 AM UTC 24
Finished Aug 27 07:12:53 AM UTC 24
Peak memory 231080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467722977 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.3467722977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2400794633
Short name T1116
Test name
Test status
Simulation time 40240903939 ps
CPU time 447.99 seconds
Started Aug 27 07:11:55 AM UTC 24
Finished Aug 27 07:19:28 AM UTC 24
Peak memory 5097620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400794633 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.2400794633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.31216417
Short name T831
Test name
Test status
Simulation time 1262030187 ps
CPU time 55.34 seconds
Started Aug 27 07:11:57 AM UTC 24
Finished Aug 27 07:12:54 AM UTC 24
Peak memory 471116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31216417 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.31216417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.2161463422
Short name T774
Test name
Test status
Simulation time 4744699112 ps
CPU time 6.69 seconds
Started Aug 27 07:11:59 AM UTC 24
Finished Aug 27 07:12:08 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161463
422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.2161463422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.2529158167
Short name T792
Test name
Test status
Simulation time 972736512 ps
CPU time 11.55 seconds
Started Aug 27 07:12:09 AM UTC 24
Finished Aug 27 07:12:22 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529158
167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2529158167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_alert_test.2088813836
Short name T819
Test name
Test status
Simulation time 131953843 ps
CPU time 0.89 seconds
Started Aug 27 07:12:45 AM UTC 24
Finished Aug 27 07:12:47 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088813836 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2088813836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.942381143
Short name T795
Test name
Test status
Simulation time 308007418 ps
CPU time 2.13 seconds
Started Aug 27 07:12:21 AM UTC 24
Finished Aug 27 07:12:24 AM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942381143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.942381143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.2735665964
Short name T797
Test name
Test status
Simulation time 348269014 ps
CPU time 8.43 seconds
Started Aug 27 07:12:17 AM UTC 24
Finished Aug 27 07:12:27 AM UTC 24
Peak memory 290696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735665964 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.2735665964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3933419890
Short name T855
Test name
Test status
Simulation time 7341073857 ps
CPU time 63.91 seconds
Started Aug 27 07:12:17 AM UTC 24
Finished Aug 27 07:13:23 AM UTC 24
Peak memory 469196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933419890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3933419890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.1286399508
Short name T898
Test name
Test status
Simulation time 1960774139 ps
CPU time 121.09 seconds
Started Aug 27 07:12:17 AM UTC 24
Finished Aug 27 07:14:21 AM UTC 24
Peak memory 694280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286399508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1286399508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.3378323797
Short name T790
Test name
Test status
Simulation time 283198487 ps
CPU time 1.2 seconds
Started Aug 27 07:12:17 AM UTC 24
Finished Aug 27 07:12:20 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378323797 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.3378323797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.1587690695
Short name T799
Test name
Test status
Simulation time 159374262 ps
CPU time 9.94 seconds
Started Aug 27 07:12:17 AM UTC 24
Finished Aug 27 07:12:29 AM UTC 24
Peak memory 241636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587690695 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.1587690695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.2059189676
Short name T127
Test name
Test status
Simulation time 3012430370 ps
CPU time 60.44 seconds
Started Aug 27 07:12:16 AM UTC 24
Finished Aug 27 07:13:18 AM UTC 24
Peak memory 983112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059189676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2059189676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.3984142802
Short name T270
Test name
Test status
Simulation time 690159230 ps
CPU time 17.11 seconds
Started Aug 27 07:12:38 AM UTC 24
Finished Aug 27 07:12:56 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984142802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3984142802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_mode_toggle.660866492
Short name T808
Test name
Test status
Simulation time 78696284 ps
CPU time 1.7 seconds
Started Aug 27 07:12:35 AM UTC 24
Finished Aug 27 07:12:38 AM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660866492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.660866492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_override.2896640725
Short name T155
Test name
Test status
Simulation time 20095428 ps
CPU time 1 seconds
Started Aug 27 07:12:15 AM UTC 24
Finished Aug 27 07:12:17 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896640725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2896640725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_perf.2629416991
Short name T794
Test name
Test status
Simulation time 605708192 ps
CPU time 3.82 seconds
Started Aug 27 07:12:19 AM UTC 24
Finished Aug 27 07:12:24 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629416991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2629416991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.3411422643
Short name T793
Test name
Test status
Simulation time 92927497 ps
CPU time 3.18 seconds
Started Aug 27 07:12:19 AM UTC 24
Finished Aug 27 07:12:23 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411422643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3411422643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.659763736
Short name T822
Test name
Test status
Simulation time 2745328303 ps
CPU time 32.24 seconds
Started Aug 27 07:12:14 AM UTC 24
Finished Aug 27 07:12:48 AM UTC 24
Peak memory 417944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659763736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.659763736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.688481190
Short name T814
Test name
Test status
Simulation time 1456037521 ps
CPU time 21.81 seconds
Started Aug 27 07:12:21 AM UTC 24
Finished Aug 27 07:12:44 AM UTC 24
Peak memory 233320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688481190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.688481190
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.299560085
Short name T812
Test name
Test status
Simulation time 973417595 ps
CPU time 6.53 seconds
Started Aug 27 07:12:34 AM UTC 24
Finished Aug 27 07:12:41 AM UTC 24
Peak memory 233748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=299560085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.299560085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.1492448480
Short name T803
Test name
Test status
Simulation time 208182173 ps
CPU time 1.36 seconds
Started Aug 27 07:12:30 AM UTC 24
Finished Aug 27 07:12:33 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492448
480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.1492448480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.3832630546
Short name T805
Test name
Test status
Simulation time 169345479 ps
CPU time 1.74 seconds
Started Aug 27 07:12:32 AM UTC 24
Finished Aug 27 07:12:34 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832630
546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.3832630546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.534782920
Short name T815
Test name
Test status
Simulation time 1947526265 ps
CPU time 5.01 seconds
Started Aug 27 07:12:38 AM UTC 24
Finished Aug 27 07:12:44 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5347829
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_acq.534782920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.2181400499
Short name T813
Test name
Test status
Simulation time 127230706 ps
CPU time 2.04 seconds
Started Aug 27 07:12:39 AM UTC 24
Finished Aug 27 07:12:42 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181400
499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.2181400499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.2330434490
Short name T809
Test name
Test status
Simulation time 224516945 ps
CPU time 3.03 seconds
Started Aug 27 07:12:34 AM UTC 24
Finished Aug 27 07:12:38 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330434
490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.2330434490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.1931352791
Short name T802
Test name
Test status
Simulation time 3152653174 ps
CPU time 4.87 seconds
Started Aug 27 07:12:26 AM UTC 24
Finished Aug 27 07:12:32 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193135
2791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.1931352791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.1998196819
Short name T830
Test name
Test status
Simulation time 25587496558 ps
CPU time 24.78 seconds
Started Aug 27 07:12:28 AM UTC 24
Finished Aug 27 07:12:54 AM UTC 24
Peak memory 682396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1998196819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.1998196819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.3392388256
Short name T821
Test name
Test status
Simulation time 1893651096 ps
CPU time 4.92 seconds
Started Aug 27 07:12:41 AM UTC 24
Finished Aug 27 07:12:47 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392388
256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.3392388256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.3155390468
Short name T825
Test name
Test status
Simulation time 1110206537 ps
CPU time 5.53 seconds
Started Aug 27 07:12:43 AM UTC 24
Finished Aug 27 07:12:49 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155390
468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_ad
dr.3155390468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_perf.783818426
Short name T816
Test name
Test status
Simulation time 1959574362 ps
CPU time 11.07 seconds
Started Aug 27 07:12:33 AM UTC 24
Finished Aug 27 07:12:45 AM UTC 24
Peak memory 233276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7838184
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.783818426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.917628421
Short name T817
Test name
Test status
Simulation time 481915226 ps
CPU time 3.85 seconds
Started Aug 27 07:12:41 AM UTC 24
Finished Aug 27 07:12:46 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9176284
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.917628421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.559378038
Short name T806
Test name
Test status
Simulation time 2158506895 ps
CPU time 12.39 seconds
Started Aug 27 07:12:23 AM UTC 24
Finished Aug 27 07:12:37 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559378038 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.559378038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.4267708694
Short name T917
Test name
Test status
Simulation time 51825766942 ps
CPU time 133.24 seconds
Started Aug 27 07:12:34 AM UTC 24
Finished Aug 27 07:14:49 AM UTC 24
Peak memory 1482976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426770
8694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.4267708694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.2818019944
Short name T838
Test name
Test status
Simulation time 1068843540 ps
CPU time 45.71 seconds
Started Aug 27 07:12:25 AM UTC 24
Finished Aug 27 07:13:13 AM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818019944 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.2818019944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.10266678
Short name T928
Test name
Test status
Simulation time 30490388985 ps
CPU time 157.5 seconds
Started Aug 27 07:12:24 AM UTC 24
Finished Aug 27 07:15:04 AM UTC 24
Peak memory 2797776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10266678 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.10266678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.4088960378
Short name T801
Test name
Test status
Simulation time 326599633 ps
CPU time 4.53 seconds
Started Aug 27 07:12:25 AM UTC 24
Finished Aug 27 07:12:31 AM UTC 24
Peak memory 244004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088960378 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.4088960378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.1328770311
Short name T807
Test name
Test status
Simulation time 1327977291 ps
CPU time 7.86 seconds
Started Aug 27 07:12:28 AM UTC 24
Finished Aug 27 07:12:37 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328770
311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.1328770311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2921933070
Short name T818
Test name
Test status
Simulation time 255645165 ps
CPU time 6.29 seconds
Started Aug 27 07:12:39 AM UTC 24
Finished Aug 27 07:12:47 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921933
070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2921933070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_alert_test.3262556167
Short name T842
Test name
Test status
Simulation time 133940871 ps
CPU time 0.91 seconds
Started Aug 27 07:13:14 AM UTC 24
Finished Aug 27 07:13:16 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262556167 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3262556167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.3474818662
Short name T98
Test name
Test status
Simulation time 266134688 ps
CPU time 12.17 seconds
Started Aug 27 07:12:52 AM UTC 24
Finished Aug 27 07:13:05 AM UTC 24
Peak memory 245912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474818662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3474818662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.2025290810
Short name T837
Test name
Test status
Simulation time 535105295 ps
CPU time 14.54 seconds
Started Aug 27 07:12:48 AM UTC 24
Finished Aug 27 07:13:04 AM UTC 24
Peak memory 270624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025290810 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.2025290810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.2935618695
Short name T961
Test name
Test status
Simulation time 11704708942 ps
CPU time 163.71 seconds
Started Aug 27 07:12:48 AM UTC 24
Finished Aug 27 07:15:35 AM UTC 24
Peak memory 495832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935618695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2935618695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.2195201485
Short name T956
Test name
Test status
Simulation time 4355934519 ps
CPU time 154.04 seconds
Started Aug 27 07:12:48 AM UTC 24
Finished Aug 27 07:15:25 AM UTC 24
Peak memory 747640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195201485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2195201485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.1001987234
Short name T826
Test name
Test status
Simulation time 554977945 ps
CPU time 1.46 seconds
Started Aug 27 07:12:48 AM UTC 24
Finished Aug 27 07:12:51 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001987234 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.1001987234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.1717802353
Short name T829
Test name
Test status
Simulation time 597356608 ps
CPU time 4.84 seconds
Started Aug 27 07:12:48 AM UTC 24
Finished Aug 27 07:12:54 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717802353 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.1717802353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.1612252066
Short name T1064
Test name
Test status
Simulation time 5103176612 ps
CPU time 279.94 seconds
Started Aug 27 07:12:47 AM UTC 24
Finished Aug 27 07:17:31 AM UTC 24
Peak memory 1522016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612252066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1612252066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.3357859058
Short name T850
Test name
Test status
Simulation time 854600056 ps
CPU time 11.66 seconds
Started Aug 27 07:13:06 AM UTC 24
Finished Aug 27 07:13:19 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357859058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3357859058
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_mode_toggle.3029061427
Short name T106
Test name
Test status
Simulation time 204788929 ps
CPU time 5.17 seconds
Started Aug 27 07:13:06 AM UTC 24
Finished Aug 27 07:13:12 AM UTC 24
Peak memory 230936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029061427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3029061427
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_override.1223191324
Short name T823
Test name
Test status
Simulation time 86060745 ps
CPU time 1 seconds
Started Aug 27 07:12:46 AM UTC 24
Finished Aug 27 07:12:48 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223191324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.1223191324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_perf.333481964
Short name T101
Test name
Test status
Simulation time 3171756267 ps
CPU time 16.78 seconds
Started Aug 27 07:12:49 AM UTC 24
Finished Aug 27 07:13:07 AM UTC 24
Peak memory 387236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333481964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.333481964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.3386783299
Short name T833
Test name
Test status
Simulation time 675461014 ps
CPU time 6.05 seconds
Started Aug 27 07:12:49 AM UTC 24
Finished Aug 27 07:12:56 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386783299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3386783299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.2734815166
Short name T852
Test name
Test status
Simulation time 9044059251 ps
CPU time 33.48 seconds
Started Aug 27 07:12:45 AM UTC 24
Finished Aug 27 07:13:20 AM UTC 24
Peak memory 403632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734815166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2734815166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.3906342560
Short name T858
Test name
Test status
Simulation time 2907640154 ps
CPU time 36.22 seconds
Started Aug 27 07:12:51 AM UTC 24
Finished Aug 27 07:13:28 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906342560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3906342560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.3507682595
Short name T841
Test name
Test status
Simulation time 3923689544 ps
CPU time 7.96 seconds
Started Aug 27 07:13:05 AM UTC 24
Finished Aug 27 07:13:14 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3507682595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_ad
dr.3507682595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.2339032059
Short name T99
Test name
Test status
Simulation time 977827401 ps
CPU time 1.87 seconds
Started Aug 27 07:13:02 AM UTC 24
Finished Aug 27 07:13:05 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339032
059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.2339032059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.4091347029
Short name T100
Test name
Test status
Simulation time 215756131 ps
CPU time 1.2 seconds
Started Aug 27 07:13:04 AM UTC 24
Finished Aug 27 07:13:06 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091347
029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.4091347029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.341021306
Short name T840
Test name
Test status
Simulation time 1928523854 ps
CPU time 4.99 seconds
Started Aug 27 07:13:07 AM UTC 24
Finished Aug 27 07:13:13 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410213
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_acq.341021306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.2446054167
Short name T105
Test name
Test status
Simulation time 175858047 ps
CPU time 2.78 seconds
Started Aug 27 07:13:08 AM UTC 24
Finished Aug 27 07:13:12 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446054
167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_tx.2446054167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_hrst.863285796
Short name T103
Test name
Test status
Simulation time 2110682482 ps
CPU time 4.72 seconds
Started Aug 27 07:13:05 AM UTC 24
Finished Aug 27 07:13:11 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8632857
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.863285796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.2758169077
Short name T834
Test name
Test status
Simulation time 1746672839 ps
CPU time 3.53 seconds
Started Aug 27 07:12:57 AM UTC 24
Finished Aug 27 07:13:02 AM UTC 24
Peak memory 230928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275816
9077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.2758169077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.3982405657
Short name T846
Test name
Test status
Simulation time 14576460412 ps
CPU time 18.91 seconds
Started Aug 27 07:12:57 AM UTC 24
Finished Aug 27 07:13:17 AM UTC 24
Peak memory 508308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3982405657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.3982405657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.1066393900
Short name T849
Test name
Test status
Simulation time 448535440 ps
CPU time 4.24 seconds
Started Aug 27 07:13:13 AM UTC 24
Finished Aug 27 07:13:18 AM UTC 24
Peak memory 216540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066393
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_ad
dr.1066393900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_perf.2925998877
Short name T104
Test name
Test status
Simulation time 1160055371 ps
CPU time 7.14 seconds
Started Aug 27 07:13:04 AM UTC 24
Finished Aug 27 07:13:12 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925998
877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.2925998877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.1562063520
Short name T844
Test name
Test status
Simulation time 4639435748 ps
CPU time 4.2 seconds
Started Aug 27 07:13:11 AM UTC 24
Finished Aug 27 07:13:17 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562063
520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.1562063520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.3566936930
Short name T285
Test name
Test status
Simulation time 5946212317 ps
CPU time 47.43 seconds
Started Aug 27 07:13:04 AM UTC 24
Finished Aug 27 07:13:53 AM UTC 24
Peak memory 276680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356693
6930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.3566936930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.2627065298
Short name T847
Test name
Test status
Simulation time 1048424256 ps
CPU time 21.43 seconds
Started Aug 27 07:12:55 AM UTC 24
Finished Aug 27 07:13:18 AM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627065298 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.2627065298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.3709706790
Short name T1001
Test name
Test status
Simulation time 45477574586 ps
CPU time 199.03 seconds
Started Aug 27 07:12:55 AM UTC 24
Finished Aug 27 07:16:16 AM UTC 24
Peak memory 3225748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709706790 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.3709706790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.3793809576
Short name T845
Test name
Test status
Simulation time 650608706 ps
CPU time 20.67 seconds
Started Aug 27 07:12:55 AM UTC 24
Finished Aug 27 07:13:17 AM UTC 24
Peak memory 313376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793809576 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.3793809576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.2010239913
Short name T102
Test name
Test status
Simulation time 1262401691 ps
CPU time 11.61 seconds
Started Aug 27 07:12:57 AM UTC 24
Finished Aug 27 07:13:10 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010239
913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.2010239913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.112310520
Short name T853
Test name
Test status
Simulation time 574970272 ps
CPU time 8.92 seconds
Started Aug 27 07:13:10 AM UTC 24
Finished Aug 27 07:13:20 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123105
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.112310520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_alert_test.3524074419
Short name T876
Test name
Test status
Simulation time 43657455 ps
CPU time 0.89 seconds
Started Aug 27 07:13:44 AM UTC 24
Finished Aug 27 07:13:46 AM UTC 24
Peak memory 214064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524074419 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3524074419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.3745704094
Short name T854
Test name
Test status
Simulation time 56015011 ps
CPU time 2.27 seconds
Started Aug 27 07:13:20 AM UTC 24
Finished Aug 27 07:13:23 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745704094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3745704094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.3176036978
Short name T868
Test name
Test status
Simulation time 355268440 ps
CPU time 20.98 seconds
Started Aug 27 07:13:17 AM UTC 24
Finished Aug 27 07:13:39 AM UTC 24
Peak memory 292896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176036978 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.3176036978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.1116183880
Short name T936
Test name
Test status
Simulation time 4179219392 ps
CPU time 110.42 seconds
Started Aug 27 07:13:18 AM UTC 24
Finished Aug 27 07:15:11 AM UTC 24
Peak memory 641136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116183880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1116183880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.1753009690
Short name T951
Test name
Test status
Simulation time 23442412634 ps
CPU time 122.54 seconds
Started Aug 27 07:13:16 AM UTC 24
Finished Aug 27 07:15:21 AM UTC 24
Peak memory 753824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753009690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1753009690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.1588598262
Short name T851
Test name
Test status
Simulation time 149086802 ps
CPU time 1.76 seconds
Started Aug 27 07:13:16 AM UTC 24
Finished Aug 27 07:13:19 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588598262 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.1588598262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.3560881606
Short name T857
Test name
Test status
Simulation time 181530275 ps
CPU time 7.03 seconds
Started Aug 27 07:13:18 AM UTC 24
Finished Aug 27 07:13:26 AM UTC 24
Peak memory 247844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560881606 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.3560881606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.404097431
Short name T979
Test name
Test status
Simulation time 10313107322 ps
CPU time 151.93 seconds
Started Aug 27 07:13:15 AM UTC 24
Finished Aug 27 07:15:49 AM UTC 24
Peak memory 1562748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404097431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.404097431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.1390299298
Short name T875
Test name
Test status
Simulation time 570143572 ps
CPU time 6.3 seconds
Started Aug 27 07:13:38 AM UTC 24
Finished Aug 27 07:13:45 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390299298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1390299298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_override.2274313005
Short name T843
Test name
Test status
Simulation time 19415546 ps
CPU time 0.84 seconds
Started Aug 27 07:13:14 AM UTC 24
Finished Aug 27 07:13:16 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274313005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2274313005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_perf.2180579944
Short name T930
Test name
Test status
Simulation time 25987014566 ps
CPU time 105.35 seconds
Started Aug 27 07:13:18 AM UTC 24
Finished Aug 27 07:15:06 AM UTC 24
Peak memory 233688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180579944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2180579944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.2223446950
Short name T949
Test name
Test status
Simulation time 2485849116 ps
CPU time 118.43 seconds
Started Aug 27 07:13:18 AM UTC 24
Finished Aug 27 07:15:19 AM UTC 24
Peak memory 216936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223446950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.2223446950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.677607405
Short name T900
Test name
Test status
Simulation time 3192710129 ps
CPU time 68.13 seconds
Started Aug 27 07:13:14 AM UTC 24
Finished Aug 27 07:14:23 AM UTC 24
Peak memory 442512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677607405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.677607405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.1282792991
Short name T1740
Test name
Test status
Simulation time 24432050068 ps
CPU time 1329.71 seconds
Started Aug 27 07:13:20 AM UTC 24
Finished Aug 27 07:35:43 AM UTC 24
Peak memory 2867472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282792991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1282792991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.3117205851
Short name T884
Test name
Test status
Simulation time 949621584 ps
CPU time 41.23 seconds
Started Aug 27 07:13:19 AM UTC 24
Finished Aug 27 07:14:01 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117205851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3117205851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.1683390198
Short name T870
Test name
Test status
Simulation time 1887169310 ps
CPU time 7.14 seconds
Started Aug 27 07:13:34 AM UTC 24
Finished Aug 27 07:13:42 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1683390198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_ad
dr.1683390198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.1311099693
Short name T860
Test name
Test status
Simulation time 233987274 ps
CPU time 1.21 seconds
Started Aug 27 07:13:28 AM UTC 24
Finished Aug 27 07:13:31 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311099
693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.1311099693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.2685973966
Short name T862
Test name
Test status
Simulation time 154045878 ps
CPU time 1.81 seconds
Started Aug 27 07:13:31 AM UTC 24
Finished Aug 27 07:13:33 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685973
966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.2685973966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.915129669
Short name T872
Test name
Test status
Simulation time 374273743 ps
CPU time 3.56 seconds
Started Aug 27 07:13:38 AM UTC 24
Finished Aug 27 07:13:43 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9151296
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_acq.915129669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.3958996654
Short name T871
Test name
Test status
Simulation time 598588899 ps
CPU time 2.39 seconds
Started Aug 27 07:13:39 AM UTC 24
Finished Aug 27 07:13:43 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958996
654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.3958996654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.1691111434
Short name T867
Test name
Test status
Simulation time 217620443 ps
CPU time 2.75 seconds
Started Aug 27 07:13:35 AM UTC 24
Finished Aug 27 07:13:39 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691111
434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.1691111434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.2648966581
Short name T863
Test name
Test status
Simulation time 2616837593 ps
CPU time 10.96 seconds
Started Aug 27 07:13:24 AM UTC 24
Finished Aug 27 07:13:36 AM UTC 24
Peak memory 248012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264896
6581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.2648966581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.2184382031
Short name T891
Test name
Test status
Simulation time 10182487274 ps
CPU time 48.11 seconds
Started Aug 27 07:13:24 AM UTC 24
Finished Aug 27 07:14:14 AM UTC 24
Peak memory 1591448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2184382031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stres
s_wr.2184382031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.2543368648
Short name T878
Test name
Test status
Simulation time 1876670976 ps
CPU time 4.65 seconds
Started Aug 27 07:13:40 AM UTC 24
Finished Aug 27 07:13:46 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543368
648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.2543368648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.2201169702
Short name T879
Test name
Test status
Simulation time 1971772961 ps
CPU time 5.23 seconds
Started Aug 27 07:13:40 AM UTC 24
Finished Aug 27 07:13:47 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201169
702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_ad
dr.2201169702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_perf.2488750948
Short name T869
Test name
Test status
Simulation time 766669984 ps
CPU time 8.21 seconds
Started Aug 27 07:13:31 AM UTC 24
Finished Aug 27 07:13:40 AM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488750
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.2488750948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.3488150769
Short name T873
Test name
Test status
Simulation time 3850979851 ps
CPU time 3.68 seconds
Started Aug 27 07:13:39 AM UTC 24
Finished Aug 27 07:13:44 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488150
769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.3488150769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.3256024907
Short name T92
Test name
Test status
Simulation time 4626970124 ps
CPU time 42.91 seconds
Started Aug 27 07:13:20 AM UTC 24
Finished Aug 27 07:14:04 AM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256024907 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.3256024907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.3114533481
Short name T1742
Test name
Test status
Simulation time 59716282163 ps
CPU time 1331.85 seconds
Started Aug 27 07:13:32 AM UTC 24
Finished Aug 27 07:35:57 AM UTC 24
Peak memory 9515168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311453
3481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.3114533481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.3374726741
Short name T877
Test name
Test status
Simulation time 1785411380 ps
CPU time 38.59 seconds
Started Aug 27 07:13:21 AM UTC 24
Finished Aug 27 07:14:01 AM UTC 24
Peak memory 244116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374726741 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.3374726741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.3184932456
Short name T896
Test name
Test status
Simulation time 31757181616 ps
CPU time 58.39 seconds
Started Aug 27 07:13:20 AM UTC 24
Finished Aug 27 07:14:20 AM UTC 24
Peak memory 823708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184932456 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.3184932456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.4115265528
Short name T866
Test name
Test status
Simulation time 5053059542 ps
CPU time 16.46 seconds
Started Aug 27 07:13:21 AM UTC 24
Finished Aug 27 07:13:39 AM UTC 24
Peak memory 387288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115265528 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.4115265528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.2390239221
Short name T865
Test name
Test status
Simulation time 1119480824 ps
CPU time 8.67 seconds
Started Aug 27 07:13:27 AM UTC 24
Finished Aug 27 07:13:37 AM UTC 24
Peak memory 233308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390239
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.2390239221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.1736005798
Short name T874
Test name
Test status
Simulation time 119944461 ps
CPU time 4.58 seconds
Started Aug 27 07:13:39 AM UTC 24
Finished Aug 27 07:13:45 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736005
798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1736005798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_alert_test.3587872498
Short name T904
Test name
Test status
Simulation time 24100152 ps
CPU time 0.94 seconds
Started Aug 27 07:14:26 AM UTC 24
Finished Aug 27 07:14:28 AM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587872498 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3587872498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.3317088394
Short name T885
Test name
Test status
Simulation time 1004628235 ps
CPU time 8.34 seconds
Started Aug 27 07:13:54 AM UTC 24
Finished Aug 27 07:14:03 AM UTC 24
Peak memory 245864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317088394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3317088394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.2692009953
Short name T820
Test name
Test status
Simulation time 771371741 ps
CPU time 12.88 seconds
Started Aug 27 07:13:47 AM UTC 24
Finished Aug 27 07:14:01 AM UTC 24
Peak memory 254244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692009953 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.2692009953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.1923621633
Short name T920
Test name
Test status
Simulation time 2229336790 ps
CPU time 63.11 seconds
Started Aug 27 07:13:47 AM UTC 24
Finished Aug 27 07:14:52 AM UTC 24
Peak memory 313940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923621633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1923621633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.1706920330
Short name T944
Test name
Test status
Simulation time 38168604159 ps
CPU time 87.45 seconds
Started Aug 27 07:13:46 AM UTC 24
Finished Aug 27 07:15:15 AM UTC 24
Peak memory 803024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706920330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1706920330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.2134763260
Short name T882
Test name
Test status
Simulation time 853054408 ps
CPU time 1.57 seconds
Started Aug 27 07:13:46 AM UTC 24
Finished Aug 27 07:13:49 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134763260 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.2134763260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.2081831444
Short name T848
Test name
Test status
Simulation time 1186323460 ps
CPU time 4.43 seconds
Started Aug 27 07:13:47 AM UTC 24
Finished Aug 27 07:13:53 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081831444 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.2081831444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3155753251
Short name T919
Test name
Test status
Simulation time 2549957732 ps
CPU time 62.76 seconds
Started Aug 27 07:13:46 AM UTC 24
Finished Aug 27 07:14:50 AM UTC 24
Peak memory 796808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155753251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3155753251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.4099038629
Short name T262
Test name
Test status
Simulation time 2626785320 ps
CPU time 5.84 seconds
Started Aug 27 07:14:19 AM UTC 24
Finished Aug 27 07:14:26 AM UTC 24
Peak memory 216744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099038629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.4099038629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_override.33844950
Short name T880
Test name
Test status
Simulation time 26549762 ps
CPU time 1.01 seconds
Started Aug 27 07:13:45 AM UTC 24
Finished Aug 27 07:13:47 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33844950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.33844950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_perf.837720985
Short name T888
Test name
Test status
Simulation time 20678030897 ps
CPU time 22.44 seconds
Started Aug 27 07:13:47 AM UTC 24
Finished Aug 27 07:14:11 AM UTC 24
Peak memory 385204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837720985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.837720985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.1683662964
Short name T1167
Test name
Test status
Simulation time 23265595326 ps
CPU time 383.57 seconds
Started Aug 27 07:13:48 AM UTC 24
Finished Aug 27 07:20:17 AM UTC 24
Peak memory 216612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683662964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1683662964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.653358924
Short name T940
Test name
Test status
Simulation time 1916130445 ps
CPU time 87.51 seconds
Started Aug 27 07:13:44 AM UTC 24
Finished Aug 27 07:15:13 AM UTC 24
Peak memory 315584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653358924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.653358924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.1987146002
Short name T910
Test name
Test status
Simulation time 854598140 ps
CPU time 37.94 seconds
Started Aug 27 07:13:50 AM UTC 24
Finished Aug 27 07:14:29 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987146002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1987146002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.3619385285
Short name T905
Test name
Test status
Simulation time 1184893374 ps
CPU time 12.2 seconds
Started Aug 27 07:14:15 AM UTC 24
Finished Aug 27 07:14:28 AM UTC 24
Peak memory 220704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3619385285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.3619385285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.2697242611
Short name T889
Test name
Test status
Simulation time 388434462 ps
CPU time 2.21 seconds
Started Aug 27 07:14:10 AM UTC 24
Finished Aug 27 07:14:14 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697242
611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.2697242611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.597580122
Short name T892
Test name
Test status
Simulation time 278137145 ps
CPU time 2.57 seconds
Started Aug 27 07:14:11 AM UTC 24
Finished Aug 27 07:14:15 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5975801
22 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.597580122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1981045952
Short name T902
Test name
Test status
Simulation time 528825145 ps
CPU time 5.05 seconds
Started Aug 27 07:14:19 AM UTC 24
Finished Aug 27 07:14:25 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981045
952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar
ks_acq.1981045952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.3795426764
Short name T899
Test name
Test status
Simulation time 836645994 ps
CPU time 1.35 seconds
Started Aug 27 07:14:20 AM UTC 24
Finished Aug 27 07:14:22 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795426
764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.3795426764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.868430194
Short name T890
Test name
Test status
Simulation time 730250428 ps
CPU time 8.63 seconds
Started Aug 27 07:14:04 AM UTC 24
Finished Aug 27 07:14:14 AM UTC 24
Peak memory 233268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868430
194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.868430194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.4100672651
Short name T1075
Test name
Test status
Simulation time 18193539633 ps
CPU time 221.62 seconds
Started Aug 27 07:14:05 AM UTC 24
Finished Aug 27 07:17:50 AM UTC 24
Peak memory 2930836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4100672651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.4100672651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.162269304
Short name T906
Test name
Test status
Simulation time 1548500865 ps
CPU time 4.57 seconds
Started Aug 27 07:14:22 AM UTC 24
Finished Aug 27 07:14:28 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622693
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.162269304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.4053873682
Short name T908
Test name
Test status
Simulation time 944613200 ps
CPU time 3.99 seconds
Started Aug 27 07:14:23 AM UTC 24
Finished Aug 27 07:14:28 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053873
682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_ad
dr.4053873682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.3977102016
Short name T907
Test name
Test status
Simulation time 529082996 ps
CPU time 2.53 seconds
Started Aug 27 07:14:24 AM UTC 24
Finished Aug 27 07:14:28 AM UTC 24
Peak memory 233488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977102
016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_txstretch.3977102016
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_perf.618935721
Short name T897
Test name
Test status
Simulation time 3316347586 ps
CPU time 7.81 seconds
Started Aug 27 07:14:12 AM UTC 24
Finished Aug 27 07:14:20 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6189357
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.618935721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.4174459937
Short name T903
Test name
Test status
Simulation time 2374054732 ps
CPU time 4.12 seconds
Started Aug 27 07:14:21 AM UTC 24
Finished Aug 27 07:14:26 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174459
937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.4174459937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.2445397536
Short name T894
Test name
Test status
Simulation time 9243932651 ps
CPU time 23.09 seconds
Started Aug 27 07:13:54 AM UTC 24
Finished Aug 27 07:14:18 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445397536 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.2445397536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.2326543087
Short name T1178
Test name
Test status
Simulation time 28111402068 ps
CPU time 386.19 seconds
Started Aug 27 07:14:15 AM UTC 24
Finished Aug 27 07:20:45 AM UTC 24
Peak memory 4847772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232654
3087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.2326543087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.808889847
Short name T887
Test name
Test status
Simulation time 1046030269 ps
CPU time 7.34 seconds
Started Aug 27 07:14:02 AM UTC 24
Finished Aug 27 07:14:10 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808889847 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.808889847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.3357136144
Short name T918
Test name
Test status
Simulation time 12231792062 ps
CPU time 46.57 seconds
Started Aug 27 07:14:02 AM UTC 24
Finished Aug 27 07:14:50 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357136144 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.3357136144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.2326592781
Short name T886
Test name
Test status
Simulation time 369492757 ps
CPU time 1.68 seconds
Started Aug 27 07:14:02 AM UTC 24
Finished Aug 27 07:14:05 AM UTC 24
Peak memory 216232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326592781 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.2326592781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.652484304
Short name T895
Test name
Test status
Simulation time 6042965372 ps
CPU time 13.18 seconds
Started Aug 27 07:14:05 AM UTC 24
Finished Aug 27 07:14:20 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6524843
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.652484304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.784146923
Short name T901
Test name
Test status
Simulation time 76147079 ps
CPU time 2.84 seconds
Started Aug 27 07:14:21 AM UTC 24
Finished Aug 27 07:14:25 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7841469
23 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.784146923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_alert_test.1069119381
Short name T938
Test name
Test status
Simulation time 21370694 ps
CPU time 0.9 seconds
Started Aug 27 07:15:11 AM UTC 24
Finished Aug 27 07:15:12 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069119381 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1069119381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.53202543
Short name T913
Test name
Test status
Simulation time 133454366 ps
CPU time 1.96 seconds
Started Aug 27 07:14:34 AM UTC 24
Finished Aug 27 07:14:37 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53202543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.53202543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.641142303
Short name T914
Test name
Test status
Simulation time 728169017 ps
CPU time 9.42 seconds
Started Aug 27 07:14:29 AM UTC 24
Finished Aug 27 07:14:40 AM UTC 24
Peak memory 293004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641142303 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.641142303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.3429058874
Short name T1025
Test name
Test status
Simulation time 2222080602 ps
CPU time 132.26 seconds
Started Aug 27 07:14:29 AM UTC 24
Finished Aug 27 07:16:44 AM UTC 24
Peak memory 620776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429058874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3429058874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.148242755
Short name T991
Test name
Test status
Simulation time 5269683441 ps
CPU time 99.95 seconds
Started Aug 27 07:14:28 AM UTC 24
Finished Aug 27 07:16:10 AM UTC 24
Peak memory 522472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148242755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.148242755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.3674967547
Short name T911
Test name
Test status
Simulation time 202705100 ps
CPU time 1.77 seconds
Started Aug 27 07:14:29 AM UTC 24
Finished Aug 27 07:14:32 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674967547 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.3674967547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.1211697496
Short name T915
Test name
Test status
Simulation time 532444244 ps
CPU time 9.65 seconds
Started Aug 27 07:14:29 AM UTC 24
Finished Aug 27 07:14:40 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211697496 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.1211697496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.3594632560
Short name T981
Test name
Test status
Simulation time 7845653606 ps
CPU time 81.83 seconds
Started Aug 27 07:14:27 AM UTC 24
Finished Aug 27 07:15:50 AM UTC 24
Peak memory 1073224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594632560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3594632560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.2688826166
Short name T271
Test name
Test status
Simulation time 2588805641 ps
CPU time 31.79 seconds
Started Aug 27 07:15:05 AM UTC 24
Finished Aug 27 07:15:38 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688826166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2688826166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_override.2417431706
Short name T909
Test name
Test status
Simulation time 29644763 ps
CPU time 0.94 seconds
Started Aug 27 07:14:27 AM UTC 24
Finished Aug 27 07:14:29 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417431706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2417431706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2513577889
Short name T964
Test name
Test status
Simulation time 2659517493 ps
CPU time 68.73 seconds
Started Aug 27 07:14:29 AM UTC 24
Finished Aug 27 07:15:40 AM UTC 24
Peak memory 669912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513577889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2513577889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.4258401835
Short name T912
Test name
Test status
Simulation time 61766385 ps
CPU time 2.25 seconds
Started Aug 27 07:14:30 AM UTC 24
Finished Aug 27 07:14:34 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258401835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.4258401835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.385392948
Short name T957
Test name
Test status
Simulation time 9030518697 ps
CPU time 59.72 seconds
Started Aug 27 07:14:26 AM UTC 24
Finished Aug 27 07:15:27 AM UTC 24
Peak memory 395596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385392948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.385392948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_stress_all.1173267509
Short name T1734
Test name
Test status
Simulation time 55345347402 ps
CPU time 1179.07 seconds
Started Aug 27 07:14:39 AM UTC 24
Finished Aug 27 07:34:30 AM UTC 24
Peak memory 4858084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173267509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1173267509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.1846422630
Short name T916
Test name
Test status
Simulation time 2662176275 ps
CPU time 13.3 seconds
Started Aug 27 07:14:32 AM UTC 24
Finished Aug 27 07:14:47 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846422630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1846422630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.2474850783
Short name T935
Test name
Test status
Simulation time 4035611000 ps
CPU time 8.39 seconds
Started Aug 27 07:15:01 AM UTC 24
Finished Aug 27 07:15:10 AM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2474850783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.2474850783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.3509837046
Short name T925
Test name
Test status
Simulation time 369704080 ps
CPU time 1.94 seconds
Started Aug 27 07:14:56 AM UTC 24
Finished Aug 27 07:14:59 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509837
046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.3509837046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.1487020492
Short name T926
Test name
Test status
Simulation time 354478413 ps
CPU time 1.3 seconds
Started Aug 27 07:14:57 AM UTC 24
Finished Aug 27 07:15:00 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487020
492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.1487020492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.2395486525
Short name T937
Test name
Test status
Simulation time 455120446 ps
CPU time 4.5 seconds
Started Aug 27 07:15:06 AM UTC 24
Finished Aug 27 07:15:11 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395486
525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar
ks_acq.2395486525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1324642030
Short name T934
Test name
Test status
Simulation time 121337864 ps
CPU time 1.75 seconds
Started Aug 27 07:15:07 AM UTC 24
Finished Aug 27 07:15:10 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324642
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.1324642030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_hrst.1962363498
Short name T927
Test name
Test status
Simulation time 340217258 ps
CPU time 2.07 seconds
Started Aug 27 07:15:01 AM UTC 24
Finished Aug 27 07:15:04 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962363
498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.1962363498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.527630547
Short name T923
Test name
Test status
Simulation time 799005941 ps
CPU time 6.44 seconds
Started Aug 27 07:14:51 AM UTC 24
Finished Aug 27 07:14:59 AM UTC 24
Peak memory 230972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527630
547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.527630547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.984975252
Short name T947
Test name
Test status
Simulation time 12514914881 ps
CPU time 24.57 seconds
Started Aug 27 07:14:51 AM UTC 24
Finished Aug 27 07:15:17 AM UTC 24
Peak memory 729240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=984975252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stress
_wr.984975252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.1716035446
Short name T943
Test name
Test status
Simulation time 2495409538 ps
CPU time 4.71 seconds
Started Aug 27 07:15:09 AM UTC 24
Finished Aug 27 07:15:15 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716035
446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.1716035446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.3434362017
Short name T942
Test name
Test status
Simulation time 1869170190 ps
CPU time 3.89 seconds
Started Aug 27 07:15:09 AM UTC 24
Finished Aug 27 07:15:14 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434362
017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad
dr.3434362017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_perf.721901945
Short name T929
Test name
Test status
Simulation time 1014473115 ps
CPU time 4.92 seconds
Started Aug 27 07:14:59 AM UTC 24
Finished Aug 27 07:15:05 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7219019
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.721901945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.2668626477
Short name T939
Test name
Test status
Simulation time 469684362 ps
CPU time 4.42 seconds
Started Aug 27 07:15:07 AM UTC 24
Finished Aug 27 07:15:13 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668626
477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.2668626477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.3568535100
Short name T932
Test name
Test status
Simulation time 1217822172 ps
CPU time 24.11 seconds
Started Aug 27 07:14:41 AM UTC 24
Finished Aug 27 07:15:06 AM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568535100 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.3568535100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.569971375
Short name T1728
Test name
Test status
Simulation time 71281940253 ps
CPU time 1137.01 seconds
Started Aug 27 07:15:01 AM UTC 24
Finished Aug 27 07:34:08 AM UTC 24
Peak memory 8544668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569971
375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.569971375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.890040555
Short name T924
Test name
Test status
Simulation time 462595319 ps
CPU time 10.32 seconds
Started Aug 27 07:14:48 AM UTC 24
Finished Aug 27 07:14:59 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890040555 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.890040555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.354258830
Short name T921
Test name
Test status
Simulation time 16790492386 ps
CPU time 11.8 seconds
Started Aug 27 07:14:41 AM UTC 24
Finished Aug 27 07:14:54 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354258830 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.354258830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.1313288452
Short name T922
Test name
Test status
Simulation time 615707278 ps
CPU time 4.43 seconds
Started Aug 27 07:14:50 AM UTC 24
Finished Aug 27 07:14:55 AM UTC 24
Peak memory 262236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313288452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.1313288452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.693335384
Short name T931
Test name
Test status
Simulation time 1390331281 ps
CPU time 11.55 seconds
Started Aug 27 07:14:53 AM UTC 24
Finished Aug 27 07:15:06 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6933353
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.693335384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.1356200492
Short name T933
Test name
Test status
Simulation time 36797797 ps
CPU time 1.48 seconds
Started Aug 27 07:15:07 AM UTC 24
Finished Aug 27 07:15:10 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356200
492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.1356200492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_alert_test.3633491612
Short name T973
Test name
Test status
Simulation time 17583652 ps
CPU time 0.86 seconds
Started Aug 27 07:15:41 AM UTC 24
Finished Aug 27 07:15:43 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633491612 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3633491612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.3685375493
Short name T950
Test name
Test status
Simulation time 62791410 ps
CPU time 2.14 seconds
Started Aug 27 07:15:18 AM UTC 24
Finished Aug 27 07:15:21 AM UTC 24
Peak memory 226720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685375493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3685375493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2059129420
Short name T962
Test name
Test status
Simulation time 4106722839 ps
CPU time 20.17 seconds
Started Aug 27 07:15:14 AM UTC 24
Finished Aug 27 07:15:35 AM UTC 24
Peak memory 270748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059129420 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.2059129420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.1741427353
Short name T1036
Test name
Test status
Simulation time 14331826696 ps
CPU time 95.01 seconds
Started Aug 27 07:15:15 AM UTC 24
Finished Aug 27 07:16:52 AM UTC 24
Peak memory 532688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741427353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1741427353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.23354954
Short name T1009
Test name
Test status
Simulation time 2552868135 ps
CPU time 66.52 seconds
Started Aug 27 07:15:13 AM UTC 24
Finished Aug 27 07:16:21 AM UTC 24
Peak memory 811220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23354954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.23354954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.2780212603
Short name T946
Test name
Test status
Simulation time 387657425 ps
CPU time 1.8 seconds
Started Aug 27 07:15:14 AM UTC 24
Finished Aug 27 07:15:17 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780212603 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.2780212603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.2482589080
Short name T953
Test name
Test status
Simulation time 115799760 ps
CPU time 7.61 seconds
Started Aug 27 07:15:14 AM UTC 24
Finished Aug 27 07:15:23 AM UTC 24
Peak memory 235716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482589080 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.2482589080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.351932514
Short name T1012
Test name
Test status
Simulation time 7999593305 ps
CPU time 68.34 seconds
Started Aug 27 07:15:13 AM UTC 24
Finished Aug 27 07:16:23 AM UTC 24
Peak memory 876680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351932514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.351932514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.4104621878
Short name T266
Test name
Test status
Simulation time 1348266609 ps
CPU time 30.91 seconds
Started Aug 27 07:15:34 AM UTC 24
Finished Aug 27 07:16:07 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104621878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.4104621878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_override.588714578
Short name T156
Test name
Test status
Simulation time 29427266 ps
CPU time 1.08 seconds
Started Aug 27 07:15:12 AM UTC 24
Finished Aug 27 07:15:14 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588714578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.588714578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_perf.59635820
Short name T954
Test name
Test status
Simulation time 319272877 ps
CPU time 7.18 seconds
Started Aug 27 07:15:15 AM UTC 24
Finished Aug 27 07:15:23 AM UTC 24
Peak memory 244048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59635820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.59635820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.1550118972
Short name T952
Test name
Test status
Simulation time 197274884 ps
CPU time 4.99 seconds
Started Aug 27 07:15:16 AM UTC 24
Finished Aug 27 07:15:22 AM UTC 24
Peak memory 233692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550118972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.1550118972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.3436316579
Short name T1013
Test name
Test status
Simulation time 1546558676 ps
CPU time 72.5 seconds
Started Aug 27 07:15:11 AM UTC 24
Finished Aug 27 07:16:25 AM UTC 24
Peak memory 344144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436316579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3436316579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.772558925
Short name T941
Test name
Test status
Simulation time 3529782493 ps
CPU time 12.42 seconds
Started Aug 27 07:15:16 AM UTC 24
Finished Aug 27 07:15:30 AM UTC 24
Peak memory 229056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772558925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.772558925
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.2943454063
Short name T969
Test name
Test status
Simulation time 11165441859 ps
CPU time 8.81 seconds
Started Aug 27 07:15:32 AM UTC 24
Finished Aug 27 07:15:42 AM UTC 24
Peak memory 233712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2943454063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad
dr.2943454063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.2570544383
Short name T959
Test name
Test status
Simulation time 167761827 ps
CPU time 1.52 seconds
Started Aug 27 07:15:27 AM UTC 24
Finished Aug 27 07:15:30 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570544
383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.2570544383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.383000935
Short name T960
Test name
Test status
Simulation time 1157974539 ps
CPU time 1.27 seconds
Started Aug 27 07:15:32 AM UTC 24
Finished Aug 27 07:15:34 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830009
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.383000935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1281527156
Short name T972
Test name
Test status
Simulation time 998980460 ps
CPU time 4.86 seconds
Started Aug 27 07:15:36 AM UTC 24
Finished Aug 27 07:15:42 AM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281527
156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.1281527156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.1214343926
Short name T965
Test name
Test status
Simulation time 666875853 ps
CPU time 2.37 seconds
Started Aug 27 07:15:36 AM UTC 24
Finished Aug 27 07:15:40 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214343
926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermark
s_tx.1214343926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.3494701814
Short name T945
Test name
Test status
Simulation time 640166097 ps
CPU time 7.08 seconds
Started Aug 27 07:15:24 AM UTC 24
Finished Aug 27 07:15:32 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349470
1814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.3494701814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.3542906534
Short name T1198
Test name
Test status
Simulation time 21061789445 ps
CPU time 338.69 seconds
Started Aug 27 07:15:24 AM UTC 24
Finished Aug 27 07:21:07 AM UTC 24
Peak memory 5198040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3542906534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres
s_wr.3542906534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.2621364244
Short name T975
Test name
Test status
Simulation time 459499936 ps
CPU time 4.4 seconds
Started Aug 27 07:15:39 AM UTC 24
Finished Aug 27 07:15:44 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621364
244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.2621364244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.1286324234
Short name T974
Test name
Test status
Simulation time 134092274 ps
CPU time 2.13 seconds
Started Aug 27 07:15:41 AM UTC 24
Finished Aug 27 07:15:44 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286324
234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_txstretch.1286324234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_perf.1185834327
Short name T967
Test name
Test status
Simulation time 2598452888 ps
CPU time 7.54 seconds
Started Aug 27 07:15:32 AM UTC 24
Finished Aug 27 07:15:41 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185834
327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.1185834327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.2087812614
Short name T970
Test name
Test status
Simulation time 1765640694 ps
CPU time 2.64 seconds
Started Aug 27 07:15:39 AM UTC 24
Finished Aug 27 07:15:42 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087812
614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.2087812614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.786888005
Short name T893
Test name
Test status
Simulation time 2735693109 ps
CPU time 10.45 seconds
Started Aug 27 07:15:20 AM UTC 24
Finished Aug 27 07:15:31 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786888005 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.786888005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.3700923325
Short name T993
Test name
Test status
Simulation time 42832781325 ps
CPU time 37.92 seconds
Started Aug 27 07:15:32 AM UTC 24
Finished Aug 27 07:16:11 AM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370092
3325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.3700923325
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.3931588055
Short name T978
Test name
Test status
Simulation time 6129928311 ps
CPU time 23.74 seconds
Started Aug 27 07:15:22 AM UTC 24
Finished Aug 27 07:15:47 AM UTC 24
Peak memory 250268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931588055 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.3931588055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.3050856588
Short name T966
Test name
Test status
Simulation time 12549508385 ps
CPU time 17.2 seconds
Started Aug 27 07:15:22 AM UTC 24
Finished Aug 27 07:15:40 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050856588 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.3050856588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.3247270416
Short name T958
Test name
Test status
Simulation time 2054477692 ps
CPU time 5.38 seconds
Started Aug 27 07:15:23 AM UTC 24
Finished Aug 27 07:15:29 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247270416 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.3247270416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.3935589045
Short name T948
Test name
Test status
Simulation time 2642970624 ps
CPU time 7.34 seconds
Started Aug 27 07:15:25 AM UTC 24
Finished Aug 27 07:15:34 AM UTC 24
Peak memory 233740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935589
045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.3935589045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.3848437437
Short name T968
Test name
Test status
Simulation time 129342198 ps
CPU time 4.09 seconds
Started Aug 27 07:15:37 AM UTC 24
Finished Aug 27 07:15:42 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848437
437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3848437437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_alert_test.1734012094
Short name T1004
Test name
Test status
Simulation time 23068550 ps
CPU time 0.94 seconds
Started Aug 27 07:16:16 AM UTC 24
Finished Aug 27 07:16:18 AM UTC 24
Peak memory 215392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734012094 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1734012094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.2735792430
Short name T982
Test name
Test status
Simulation time 89188351 ps
CPU time 3.5 seconds
Started Aug 27 07:15:48 AM UTC 24
Finished Aug 27 07:15:52 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735792430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2735792430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.1238239194
Short name T983
Test name
Test status
Simulation time 369484504 ps
CPU time 10.82 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:15:55 AM UTC 24
Peak memory 295072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238239194 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.1238239194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.2055783310
Short name T1033
Test name
Test status
Simulation time 14171264148 ps
CPU time 208.63 seconds
Started Aug 27 07:15:46 AM UTC 24
Finished Aug 27 07:19:17 AM UTC 24
Peak memory 680136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055783310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2055783310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.701926421
Short name T1077
Test name
Test status
Simulation time 8630457853 ps
CPU time 135.37 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:18:01 AM UTC 24
Peak memory 678040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701926421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.701926421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.3539038606
Short name T977
Test name
Test status
Simulation time 432891998 ps
CPU time 1.57 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:15:46 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539038606 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.3539038606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.3933628880
Short name T984
Test name
Test status
Simulation time 771528373 ps
CPU time 12.93 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:15:57 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933628880 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.3933628880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.1582578704
Short name T1053
Test name
Test status
Simulation time 5685503524 ps
CPU time 89.75 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:17:15 AM UTC 24
Peak memory 1278100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582578704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1582578704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.2745990694
Short name T1011
Test name
Test status
Simulation time 683450237 ps
CPU time 9.9 seconds
Started Aug 27 07:16:11 AM UTC 24
Finished Aug 27 07:16:22 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745990694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2745990694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_override.3198875410
Short name T976
Test name
Test status
Simulation time 16090620 ps
CPU time 0.94 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:15:45 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198875410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.3198875410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_perf.2898547174
Short name T1119
Test name
Test status
Simulation time 27500181428 ps
CPU time 221.82 seconds
Started Aug 27 07:15:46 AM UTC 24
Finished Aug 27 07:19:31 AM UTC 24
Peak memory 260512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898547174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2898547174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.1456694306
Short name T980
Test name
Test status
Simulation time 116269521 ps
CPU time 2.82 seconds
Started Aug 27 07:15:46 AM UTC 24
Finished Aug 27 07:15:49 AM UTC 24
Peak memory 233444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456694306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1456694306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2600441589
Short name T1021
Test name
Test status
Simulation time 5909880005 ps
CPU time 52.18 seconds
Started Aug 27 07:15:43 AM UTC 24
Finished Aug 27 07:16:37 AM UTC 24
Peak memory 340120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600441589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2600441589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.2724847810
Short name T987
Test name
Test status
Simulation time 1553650570 ps
CPU time 13.01 seconds
Started Aug 27 07:15:46 AM UTC 24
Finished Aug 27 07:16:00 AM UTC 24
Peak memory 233896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724847810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2724847810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.1106504170
Short name T998
Test name
Test status
Simulation time 3815398842 ps
CPU time 8.72 seconds
Started Aug 27 07:16:05 AM UTC 24
Finished Aug 27 07:16:15 AM UTC 24
Peak memory 231052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1106504170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_ad
dr.1106504170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.247919738
Short name T988
Test name
Test status
Simulation time 116629549 ps
CPU time 1.63 seconds
Started Aug 27 07:16:01 AM UTC 24
Finished Aug 27 07:16:03 AM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479197
38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.247919738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.2022953946
Short name T989
Test name
Test status
Simulation time 219263832 ps
CPU time 2.16 seconds
Started Aug 27 07:16:01 AM UTC 24
Finished Aug 27 07:16:04 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022953
946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.2022953946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.1072521448
Short name T1000
Test name
Test status
Simulation time 1310811610 ps
CPU time 3.06 seconds
Started Aug 27 07:16:12 AM UTC 24
Finished Aug 27 07:16:16 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072521
448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar
ks_acq.1072521448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.2787902897
Short name T999
Test name
Test status
Simulation time 89654012 ps
CPU time 1.61 seconds
Started Aug 27 07:16:12 AM UTC 24
Finished Aug 27 07:16:15 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787902
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermark
s_tx.2787902897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.3636186196
Short name T995
Test name
Test status
Simulation time 1435727453 ps
CPU time 3.81 seconds
Started Aug 27 07:16:07 AM UTC 24
Finished Aug 27 07:16:12 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636186
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.3636186196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.3908867062
Short name T990
Test name
Test status
Simulation time 15664751278 ps
CPU time 11.84 seconds
Started Aug 27 07:15:54 AM UTC 24
Finished Aug 27 07:16:07 AM UTC 24
Peak memory 230980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390886
7062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.3908867062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.3996997752
Short name T986
Test name
Test status
Simulation time 661126421 ps
CPU time 2.34 seconds
Started Aug 27 07:15:56 AM UTC 24
Finished Aug 27 07:16:00 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3996997752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres
s_wr.3996997752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.1502567403
Short name T1007
Test name
Test status
Simulation time 1084813693 ps
CPU time 4.21 seconds
Started Aug 27 07:16:15 AM UTC 24
Finished Aug 27 07:16:20 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502567
403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.1502567403
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1038676091
Short name T1006
Test name
Test status
Simulation time 3985242057 ps
CPU time 4.09 seconds
Started Aug 27 07:16:15 AM UTC 24
Finished Aug 27 07:16:20 AM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038676
091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad
dr.1038676091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.1327044944
Short name T1002
Test name
Test status
Simulation time 786954698 ps
CPU time 1.69 seconds
Started Aug 27 07:16:15 AM UTC 24
Finished Aug 27 07:16:17 AM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327044
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.1327044944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_perf.3728513745
Short name T996
Test name
Test status
Simulation time 927620115 ps
CPU time 9.7 seconds
Started Aug 27 07:16:03 AM UTC 24
Finished Aug 27 07:16:14 AM UTC 24
Peak memory 233664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728513
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.3728513745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.2848996824
Short name T1003
Test name
Test status
Simulation time 426519026 ps
CPU time 4.05 seconds
Started Aug 27 07:16:13 AM UTC 24
Finished Aug 27 07:16:18 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848996
824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.2848996824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.4030388377
Short name T93
Test name
Test status
Simulation time 2398136698 ps
CPU time 21.98 seconds
Started Aug 27 07:15:51 AM UTC 24
Finished Aug 27 07:16:14 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030388377 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.4030388377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3586896670
Short name T1333
Test name
Test status
Simulation time 66428846697 ps
CPU time 461.09 seconds
Started Aug 27 07:16:04 AM UTC 24
Finished Aug 27 07:23:50 AM UTC 24
Peak memory 4057240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358689
6670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.3586896670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.1187236151
Short name T985
Test name
Test status
Simulation time 987494869 ps
CPU time 6.85 seconds
Started Aug 27 07:15:51 AM UTC 24
Finished Aug 27 07:15:59 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187236151 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.1187236151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.1967478673
Short name T1748
Test name
Test status
Simulation time 61376401488 ps
CPU time 1440.52 seconds
Started Aug 27 07:15:51 AM UTC 24
Finished Aug 27 07:40:05 AM UTC 24
Peak memory 10494176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967478673 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.1967478673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.792555750
Short name T994
Test name
Test status
Simulation time 6906260312 ps
CPU time 11.95 seconds
Started Aug 27 07:15:58 AM UTC 24
Finished Aug 27 07:16:12 AM UTC 24
Peak memory 233460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7925557
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.792555750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.2888842105
Short name T1010
Test name
Test status
Simulation time 430697436 ps
CPU time 8.58 seconds
Started Aug 27 07:16:12 AM UTC 24
Finished Aug 27 07:16:22 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888842
105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.2888842105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_alert_test.1605445959
Short name T992
Test name
Test status
Simulation time 33889414 ps
CPU time 0.94 seconds
Started Aug 27 07:16:49 AM UTC 24
Finished Aug 27 07:16:51 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605445959 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1605445959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.2031855012
Short name T1014
Test name
Test status
Simulation time 269444835 ps
CPU time 4.72 seconds
Started Aug 27 07:16:22 AM UTC 24
Finished Aug 27 07:16:28 AM UTC 24
Peak memory 227088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031855012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2031855012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.2186513832
Short name T1017
Test name
Test status
Simulation time 1251717023 ps
CPU time 11.75 seconds
Started Aug 27 07:16:18 AM UTC 24
Finished Aug 27 07:16:31 AM UTC 24
Peak memory 342140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186513832 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.2186513832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.4171327512
Short name T1052
Test name
Test status
Simulation time 9546548149 ps
CPU time 162.41 seconds
Started Aug 27 07:16:20 AM UTC 24
Finished Aug 27 07:19:06 AM UTC 24
Peak memory 539020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171327512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.4171327512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.2862502054
Short name T1107
Test name
Test status
Simulation time 13827185904 ps
CPU time 145.79 seconds
Started Aug 27 07:16:18 AM UTC 24
Finished Aug 27 07:18:46 AM UTC 24
Peak memory 852180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862502054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2862502054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.2210870587
Short name T1008
Test name
Test status
Simulation time 210914547 ps
CPU time 1.61 seconds
Started Aug 27 07:16:18 AM UTC 24
Finished Aug 27 07:16:21 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210870587 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.2210870587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.2905706964
Short name T1016
Test name
Test status
Simulation time 655376760 ps
CPU time 11.37 seconds
Started Aug 27 07:16:18 AM UTC 24
Finished Aug 27 07:16:31 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905706964 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.2905706964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.2455763244
Short name T1114
Test name
Test status
Simulation time 3372261633 ps
CPU time 187.68 seconds
Started Aug 27 07:16:17 AM UTC 24
Finished Aug 27 07:19:28 AM UTC 24
Peak memory 1036704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455763244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2455763244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.3932621257
Short name T963
Test name
Test status
Simulation time 2127218516 ps
CPU time 8.59 seconds
Started Aug 27 07:16:40 AM UTC 24
Finished Aug 27 07:16:50 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932621257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3932621257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_override.1641624076
Short name T1005
Test name
Test status
Simulation time 18621485 ps
CPU time 1.06 seconds
Started Aug 27 07:16:17 AM UTC 24
Finished Aug 27 07:16:19 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641624076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1641624076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_perf.542687457
Short name T1019
Test name
Test status
Simulation time 3134430247 ps
CPU time 12.12 seconds
Started Aug 27 07:16:21 AM UTC 24
Finished Aug 27 07:16:34 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542687457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.542687457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.2809562297
Short name T1015
Test name
Test status
Simulation time 2510512441 ps
CPU time 8.16 seconds
Started Aug 27 07:16:21 AM UTC 24
Finished Aug 27 07:16:30 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809562297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2809562297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.4175522632
Short name T1032
Test name
Test status
Simulation time 6917735156 ps
CPU time 31.86 seconds
Started Aug 27 07:16:16 AM UTC 24
Finished Aug 27 07:16:49 AM UTC 24
Peak memory 350432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175522632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.4175522632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.674072139
Short name T1018
Test name
Test status
Simulation time 1547292075 ps
CPU time 9.86 seconds
Started Aug 27 07:16:22 AM UTC 24
Finished Aug 27 07:16:33 AM UTC 24
Peak memory 233368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674072139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.674072139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.280805278
Short name T1026
Test name
Test status
Simulation time 782024229 ps
CPU time 6.33 seconds
Started Aug 27 07:16:38 AM UTC 24
Finished Aug 27 07:16:46 AM UTC 24
Peak memory 233864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=280805278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.280805278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.3944606270
Short name T309
Test name
Test status
Simulation time 649586574 ps
CPU time 2.65 seconds
Started Aug 27 07:16:34 AM UTC 24
Finished Aug 27 07:16:37 AM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944606
270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.3944606270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.3430522632
Short name T1022
Test name
Test status
Simulation time 304719727 ps
CPU time 1.83 seconds
Started Aug 27 07:16:35 AM UTC 24
Finished Aug 27 07:16:38 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430522
632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.3430522632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.1791431153
Short name T1029
Test name
Test status
Simulation time 1586349849 ps
CPU time 3.55 seconds
Started Aug 27 07:16:43 AM UTC 24
Finished Aug 27 07:16:48 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791431
153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar
ks_acq.1791431153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.1242861722
Short name T1028
Test name
Test status
Simulation time 116938986 ps
CPU time 1.84 seconds
Started Aug 27 07:16:44 AM UTC 24
Finished Aug 27 07:16:47 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242861
722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_tx.1242861722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.416069028
Short name T1023
Test name
Test status
Simulation time 1278794744 ps
CPU time 9.96 seconds
Started Aug 27 07:16:28 AM UTC 24
Finished Aug 27 07:16:39 AM UTC 24
Peak memory 230904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416069
028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.416069028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.452329542
Short name T1034
Test name
Test status
Simulation time 8623620740 ps
CPU time 18.26 seconds
Started Aug 27 07:16:31 AM UTC 24
Finished Aug 27 07:16:51 AM UTC 24
Peak memory 545244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=452329542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stress
_wr.452329542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.2002785322
Short name T1040
Test name
Test status
Simulation time 528792463 ps
CPU time 5.36 seconds
Started Aug 27 07:16:47 AM UTC 24
Finished Aug 27 07:16:53 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002785
322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.2002785322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.2939322045
Short name T1039
Test name
Test status
Simulation time 507227442 ps
CPU time 4.3 seconds
Started Aug 27 07:16:48 AM UTC 24
Finished Aug 27 07:16:53 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939322
045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_ad
dr.2939322045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_perf.1418042900
Short name T1027
Test name
Test status
Simulation time 1615732023 ps
CPU time 8.68 seconds
Started Aug 27 07:16:36 AM UTC 24
Finished Aug 27 07:16:46 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418042
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.1418042900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.3476824944
Short name T1035
Test name
Test status
Simulation time 514193685 ps
CPU time 4.21 seconds
Started Aug 27 07:16:47 AM UTC 24
Finished Aug 27 07:16:52 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476824
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.3476824944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.1753241600
Short name T94
Test name
Test status
Simulation time 1299491108 ps
CPU time 41.87 seconds
Started Aug 27 07:16:23 AM UTC 24
Finished Aug 27 07:17:06 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753241600 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.1753241600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.2358832816
Short name T1043
Test name
Test status
Simulation time 6408133400 ps
CPU time 22.01 seconds
Started Aug 27 07:16:37 AM UTC 24
Finished Aug 27 07:17:01 AM UTC 24
Peak memory 244188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235883
2816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.2358832816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.2437631062
Short name T1041
Test name
Test status
Simulation time 652324895 ps
CPU time 26.65 seconds
Started Aug 27 07:16:26 AM UTC 24
Finished Aug 27 07:16:54 AM UTC 24
Peak memory 216756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437631062 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.2437631062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.451065855
Short name T1054
Test name
Test status
Simulation time 17567414881 ps
CPU time 50.82 seconds
Started Aug 27 07:16:24 AM UTC 24
Finished Aug 27 07:17:16 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451065855 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.451065855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.4200352202
Short name T1020
Test name
Test status
Simulation time 1572634093 ps
CPU time 8.44 seconds
Started Aug 27 07:16:26 AM UTC 24
Finished Aug 27 07:16:36 AM UTC 24
Peak memory 289056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200352202 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.4200352202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.929118450
Short name T1024
Test name
Test status
Simulation time 5178193347 ps
CPU time 10.65 seconds
Started Aug 27 07:16:31 AM UTC 24
Finished Aug 27 07:16:44 AM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9291184
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.929118450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.3720665590
Short name T1030
Test name
Test status
Simulation time 65600080 ps
CPU time 2.59 seconds
Started Aug 27 07:16:44 AM UTC 24
Finished Aug 27 07:16:48 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720665
590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.3720665590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_alert_test.1728763601
Short name T1065
Test name
Test status
Simulation time 24141935 ps
CPU time 0.97 seconds
Started Aug 27 07:17:30 AM UTC 24
Finished Aug 27 07:17:32 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728763601 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1728763601
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.3460952653
Short name T1045
Test name
Test status
Simulation time 199504213 ps
CPU time 4.69 seconds
Started Aug 27 07:16:55 AM UTC 24
Finished Aug 27 07:17:01 AM UTC 24
Peak memory 237788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460952653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3460952653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.50919776
Short name T1044
Test name
Test status
Simulation time 512233041 ps
CPU time 6.19 seconds
Started Aug 27 07:16:53 AM UTC 24
Finished Aug 27 07:17:01 AM UTC 24
Peak memory 270360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50919776 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.50919776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.3599671860
Short name T1071
Test name
Test status
Simulation time 1778513575 ps
CPU time 44.16 seconds
Started Aug 27 07:16:54 AM UTC 24
Finished Aug 27 07:17:39 AM UTC 24
Peak memory 295316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599671860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3599671860
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.857097882
Short name T1076
Test name
Test status
Simulation time 10540154459 ps
CPU time 65.99 seconds
Started Aug 27 07:16:52 AM UTC 24
Finished Aug 27 07:18:00 AM UTC 24
Peak memory 862412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857097882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.857097882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.381726725
Short name T1042
Test name
Test status
Simulation time 385833036 ps
CPU time 1.44 seconds
Started Aug 27 07:16:52 AM UTC 24
Finished Aug 27 07:16:55 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381726725 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.381726725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3036342024
Short name T1046
Test name
Test status
Simulation time 712501400 ps
CPU time 6.33 seconds
Started Aug 27 07:16:53 AM UTC 24
Finished Aug 27 07:17:01 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036342024 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3036342024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.1083246179
Short name T1193
Test name
Test status
Simulation time 9151727566 ps
CPU time 245.65 seconds
Started Aug 27 07:16:51 AM UTC 24
Finished Aug 27 07:21:00 AM UTC 24
Peak memory 1317016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083246179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1083246179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.1889965207
Short name T274
Test name
Test status
Simulation time 3006337675 ps
CPU time 8.87 seconds
Started Aug 27 07:17:20 AM UTC 24
Finished Aug 27 07:17:30 AM UTC 24
Peak memory 216752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889965207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1889965207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_override.1042123821
Short name T1037
Test name
Test status
Simulation time 82365369 ps
CPU time 1.04 seconds
Started Aug 27 07:16:50 AM UTC 24
Finished Aug 27 07:16:52 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042123821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1042123821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_perf.894623611
Short name T45
Test name
Test status
Simulation time 6774814069 ps
CPU time 286.74 seconds
Started Aug 27 07:16:54 AM UTC 24
Finished Aug 27 07:21:44 AM UTC 24
Peak memory 360904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894623611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.894623611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.323088327
Short name T1337
Test name
Test status
Simulation time 24469573102 ps
CPU time 413.73 seconds
Started Aug 27 07:16:54 AM UTC 24
Finished Aug 27 07:23:52 AM UTC 24
Peak memory 798924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323088327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.323088327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.3118022935
Short name T1080
Test name
Test status
Simulation time 1565981317 ps
CPU time 78.9 seconds
Started Aug 27 07:16:49 AM UTC 24
Finished Aug 27 07:18:10 AM UTC 24
Peak memory 376996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118022935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3118022935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.1393182132
Short name T1047
Test name
Test status
Simulation time 1967709874 ps
CPU time 8.3 seconds
Started Aug 27 07:16:55 AM UTC 24
Finished Aug 27 07:17:04 AM UTC 24
Peak memory 226776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393182132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1393182132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.2044558360
Short name T1055
Test name
Test status
Simulation time 299190305 ps
CPU time 1.98 seconds
Started Aug 27 07:17:16 AM UTC 24
Finished Aug 27 07:17:19 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044558
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.2044558360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.4192049536
Short name T1056
Test name
Test status
Simulation time 373320852 ps
CPU time 2.71 seconds
Started Aug 27 07:17:16 AM UTC 24
Finished Aug 27 07:17:20 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192049
536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.4192049536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.768781519
Short name T1062
Test name
Test status
Simulation time 595287029 ps
CPU time 5.15 seconds
Started Aug 27 07:17:22 AM UTC 24
Finished Aug 27 07:17:29 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7687815
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_acq.768781519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.2746788373
Short name T1061
Test name
Test status
Simulation time 930069990 ps
CPU time 2.54 seconds
Started Aug 27 07:17:25 AM UTC 24
Finished Aug 27 07:17:28 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746788
373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_tx.2746788373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.2728914862
Short name T1051
Test name
Test status
Simulation time 1388147376 ps
CPU time 8.03 seconds
Started Aug 27 07:17:05 AM UTC 24
Finished Aug 27 07:17:14 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272891
4862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.2728914862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.407403643
Short name T1184
Test name
Test status
Simulation time 15398846901 ps
CPU time 225.3 seconds
Started Aug 27 07:17:07 AM UTC 24
Finished Aug 27 07:20:56 AM UTC 24
Peak memory 3891356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=407403643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.407403643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.1125698422
Short name T1067
Test name
Test status
Simulation time 4356485841 ps
CPU time 3.65 seconds
Started Aug 27 07:17:29 AM UTC 24
Finished Aug 27 07:17:33 AM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125698
422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.1125698422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.4154068776
Short name T55
Test name
Test status
Simulation time 570983885 ps
CPU time 4.51 seconds
Started Aug 27 07:17:29 AM UTC 24
Finished Aug 27 07:17:34 AM UTC 24
Peak memory 216404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154068
776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad
dr.4154068776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_perf.3256686367
Short name T1058
Test name
Test status
Simulation time 1734787986 ps
CPU time 8.22 seconds
Started Aug 27 07:17:16 AM UTC 24
Finished Aug 27 07:17:25 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256686
367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.3256686367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.1589209083
Short name T1068
Test name
Test status
Simulation time 468339543 ps
CPU time 3.81 seconds
Started Aug 27 07:17:29 AM UTC 24
Finished Aug 27 07:17:34 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589209
083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.1589209083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2279041074
Short name T1050
Test name
Test status
Simulation time 3110555805 ps
CPU time 12.3 seconds
Started Aug 27 07:17:01 AM UTC 24
Finished Aug 27 07:17:14 AM UTC 24
Peak memory 233772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279041074 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.2279041074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.3340689665
Short name T226
Test name
Test status
Simulation time 92142542339 ps
CPU time 161.48 seconds
Started Aug 27 07:17:16 AM UTC 24
Finished Aug 27 07:20:00 AM UTC 24
Peak memory 1321240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334068
9665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.3340689665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.1412378625
Short name T1048
Test name
Test status
Simulation time 249281961 ps
CPU time 4.91 seconds
Started Aug 27 07:17:02 AM UTC 24
Finished Aug 27 07:17:08 AM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412378625 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.1412378625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.1872089541
Short name T1069
Test name
Test status
Simulation time 30408889434 ps
CPU time 30.54 seconds
Started Aug 27 07:17:02 AM UTC 24
Finished Aug 27 07:17:34 AM UTC 24
Peak memory 690396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872089541 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.1872089541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2787761674
Short name T1049
Test name
Test status
Simulation time 4072305974 ps
CPU time 7.37 seconds
Started Aug 27 07:17:02 AM UTC 24
Finished Aug 27 07:17:11 AM UTC 24
Peak memory 246224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787761674 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.2787761674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.3742935221
Short name T1057
Test name
Test status
Simulation time 4921809825 ps
CPU time 11.81 seconds
Started Aug 27 07:17:09 AM UTC 24
Finished Aug 27 07:17:21 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742935
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.3742935221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.1939219539
Short name T1063
Test name
Test status
Simulation time 102514807 ps
CPU time 2.19 seconds
Started Aug 27 07:17:26 AM UTC 24
Finished Aug 27 07:17:29 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939219
539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1939219539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_alert_test.3831040104
Short name T335
Test name
Test status
Simulation time 18900378 ps
CPU time 0.74 seconds
Started Aug 27 07:04:30 AM UTC 24
Finished Aug 27 07:04:32 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831040104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3831040104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.2106870597
Short name T31
Test name
Test status
Simulation time 3180606725 ps
CPU time 3.62 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:04:27 AM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106870597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2106870597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.863707597
Short name T332
Test name
Test status
Simulation time 1408801997 ps
CPU time 7 seconds
Started Aug 27 07:04:21 AM UTC 24
Finished Aug 27 07:04:29 AM UTC 24
Peak memory 290884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863707597 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.863707597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.2837487868
Short name T167
Test name
Test status
Simulation time 10325418144 ps
CPU time 52.18 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:05:16 AM UTC 24
Peak memory 291040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837487868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2837487868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.995191062
Short name T87
Test name
Test status
Simulation time 3652120465 ps
CPU time 38.48 seconds
Started Aug 27 07:04:21 AM UTC 24
Finished Aug 27 07:05:01 AM UTC 24
Peak memory 670024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995191062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.995191062
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.181743927
Short name T325
Test name
Test status
Simulation time 522491614 ps
CPU time 1.73 seconds
Started Aug 27 07:04:21 AM UTC 24
Finished Aug 27 07:04:24 AM UTC 24
Peak memory 215136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181743927 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.181743927
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.3248061467
Short name T86
Test name
Test status
Simulation time 529797683 ps
CPU time 8.52 seconds
Started Aug 27 07:04:21 AM UTC 24
Finished Aug 27 07:04:31 AM UTC 24
Peak memory 239896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248061467 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.3248061467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.295113766
Short name T89
Test name
Test status
Simulation time 3407199844 ps
CPU time 53.5 seconds
Started Aug 27 07:04:21 AM UTC 24
Finished Aug 27 07:05:16 AM UTC 24
Peak memory 942192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295113766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.295113766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.1587859052
Short name T268
Test name
Test status
Simulation time 1824915604 ps
CPU time 33.54 seconds
Started Aug 27 07:04:28 AM UTC 24
Finished Aug 27 07:05:03 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587859052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1587859052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_override.3767957536
Short name T150
Test name
Test status
Simulation time 47598467 ps
CPU time 0.97 seconds
Started Aug 27 07:04:20 AM UTC 24
Finished Aug 27 07:04:22 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767957536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3767957536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_perf.591835489
Short name T250
Test name
Test status
Simulation time 4605767564 ps
CPU time 74.27 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:05:39 AM UTC 24
Peak memory 915608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591835489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.591835489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.1005636762
Short name T248
Test name
Test status
Simulation time 1148637818 ps
CPU time 5.87 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:04:29 AM UTC 24
Peak memory 270404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005636762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.1005636762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.847643787
Short name T39
Test name
Test status
Simulation time 12333806452 ps
CPU time 61.59 seconds
Started Aug 27 07:04:20 AM UTC 24
Finished Aug 27 07:05:23 AM UTC 24
Peak memory 348584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847643787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.847643787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.231612045
Short name T223
Test name
Test status
Simulation time 12958167093 ps
CPU time 14.56 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:04:38 AM UTC 24
Peak memory 243856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231612045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.231612045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.914971880
Short name T206
Test name
Test status
Simulation time 67638650 ps
CPU time 1.42 seconds
Started Aug 27 07:04:30 AM UTC 24
Finished Aug 27 07:04:33 AM UTC 24
Peak memory 246612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914971880 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.914971880
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.809348655
Short name T337
Test name
Test status
Simulation time 914077125 ps
CPU time 6.97 seconds
Started Aug 27 07:04:25 AM UTC 24
Finished Aug 27 07:04:33 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=809348655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.809348655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.3043549404
Short name T330
Test name
Test status
Simulation time 357216459 ps
CPU time 2 seconds
Started Aug 27 07:04:24 AM UTC 24
Finished Aug 27 07:04:28 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043549
404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.3043549404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.1834204946
Short name T329
Test name
Test status
Simulation time 283540774 ps
CPU time 1.68 seconds
Started Aug 27 07:04:25 AM UTC 24
Finished Aug 27 07:04:28 AM UTC 24
Peak memory 218568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834204
946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.1834204946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.3787457200
Short name T334
Test name
Test status
Simulation time 354522680 ps
CPU time 2.45 seconds
Started Aug 27 07:04:28 AM UTC 24
Finished Aug 27 07:04:32 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787457
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.3787457200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.1636357816
Short name T185
Test name
Test status
Simulation time 263336644 ps
CPU time 1.75 seconds
Started Aug 27 07:04:28 AM UTC 24
Finished Aug 27 07:04:31 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636357
816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks
_tx.1636357816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.1725165308
Short name T201
Test name
Test status
Simulation time 248239582 ps
CPU time 3.1 seconds
Started Aug 27 07:04:25 AM UTC 24
Finished Aug 27 07:04:29 AM UTC 24
Peak memory 226792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725165
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.1725165308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.1174471586
Short name T224
Test name
Test status
Simulation time 4990464156 ps
CPU time 12.18 seconds
Started Aug 27 07:04:23 AM UTC 24
Finished Aug 27 07:04:37 AM UTC 24
Peak memory 233720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117447
1586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.1174471586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.1483075307
Short name T353
Test name
Test status
Simulation time 3003277676 ps
CPU time 22.77 seconds
Started Aug 27 07:04:23 AM UTC 24
Finished Aug 27 07:04:47 AM UTC 24
Peak memory 876696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1483075307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.1483075307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.354737692
Short name T163
Test name
Test status
Simulation time 559442276 ps
CPU time 3.17 seconds
Started Aug 27 07:04:30 AM UTC 24
Finished Aug 27 07:04:35 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547376
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.354737692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.3007881592
Short name T164
Test name
Test status
Simulation time 460981931 ps
CPU time 3.64 seconds
Started Aug 27 07:04:30 AM UTC 24
Finished Aug 27 07:04:35 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007881
592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.3007881592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.2349265852
Short name T186
Test name
Test status
Simulation time 739958738 ps
CPU time 1.89 seconds
Started Aug 27 07:04:30 AM UTC 24
Finished Aug 27 07:04:33 AM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349265
852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_txstretch.2349265852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_perf.4238429463
Short name T341
Test name
Test status
Simulation time 766377719 ps
CPU time 8.07 seconds
Started Aug 27 07:04:25 AM UTC 24
Finished Aug 27 07:04:34 AM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238429
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.4238429463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.3922120081
Short name T340
Test name
Test status
Simulation time 504348638 ps
CPU time 2.88 seconds
Started Aug 27 07:04:29 AM UTC 24
Finished Aug 27 07:04:34 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922120
081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.3922120081
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.1536230140
Short name T336
Test name
Test status
Simulation time 1401564858 ps
CPU time 9.15 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:04:33 AM UTC 24
Peak memory 226860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536230140 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.1536230140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.3378758757
Short name T252
Test name
Test status
Simulation time 8058310445 ps
CPU time 26.13 seconds
Started Aug 27 07:04:25 AM UTC 24
Finished Aug 27 07:04:52 AM UTC 24
Peak memory 266460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337875
8757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.3378758757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.798835363
Short name T278
Test name
Test status
Simulation time 1989276657 ps
CPU time 34.42 seconds
Started Aug 27 07:04:23 AM UTC 24
Finished Aug 27 07:04:59 AM UTC 24
Peak memory 243868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798835363 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.798835363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.1733659275
Short name T67
Test name
Test status
Simulation time 41599313327 ps
CPU time 181.58 seconds
Started Aug 27 07:04:22 AM UTC 24
Finished Aug 27 07:07:27 AM UTC 24
Peak memory 2894044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733659275 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.1733659275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.1655104229
Short name T333
Test name
Test status
Simulation time 2150267830 ps
CPU time 6.61 seconds
Started Aug 27 07:04:23 AM UTC 24
Finished Aug 27 07:04:31 AM UTC 24
Peak memory 336124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655104229 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.1655104229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.1518887359
Short name T339
Test name
Test status
Simulation time 1088291677 ps
CPU time 8.9 seconds
Started Aug 27 07:04:23 AM UTC 24
Finished Aug 27 07:04:33 AM UTC 24
Peak memory 243904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518887
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.1518887359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.1109820608
Short name T342
Test name
Test status
Simulation time 437872990 ps
CPU time 6.45 seconds
Started Aug 27 07:04:29 AM UTC 24
Finished Aug 27 07:04:37 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109820
608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1109820608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_alert_test.2780772339
Short name T1098
Test name
Test status
Simulation time 34633587 ps
CPU time 0.99 seconds
Started Aug 27 07:18:31 AM UTC 24
Finished Aug 27 07:18:33 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780772339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2780772339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.2127592045
Short name T1072
Test name
Test status
Simulation time 155559656 ps
CPU time 2.13 seconds
Started Aug 27 07:17:40 AM UTC 24
Finished Aug 27 07:17:43 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127592045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2127592045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.2747613109
Short name T1073
Test name
Test status
Simulation time 526985693 ps
CPU time 7.9 seconds
Started Aug 27 07:17:35 AM UTC 24
Finished Aug 27 07:17:43 AM UTC 24
Peak memory 276508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747613109 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.2747613109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.1894385668
Short name T1141
Test name
Test status
Simulation time 2461412456 ps
CPU time 139.2 seconds
Started Aug 27 07:17:35 AM UTC 24
Finished Aug 27 07:19:56 AM UTC 24
Peak memory 537104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894385668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1894385668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.3873417186
Short name T1139
Test name
Test status
Simulation time 2296380662 ps
CPU time 135.09 seconds
Started Aug 27 07:17:34 AM UTC 24
Finished Aug 27 07:19:52 AM UTC 24
Peak memory 757996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873417186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3873417186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.2030585391
Short name T1070
Test name
Test status
Simulation time 120762327 ps
CPU time 1.61 seconds
Started Aug 27 07:17:34 AM UTC 24
Finished Aug 27 07:17:37 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030585391 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.2030585391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1336392476
Short name T1074
Test name
Test status
Simulation time 508369586 ps
CPU time 9.96 seconds
Started Aug 27 07:17:35 AM UTC 24
Finished Aug 27 07:17:46 AM UTC 24
Peak memory 239840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336392476 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.1336392476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.3557055139
Short name T1169
Test name
Test status
Simulation time 3479943817 ps
CPU time 169.78 seconds
Started Aug 27 07:17:33 AM UTC 24
Finished Aug 27 07:20:26 AM UTC 24
Peak memory 874908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557055139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3557055139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.4008599319
Short name T1100
Test name
Test status
Simulation time 229943019 ps
CPU time 11.52 seconds
Started Aug 27 07:18:21 AM UTC 24
Finished Aug 27 07:18:34 AM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008599319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.4008599319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_override.2158021194
Short name T276
Test name
Test status
Simulation time 180521097 ps
CPU time 0.95 seconds
Started Aug 27 07:17:31 AM UTC 24
Finished Aug 27 07:17:33 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158021194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2158021194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_perf.4175647987
Short name T1331
Test name
Test status
Simulation time 27533440563 ps
CPU time 363.61 seconds
Started Aug 27 07:17:36 AM UTC 24
Finished Aug 27 07:23:44 AM UTC 24
Peak memory 250112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175647987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.4175647987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.2767032677
Short name T1110
Test name
Test status
Simulation time 2484426007 ps
CPU time 100.74 seconds
Started Aug 27 07:17:36 AM UTC 24
Finished Aug 27 07:19:18 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767032677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.2767032677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.1767421350
Short name T1122
Test name
Test status
Simulation time 9086968134 ps
CPU time 118.57 seconds
Started Aug 27 07:17:31 AM UTC 24
Finished Aug 27 07:19:32 AM UTC 24
Peak memory 442536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767421350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1767421350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.1092303978
Short name T1085
Test name
Test status
Simulation time 1402794739 ps
CPU time 39.19 seconds
Started Aug 27 07:17:38 AM UTC 24
Finished Aug 27 07:18:19 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092303978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1092303978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.254336224
Short name T1093
Test name
Test status
Simulation time 5082223455 ps
CPU time 9.57 seconds
Started Aug 27 07:18:19 AM UTC 24
Finished Aug 27 07:18:30 AM UTC 24
Peak memory 233196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=254336224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.254336224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.2624683559
Short name T1083
Test name
Test status
Simulation time 226112615 ps
CPU time 1.49 seconds
Started Aug 27 07:18:15 AM UTC 24
Finished Aug 27 07:18:17 AM UTC 24
Peak memory 230520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624683
559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.2624683559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.3029675897
Short name T1084
Test name
Test status
Simulation time 173214687 ps
CPU time 1.57 seconds
Started Aug 27 07:18:16 AM UTC 24
Finished Aug 27 07:18:18 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029675
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.3029675897
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.1401169875
Short name T1090
Test name
Test status
Simulation time 646381126 ps
CPU time 3.04 seconds
Started Aug 27 07:18:22 AM UTC 24
Finished Aug 27 07:18:26 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401169
875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermar
ks_acq.1401169875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.2454088720
Short name T1092
Test name
Test status
Simulation time 611546927 ps
CPU time 2.16 seconds
Started Aug 27 07:18:25 AM UTC 24
Finished Aug 27 07:18:28 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454088
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_tx.2454088720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.4280927111
Short name T1089
Test name
Test status
Simulation time 629158977 ps
CPU time 3.16 seconds
Started Aug 27 07:18:19 AM UTC 24
Finished Aug 27 07:18:23 AM UTC 24
Peak memory 227128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280927
111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.4280927111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.2124905756
Short name T1081
Test name
Test status
Simulation time 7557091380 ps
CPU time 12.08 seconds
Started Aug 27 07:18:01 AM UTC 24
Finished Aug 27 07:18:15 AM UTC 24
Peak memory 243944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212490
5756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.2124905756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.4261920418
Short name T1082
Test name
Test status
Simulation time 3578629805 ps
CPU time 9.45 seconds
Started Aug 27 07:18:07 AM UTC 24
Finished Aug 27 07:18:17 AM UTC 24
Peak memory 397460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4261920418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres
s_wr.4261920418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.3646733017
Short name T1097
Test name
Test status
Simulation time 423326473 ps
CPU time 4.22 seconds
Started Aug 27 07:18:28 AM UTC 24
Finished Aug 27 07:18:33 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646733
017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.3646733017
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.138146068
Short name T1102
Test name
Test status
Simulation time 450813175 ps
CPU time 4.31 seconds
Started Aug 27 07:18:29 AM UTC 24
Finished Aug 27 07:18:34 AM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381460
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_addr.138146068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_perf.1981396950
Short name T1094
Test name
Test status
Simulation time 7457532397 ps
CPU time 11.22 seconds
Started Aug 27 07:18:18 AM UTC 24
Finished Aug 27 07:18:30 AM UTC 24
Peak memory 243812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981396
950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.1981396950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1212617556
Short name T1095
Test name
Test status
Simulation time 1203920674 ps
CPU time 3.42 seconds
Started Aug 27 07:18:27 AM UTC 24
Finished Aug 27 07:18:31 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212617
556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.1212617556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.1981519934
Short name T1088
Test name
Test status
Simulation time 1211688572 ps
CPU time 35.46 seconds
Started Aug 27 07:17:44 AM UTC 24
Finished Aug 27 07:18:21 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981519934 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.1981519934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.102211277
Short name T1038
Test name
Test status
Simulation time 25143726985 ps
CPU time 41.67 seconds
Started Aug 27 07:18:18 AM UTC 24
Finished Aug 27 07:19:01 AM UTC 24
Peak memory 250140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102211
277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.102211277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.2132838525
Short name T1091
Test name
Test status
Simulation time 1693322429 ps
CPU time 35.56 seconds
Started Aug 27 07:17:50 AM UTC 24
Finished Aug 27 07:18:27 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132838525 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.2132838525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.3635334680
Short name T1079
Test name
Test status
Simulation time 15200985945 ps
CPU time 20.76 seconds
Started Aug 27 07:17:46 AM UTC 24
Finished Aug 27 07:18:08 AM UTC 24
Peak memory 217016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635334680 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.3635334680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.2550030970
Short name T1078
Test name
Test status
Simulation time 246841346 ps
CPU time 4.19 seconds
Started Aug 27 07:18:00 AM UTC 24
Finished Aug 27 07:18:06 AM UTC 24
Peak memory 218868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550030970 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.2550030970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.4071132138
Short name T1087
Test name
Test status
Simulation time 1392777366 ps
CPU time 11.08 seconds
Started Aug 27 07:18:09 AM UTC 24
Finished Aug 27 07:18:21 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071132
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.4071132138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.376701106
Short name T1096
Test name
Test status
Simulation time 152727479 ps
CPU time 5.11 seconds
Started Aug 27 07:18:26 AM UTC 24
Finished Aug 27 07:18:32 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767011
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.376701106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_alert_test.4212818579
Short name T1124
Test name
Test status
Simulation time 71411376 ps
CPU time 0.86 seconds
Started Aug 27 07:19:32 AM UTC 24
Finished Aug 27 07:19:34 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212818579 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.4212818579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.2450839514
Short name T1108
Test name
Test status
Simulation time 225832854 ps
CPU time 10.32 seconds
Started Aug 27 07:18:46 AM UTC 24
Finished Aug 27 07:18:58 AM UTC 24
Peak memory 237788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450839514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2450839514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3102627364
Short name T1106
Test name
Test status
Simulation time 599595356 ps
CPU time 9.33 seconds
Started Aug 27 07:18:36 AM UTC 24
Finished Aug 27 07:18:46 AM UTC 24
Peak memory 235616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102627364 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.3102627364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.3647496554
Short name T1212
Test name
Test status
Simulation time 12322781862 ps
CPU time 166.89 seconds
Started Aug 27 07:18:36 AM UTC 24
Finished Aug 27 07:21:25 AM UTC 24
Peak memory 477460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647496554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3647496554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.3469977822
Short name T1143
Test name
Test status
Simulation time 9597747431 ps
CPU time 82.44 seconds
Started Aug 27 07:18:34 AM UTC 24
Finished Aug 27 07:19:59 AM UTC 24
Peak memory 805392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469977822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3469977822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.404403884
Short name T1103
Test name
Test status
Simulation time 1126738757 ps
CPU time 1.69 seconds
Started Aug 27 07:18:36 AM UTC 24
Finished Aug 27 07:18:38 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404403884 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.404403884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.76120313
Short name T1104
Test name
Test status
Simulation time 167112012 ps
CPU time 4.81 seconds
Started Aug 27 07:18:36 AM UTC 24
Finished Aug 27 07:18:42 AM UTC 24
Peak memory 247952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76120313 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.76120313
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.3810330570
Short name T1205
Test name
Test status
Simulation time 2580352812 ps
CPU time 162.53 seconds
Started Aug 27 07:18:34 AM UTC 24
Finished Aug 27 07:21:20 AM UTC 24
Peak memory 772316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810330570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3810330570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.4146608163
Short name T1130
Test name
Test status
Simulation time 633105284 ps
CPU time 9.22 seconds
Started Aug 27 07:19:28 AM UTC 24
Finished Aug 27 07:19:38 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146608163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.4146608163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_override.3635742471
Short name T1101
Test name
Test status
Simulation time 17209507 ps
CPU time 1.06 seconds
Started Aug 27 07:18:32 AM UTC 24
Finished Aug 27 07:18:34 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635742471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3635742471
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_perf.912360539
Short name T1231
Test name
Test status
Simulation time 26842542757 ps
CPU time 182.16 seconds
Started Aug 27 07:18:39 AM UTC 24
Finished Aug 27 07:21:44 AM UTC 24
Peak memory 299336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912360539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.912360539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.3759544980
Short name T1105
Test name
Test status
Simulation time 545907684 ps
CPU time 2.2 seconds
Started Aug 27 07:18:42 AM UTC 24
Finished Aug 27 07:18:45 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759544980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3759544980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.1202238845
Short name T1099
Test name
Test status
Simulation time 3849494171 ps
CPU time 39.76 seconds
Started Aug 27 07:18:32 AM UTC 24
Finished Aug 27 07:19:13 AM UTC 24
Peak memory 381156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202238845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1202238845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.24539234
Short name T1059
Test name
Test status
Simulation time 5845562550 ps
CPU time 30.34 seconds
Started Aug 27 07:18:43 AM UTC 24
Finished Aug 27 07:19:15 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24539234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.24539234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.383478635
Short name T1120
Test name
Test status
Simulation time 4663711981 ps
CPU time 10.14 seconds
Started Aug 27 07:19:19 AM UTC 24
Finished Aug 27 07:19:31 AM UTC 24
Peak memory 233140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=383478635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.383478635
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.1438861231
Short name T1109
Test name
Test status
Simulation time 329946832 ps
CPU time 1.52 seconds
Started Aug 27 07:19:16 AM UTC 24
Finished Aug 27 07:19:18 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438861
231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.1438861231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.2322895356
Short name T1111
Test name
Test status
Simulation time 456045921 ps
CPU time 2.5 seconds
Started Aug 27 07:19:18 AM UTC 24
Finished Aug 27 07:19:22 AM UTC 24
Peak memory 220940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322895
356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.2322895356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.3133789793
Short name T1123
Test name
Test status
Simulation time 1217228770 ps
CPU time 2.27 seconds
Started Aug 27 07:19:29 AM UTC 24
Finished Aug 27 07:19:32 AM UTC 24
Peak memory 216344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133789
793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermar
ks_acq.3133789793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.623611746
Short name T1121
Test name
Test status
Simulation time 140534096 ps
CPU time 1.97 seconds
Started Aug 27 07:19:29 AM UTC 24
Finished Aug 27 07:19:32 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6236117
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermarks
_tx.623611746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.3135658340
Short name T1113
Test name
Test status
Simulation time 296942930 ps
CPU time 3.39 seconds
Started Aug 27 07:19:22 AM UTC 24
Finished Aug 27 07:19:27 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135658
340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.3135658340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.3793624391
Short name T997
Test name
Test status
Simulation time 1470560554 ps
CPU time 7.34 seconds
Started Aug 27 07:19:07 AM UTC 24
Finished Aug 27 07:19:15 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379362
4391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.3793624391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.1426752991
Short name T1162
Test name
Test status
Simulation time 12799519328 ps
CPU time 57.06 seconds
Started Aug 27 07:19:15 AM UTC 24
Finished Aug 27 07:20:13 AM UTC 24
Peak memory 1296604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1426752991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stres
s_wr.1426752991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.3690310359
Short name T1129
Test name
Test status
Simulation time 2345044587 ps
CPU time 5.26 seconds
Started Aug 27 07:19:31 AM UTC 24
Finished Aug 27 07:19:37 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690310
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.3690310359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.878622960
Short name T1128
Test name
Test status
Simulation time 2783644110 ps
CPU time 4.26 seconds
Started Aug 27 07:19:31 AM UTC 24
Finished Aug 27 07:19:36 AM UTC 24
Peak memory 216728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8786229
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.878622960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.3708034449
Short name T1126
Test name
Test status
Simulation time 129120806 ps
CPU time 2.36 seconds
Started Aug 27 07:19:31 AM UTC 24
Finished Aug 27 07:19:35 AM UTC 24
Peak memory 233280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708034
449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.3708034449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_perf.788771009
Short name T1115
Test name
Test status
Simulation time 1304851238 ps
CPU time 7.29 seconds
Started Aug 27 07:19:19 AM UTC 24
Finished Aug 27 07:19:28 AM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7887710
09 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.788771009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.1149704547
Short name T1125
Test name
Test status
Simulation time 3483072915 ps
CPU time 3.19 seconds
Started Aug 27 07:19:30 AM UTC 24
Finished Aug 27 07:19:34 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149704
547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.1149704547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.2643940792
Short name T1066
Test name
Test status
Simulation time 2759720072 ps
CPU time 13.44 seconds
Started Aug 27 07:18:47 AM UTC 24
Finished Aug 27 07:19:02 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643940792 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.2643940792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.435611028
Short name T1140
Test name
Test status
Simulation time 17216153881 ps
CPU time 32.85 seconds
Started Aug 27 07:19:19 AM UTC 24
Finished Aug 27 07:19:53 AM UTC 24
Peak memory 266520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435611
028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.435611028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.515170745
Short name T1117
Test name
Test status
Simulation time 4931170320 ps
CPU time 24.94 seconds
Started Aug 27 07:19:03 AM UTC 24
Finished Aug 27 07:19:29 AM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515170745 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.515170745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.2450370101
Short name T1137
Test name
Test status
Simulation time 24930462480 ps
CPU time 46.24 seconds
Started Aug 27 07:18:58 AM UTC 24
Finished Aug 27 07:19:46 AM UTC 24
Peak memory 757980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450370101 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.2450370101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.4039343100
Short name T1112
Test name
Test status
Simulation time 1116210739 ps
CPU time 10.55 seconds
Started Aug 27 07:19:15 AM UTC 24
Finished Aug 27 07:19:26 AM UTC 24
Peak memory 233160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039343
100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.4039343100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.2911251264
Short name T1132
Test name
Test status
Simulation time 603722959 ps
CPU time 13.75 seconds
Started Aug 27 07:19:29 AM UTC 24
Finished Aug 27 07:19:44 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911251
264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2911251264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_alert_test.3781939270
Short name T1159
Test name
Test status
Simulation time 28008180 ps
CPU time 0.9 seconds
Started Aug 27 07:20:10 AM UTC 24
Finished Aug 27 07:20:12 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781939270 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3781939270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.298096336
Short name T1138
Test name
Test status
Simulation time 647761094 ps
CPU time 3.42 seconds
Started Aug 27 07:19:44 AM UTC 24
Finished Aug 27 07:19:49 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298096336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.298096336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.2207667668
Short name T1136
Test name
Test status
Simulation time 594363199 ps
CPU time 7.91 seconds
Started Aug 27 07:19:37 AM UTC 24
Finished Aug 27 07:19:46 AM UTC 24
Peak memory 266452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207667668 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.2207667668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.3110876206
Short name T1186
Test name
Test status
Simulation time 3021070641 ps
CPU time 76.4 seconds
Started Aug 27 07:19:38 AM UTC 24
Finished Aug 27 07:20:56 AM UTC 24
Peak memory 356876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110876206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3110876206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.2072918825
Short name T1188
Test name
Test status
Simulation time 2675024889 ps
CPU time 80.48 seconds
Started Aug 27 07:19:35 AM UTC 24
Finished Aug 27 07:20:57 AM UTC 24
Peak memory 870672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072918825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2072918825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.4075355963
Short name T1131
Test name
Test status
Simulation time 124096943 ps
CPU time 1.54 seconds
Started Aug 27 07:19:36 AM UTC 24
Finished Aug 27 07:19:38 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075355963 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.4075355963
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.2329543619
Short name T1134
Test name
Test status
Simulation time 707148525 ps
CPU time 6.74 seconds
Started Aug 27 07:19:37 AM UTC 24
Finished Aug 27 07:19:45 AM UTC 24
Peak memory 252040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329543619 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.2329543619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.4038674059
Short name T1187
Test name
Test status
Simulation time 17373443845 ps
CPU time 80.13 seconds
Started Aug 27 07:19:35 AM UTC 24
Finished Aug 27 07:20:56 AM UTC 24
Peak memory 1284596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038674059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.4038674059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.760654295
Short name T1161
Test name
Test status
Simulation time 514593280 ps
CPU time 8.23 seconds
Started Aug 27 07:20:04 AM UTC 24
Finished Aug 27 07:20:13 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760654295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.760654295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_override.1156595271
Short name T1127
Test name
Test status
Simulation time 49796768 ps
CPU time 1.05 seconds
Started Aug 27 07:19:33 AM UTC 24
Finished Aug 27 07:19:35 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156595271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1156595271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_perf.2574157170
Short name T1135
Test name
Test status
Simulation time 393722751 ps
CPU time 5.54 seconds
Started Aug 27 07:19:39 AM UTC 24
Finished Aug 27 07:19:46 AM UTC 24
Peak memory 241832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574157170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2574157170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.540881488
Short name T1133
Test name
Test status
Simulation time 242518392 ps
CPU time 3.92 seconds
Started Aug 27 07:19:39 AM UTC 24
Finished Aug 27 07:19:44 AM UTC 24
Peak memory 230796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540881488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.540881488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.1138399176
Short name T1154
Test name
Test status
Simulation time 19619570352 ps
CPU time 35.14 seconds
Started Aug 27 07:19:33 AM UTC 24
Finished Aug 27 07:20:10 AM UTC 24
Peak memory 348428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138399176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1138399176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_stress_all.1938954296
Short name T291
Test name
Test status
Simulation time 14737688572 ps
CPU time 436.65 seconds
Started Aug 27 07:19:45 AM UTC 24
Finished Aug 27 07:27:07 AM UTC 24
Peak memory 2187540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938954296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1938954296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.3886534638
Short name T1146
Test name
Test status
Simulation time 5403375941 ps
CPU time 18.45 seconds
Started Aug 27 07:19:42 AM UTC 24
Finished Aug 27 07:20:02 AM UTC 24
Peak memory 234032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886534638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3886534638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.2706918739
Short name T1158
Test name
Test status
Simulation time 2032513836 ps
CPU time 8.35 seconds
Started Aug 27 07:20:03 AM UTC 24
Finished Aug 27 07:20:12 AM UTC 24
Peak memory 226860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2706918739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_ad
dr.2706918739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.3499794420
Short name T1144
Test name
Test status
Simulation time 435999254 ps
CPU time 2.16 seconds
Started Aug 27 07:19:58 AM UTC 24
Finished Aug 27 07:20:01 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499794
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.3499794420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.3882609873
Short name T1145
Test name
Test status
Simulation time 311532176 ps
CPU time 1.31 seconds
Started Aug 27 07:19:59 AM UTC 24
Finished Aug 27 07:20:02 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882609
873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.3882609873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.898033195
Short name T1155
Test name
Test status
Simulation time 520280305 ps
CPU time 4.85 seconds
Started Aug 27 07:20:05 AM UTC 24
Finished Aug 27 07:20:11 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8980331
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_acq.898033195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.285260682
Short name T1153
Test name
Test status
Simulation time 148500266 ps
CPU time 1.89 seconds
Started Aug 27 07:20:06 AM UTC 24
Finished Aug 27 07:20:09 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852606
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermarks
_tx.285260682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.1330910660
Short name T1142
Test name
Test status
Simulation time 1609851497 ps
CPU time 6.27 seconds
Started Aug 27 07:19:50 AM UTC 24
Finished Aug 27 07:19:57 AM UTC 24
Peak memory 226884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133091
0660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.1330910660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.4276263400
Short name T1148
Test name
Test status
Simulation time 22114542149 ps
CPU time 9.68 seconds
Started Aug 27 07:19:53 AM UTC 24
Finished Aug 27 07:20:04 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4276263400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stres
s_wr.4276263400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.1266019125
Short name T61
Test name
Test status
Simulation time 534582052 ps
CPU time 5.1 seconds
Started Aug 27 07:20:07 AM UTC 24
Finished Aug 27 07:20:13 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266019
125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.1266019125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.1791096237
Short name T1164
Test name
Test status
Simulation time 786991251 ps
CPU time 5.64 seconds
Started Aug 27 07:20:08 AM UTC 24
Finished Aug 27 07:20:15 AM UTC 24
Peak memory 216860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791096
237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_ad
dr.1791096237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_perf.3277165930
Short name T1151
Test name
Test status
Simulation time 1832207643 ps
CPU time 5.24 seconds
Started Aug 27 07:20:00 AM UTC 24
Finished Aug 27 07:20:07 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277165
930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.3277165930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.4011138686
Short name T1157
Test name
Test status
Simulation time 1082885001 ps
CPU time 3.66 seconds
Started Aug 27 07:20:07 AM UTC 24
Finished Aug 27 07:20:12 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011138
686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.4011138686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.344981690
Short name T1149
Test name
Test status
Simulation time 15215681522 ps
CPU time 19 seconds
Started Aug 27 07:19:45 AM UTC 24
Finished Aug 27 07:20:06 AM UTC 24
Peak memory 231028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344981690 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.344981690
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.539011249
Short name T1234
Test name
Test status
Simulation time 10775370644 ps
CPU time 102.81 seconds
Started Aug 27 07:20:01 AM UTC 24
Finished Aug 27 07:21:46 AM UTC 24
Peak memory 833704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539011
249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.539011249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.3280236247
Short name T1150
Test name
Test status
Simulation time 702655548 ps
CPU time 18.01 seconds
Started Aug 27 07:19:47 AM UTC 24
Finished Aug 27 07:20:06 AM UTC 24
Peak memory 228744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280236247 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.3280236247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2736218386
Short name T1746
Test name
Test status
Simulation time 60239679876 ps
CPU time 1178.53 seconds
Started Aug 27 07:19:47 AM UTC 24
Finished Aug 27 07:39:37 AM UTC 24
Peak memory 9181460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736218386 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.2736218386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2621902577
Short name T1152
Test name
Test status
Simulation time 1419687413 ps
CPU time 19.4 seconds
Started Aug 27 07:19:47 AM UTC 24
Finished Aug 27 07:20:07 AM UTC 24
Peak memory 432480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621902577 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.2621902577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.3049999618
Short name T1147
Test name
Test status
Simulation time 8102176803 ps
CPU time 8.18 seconds
Started Aug 27 07:19:54 AM UTC 24
Finished Aug 27 07:20:03 AM UTC 24
Peak memory 233860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049999
618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.3049999618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.1901675187
Short name T1156
Test name
Test status
Simulation time 95112922 ps
CPU time 3.78 seconds
Started Aug 27 07:20:06 AM UTC 24
Finished Aug 27 07:20:11 AM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901675
187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.1901675187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_alert_test.1110004147
Short name T1190
Test name
Test status
Simulation time 30730027 ps
CPU time 0.98 seconds
Started Aug 27 07:20:57 AM UTC 24
Finished Aug 27 07:20:59 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110004147 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1110004147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.944392477
Short name T1170
Test name
Test status
Simulation time 246360486 ps
CPU time 10.99 seconds
Started Aug 27 07:20:16 AM UTC 24
Finished Aug 27 07:20:28 AM UTC 24
Peak memory 252324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944392477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.944392477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.1536159883
Short name T1171
Test name
Test status
Simulation time 1952988889 ps
CPU time 14.27 seconds
Started Aug 27 07:20:14 AM UTC 24
Finished Aug 27 07:20:29 AM UTC 24
Peak memory 323664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536159883 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.1536159883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.1425199848
Short name T1228
Test name
Test status
Simulation time 2618689703 ps
CPU time 85.39 seconds
Started Aug 27 07:20:14 AM UTC 24
Finished Aug 27 07:21:41 AM UTC 24
Peak memory 789068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425199848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1425199848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.581876285
Short name T1232
Test name
Test status
Simulation time 16055324116 ps
CPU time 89.76 seconds
Started Aug 27 07:20:13 AM UTC 24
Finished Aug 27 07:21:44 AM UTC 24
Peak memory 829600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581876285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.581876285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.493764234
Short name T1165
Test name
Test status
Simulation time 418276676 ps
CPU time 1.54 seconds
Started Aug 27 07:20:13 AM UTC 24
Finished Aug 27 07:20:15 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493764234 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.493764234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.3019783311
Short name T1168
Test name
Test status
Simulation time 422338782 ps
CPU time 5.98 seconds
Started Aug 27 07:20:14 AM UTC 24
Finished Aug 27 07:20:21 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019783311 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.3019783311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.934712277
Short name T1215
Test name
Test status
Simulation time 12642037607 ps
CPU time 74.86 seconds
Started Aug 27 07:20:13 AM UTC 24
Finished Aug 27 07:21:29 AM UTC 24
Peak memory 993692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934712277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.934712277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.2286746818
Short name T1199
Test name
Test status
Simulation time 482909911 ps
CPU time 21.99 seconds
Started Aug 27 07:20:47 AM UTC 24
Finished Aug 27 07:21:10 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286746818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2286746818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_override.3830064401
Short name T1163
Test name
Test status
Simulation time 27752078 ps
CPU time 0.87 seconds
Started Aug 27 07:20:12 AM UTC 24
Finished Aug 27 07:20:13 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830064401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3830064401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_perf.2012598579
Short name T1307
Test name
Test status
Simulation time 27752219926 ps
CPU time 177.95 seconds
Started Aug 27 07:20:14 AM UTC 24
Finished Aug 27 07:23:15 AM UTC 24
Peak memory 1560804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012598579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2012598579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.1953108764
Short name T1180
Test name
Test status
Simulation time 6431088375 ps
CPU time 31.8 seconds
Started Aug 27 07:20:14 AM UTC 24
Finished Aug 27 07:20:47 AM UTC 24
Peak memory 528540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953108764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1953108764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.2411343417
Short name T1207
Test name
Test status
Simulation time 1339983409 ps
CPU time 67.55 seconds
Started Aug 27 07:20:12 AM UTC 24
Finished Aug 27 07:21:21 AM UTC 24
Peak memory 348452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411343417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2411343417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.542241197
Short name T1752
Test name
Test status
Simulation time 15540646519 ps
CPU time 1457.8 seconds
Started Aug 27 07:20:16 AM UTC 24
Finished Aug 27 07:44:49 AM UTC 24
Peak memory 3051664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542241197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.542241197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.921143171
Short name T1177
Test name
Test status
Simulation time 599115636 ps
CPU time 28.27 seconds
Started Aug 27 07:20:15 AM UTC 24
Finished Aug 27 07:20:45 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921143171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.921143171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.679549595
Short name T1118
Test name
Test status
Simulation time 13714125846 ps
CPU time 9.4 seconds
Started Aug 27 07:20:45 AM UTC 24
Finished Aug 27 07:20:55 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=679549595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.679549595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.3494294440
Short name T1174
Test name
Test status
Simulation time 262356859 ps
CPU time 1.57 seconds
Started Aug 27 07:20:39 AM UTC 24
Finished Aug 27 07:20:42 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494294
440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.3494294440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.3683786607
Short name T1176
Test name
Test status
Simulation time 727151964 ps
CPU time 2.23 seconds
Started Aug 27 07:20:40 AM UTC 24
Finished Aug 27 07:20:44 AM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683786
607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.3683786607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.961966269
Short name T1160
Test name
Test status
Simulation time 2568290259 ps
CPU time 5.88 seconds
Started Aug 27 07:20:48 AM UTC 24
Finished Aug 27 07:20:55 AM UTC 24
Peak memory 216976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9619662
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_acq.961966269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.2860466727
Short name T1183
Test name
Test status
Simulation time 124309828 ps
CPU time 1.96 seconds
Started Aug 27 07:20:51 AM UTC 24
Finished Aug 27 07:20:54 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860466
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.2860466727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.573791473
Short name T1181
Test name
Test status
Simulation time 848425380 ps
CPU time 3.48 seconds
Started Aug 27 07:20:46 AM UTC 24
Finished Aug 27 07:20:50 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5737914
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_hrst.573791473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.2186853192
Short name T1175
Test name
Test status
Simulation time 5517205856 ps
CPU time 11.57 seconds
Started Aug 27 07:20:30 AM UTC 24
Finished Aug 27 07:20:42 AM UTC 24
Peak memory 243872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218685
3192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.2186853192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.520506099
Short name T1451
Test name
Test status
Simulation time 20088723365 ps
CPU time 349.06 seconds
Started Aug 27 07:20:32 AM UTC 24
Finished Aug 27 07:26:25 AM UTC 24
Peak memory 4892820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=520506099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stress
_wr.520506099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.1099494968
Short name T1192
Test name
Test status
Simulation time 4147130981 ps
CPU time 4.03 seconds
Started Aug 27 07:20:54 AM UTC 24
Finished Aug 27 07:20:59 AM UTC 24
Peak memory 226640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099494
968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.1099494968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.3510154989
Short name T1194
Test name
Test status
Simulation time 1946591238 ps
CPU time 4.26 seconds
Started Aug 27 07:20:55 AM UTC 24
Finished Aug 27 07:21:01 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510154
989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.3510154989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_perf.2519915455
Short name T1182
Test name
Test status
Simulation time 4704212064 ps
CPU time 8.9 seconds
Started Aug 27 07:20:42 AM UTC 24
Finished Aug 27 07:20:52 AM UTC 24
Peak memory 233168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519915
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.2519915455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.1013028734
Short name T1189
Test name
Test status
Simulation time 529030545 ps
CPU time 3.81 seconds
Started Aug 27 07:20:53 AM UTC 24
Finished Aug 27 07:20:58 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013028
734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.1013028734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.1408164793
Short name T1173
Test name
Test status
Simulation time 2697941101 ps
CPU time 20.27 seconds
Started Aug 27 07:20:19 AM UTC 24
Finished Aug 27 07:20:40 AM UTC 24
Peak memory 231116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408164793 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.1408164793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.4091459571
Short name T1267
Test name
Test status
Simulation time 55650393040 ps
CPU time 98.96 seconds
Started Aug 27 07:20:44 AM UTC 24
Finished Aug 27 07:22:24 AM UTC 24
Peak memory 756192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409145
9571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.4091459571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.473805755
Short name T1172
Test name
Test status
Simulation time 280748244 ps
CPU time 7.13 seconds
Started Aug 27 07:20:27 AM UTC 24
Finished Aug 27 07:20:35 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473805755 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.473805755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.4174374596
Short name T1202
Test name
Test status
Simulation time 22162097418 ps
CPU time 51.04 seconds
Started Aug 27 07:20:22 AM UTC 24
Finished Aug 27 07:21:14 AM UTC 24
Peak memory 495760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174374596 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.4174374596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.3655448163
Short name T1301
Test name
Test status
Simulation time 3873496692 ps
CPU time 154.14 seconds
Started Aug 27 07:20:30 AM UTC 24
Finished Aug 27 07:23:06 AM UTC 24
Peak memory 1069308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655448163 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.3655448163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.3459770641
Short name T1179
Test name
Test status
Simulation time 6396699570 ps
CPU time 12.07 seconds
Started Aug 27 07:20:33 AM UTC 24
Finished Aug 27 07:20:46 AM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459770
641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.3459770641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.3493986514
Short name T1195
Test name
Test status
Simulation time 675938540 ps
CPU time 9.91 seconds
Started Aug 27 07:20:51 AM UTC 24
Finished Aug 27 07:21:02 AM UTC 24
Peak memory 218568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493986
514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.3493986514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_alert_test.1076211208
Short name T1221
Test name
Test status
Simulation time 28741522 ps
CPU time 0.95 seconds
Started Aug 27 07:21:32 AM UTC 24
Finished Aug 27 07:21:34 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076211208 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1076211208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.1971510096
Short name T1201
Test name
Test status
Simulation time 4434500984 ps
CPU time 8.06 seconds
Started Aug 27 07:21:03 AM UTC 24
Finished Aug 27 07:21:12 AM UTC 24
Peak memory 233672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971510096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1971510096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.1701755446
Short name T1200
Test name
Test status
Simulation time 1121624229 ps
CPU time 9.92 seconds
Started Aug 27 07:21:00 AM UTC 24
Finished Aug 27 07:21:11 AM UTC 24
Peak memory 278552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701755446 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.1701755446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.683394874
Short name T1255
Test name
Test status
Simulation time 5258219938 ps
CPU time 63.25 seconds
Started Aug 27 07:21:00 AM UTC 24
Finished Aug 27 07:22:05 AM UTC 24
Peak memory 428304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683394874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.683394874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.21800867
Short name T1260
Test name
Test status
Simulation time 2878612844 ps
CPU time 68.1 seconds
Started Aug 27 07:20:58 AM UTC 24
Finished Aug 27 07:22:08 AM UTC 24
Peak memory 729292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21800867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.21800867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.4145800633
Short name T257
Test name
Test status
Simulation time 423696931 ps
CPU time 1.5 seconds
Started Aug 27 07:20:59 AM UTC 24
Finished Aug 27 07:21:01 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145800633 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.4145800633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1169475423
Short name T1197
Test name
Test status
Simulation time 531347865 ps
CPU time 4.66 seconds
Started Aug 27 07:21:00 AM UTC 24
Finished Aug 27 07:21:06 AM UTC 24
Peak memory 243800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169475423 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.1169475423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.802716954
Short name T1326
Test name
Test status
Simulation time 11768672150 ps
CPU time 153.71 seconds
Started Aug 27 07:20:58 AM UTC 24
Finished Aug 27 07:23:34 AM UTC 24
Peak memory 966848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802716954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.802716954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.346189915
Short name T1219
Test name
Test status
Simulation time 1213054415 ps
CPU time 5.91 seconds
Started Aug 27 07:21:25 AM UTC 24
Finished Aug 27 07:21:32 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346189915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.346189915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_override.3237551324
Short name T1191
Test name
Test status
Simulation time 98400900 ps
CPU time 0.94 seconds
Started Aug 27 07:20:57 AM UTC 24
Finished Aug 27 07:20:59 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237551324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3237551324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_perf.2491206339
Short name T46
Test name
Test status
Simulation time 29739274910 ps
CPU time 42.78 seconds
Started Aug 27 07:21:01 AM UTC 24
Finished Aug 27 07:21:46 AM UTC 24
Peak memory 260380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491206339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2491206339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.763518443
Short name T1196
Test name
Test status
Simulation time 99939558 ps
CPU time 2.4 seconds
Started Aug 27 07:21:01 AM UTC 24
Finished Aug 27 07:21:05 AM UTC 24
Peak memory 238856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763518443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.763518443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.7336977
Short name T1204
Test name
Test status
Simulation time 1038755525 ps
CPU time 19.03 seconds
Started Aug 27 07:20:57 AM UTC 24
Finished Aug 27 07:21:17 AM UTC 24
Peak memory 249588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7336977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos
t_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.7336977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.1739756426
Short name T1203
Test name
Test status
Simulation time 1075131709 ps
CPU time 14.63 seconds
Started Aug 27 07:21:01 AM UTC 24
Finished Aug 27 07:21:17 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739756426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1739756426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.2340674386
Short name T1216
Test name
Test status
Simulation time 1342143565 ps
CPU time 7.41 seconds
Started Aug 27 07:21:22 AM UTC 24
Finished Aug 27 07:21:31 AM UTC 24
Peak memory 228940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2340674386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_ad
dr.2340674386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.387288376
Short name T1208
Test name
Test status
Simulation time 198401733 ps
CPU time 2.04 seconds
Started Aug 27 07:21:18 AM UTC 24
Finished Aug 27 07:21:21 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872883
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.387288376
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.3021872896
Short name T1209
Test name
Test status
Simulation time 198662194 ps
CPU time 1.49 seconds
Started Aug 27 07:21:20 AM UTC 24
Finished Aug 27 07:21:23 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021872
896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.3021872896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.3160041465
Short name T1218
Test name
Test status
Simulation time 1777463311 ps
CPU time 4.5 seconds
Started Aug 27 07:21:26 AM UTC 24
Finished Aug 27 07:21:32 AM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160041
465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermar
ks_acq.3160041465
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.1019854786
Short name T1214
Test name
Test status
Simulation time 645343865 ps
CPU time 1.77 seconds
Started Aug 27 07:21:26 AM UTC 24
Finished Aug 27 07:21:29 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019854
786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.1019854786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.1835994402
Short name T1210
Test name
Test status
Simulation time 21606163628 ps
CPU time 11.01 seconds
Started Aug 27 07:21:12 AM UTC 24
Finished Aug 27 07:21:24 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183599
4402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.1835994402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.2293471495
Short name T1247
Test name
Test status
Simulation time 25211697589 ps
CPU time 44.81 seconds
Started Aug 27 07:21:13 AM UTC 24
Finished Aug 27 07:21:59 AM UTC 24
Peak memory 889240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2293471495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.2293471495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.289034165
Short name T1225
Test name
Test status
Simulation time 576539201 ps
CPU time 5.3 seconds
Started Aug 27 07:21:29 AM UTC 24
Finished Aug 27 07:21:36 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890341
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.289034165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.520330629
Short name T1223
Test name
Test status
Simulation time 574456174 ps
CPU time 3.59 seconds
Started Aug 27 07:21:29 AM UTC 24
Finished Aug 27 07:21:34 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5203306
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.520330629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.2875030598
Short name T1222
Test name
Test status
Simulation time 257803875 ps
CPU time 2.38 seconds
Started Aug 27 07:21:31 AM UTC 24
Finished Aug 27 07:21:34 AM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875030
598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.2875030598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_perf.3344172630
Short name T1217
Test name
Test status
Simulation time 2885040626 ps
CPU time 7.63 seconds
Started Aug 27 07:21:22 AM UTC 24
Finished Aug 27 07:21:31 AM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344172
630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.3344172630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.507458583
Short name T1220
Test name
Test status
Simulation time 463087094 ps
CPU time 3.27 seconds
Started Aug 27 07:21:28 AM UTC 24
Finished Aug 27 07:21:33 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5074585
83 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.507458583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.2247351122
Short name T95
Test name
Test status
Simulation time 764198378 ps
CPU time 28.18 seconds
Started Aug 27 07:21:07 AM UTC 24
Finished Aug 27 07:21:37 AM UTC 24
Peak memory 230952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247351122 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.2247351122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.754068788
Short name T1487
Test name
Test status
Simulation time 44923999518 ps
CPU time 357.36 seconds
Started Aug 27 07:21:22 AM UTC 24
Finished Aug 27 07:27:23 AM UTC 24
Peak memory 2744476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754068
788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.754068788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.2881042579
Short name T1227
Test name
Test status
Simulation time 1956783094 ps
CPU time 29.34 seconds
Started Aug 27 07:21:08 AM UTC 24
Finished Aug 27 07:21:39 AM UTC 24
Peak memory 245776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881042579 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.2881042579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.3422492348
Short name T1213
Test name
Test status
Simulation time 15434212649 ps
CPU time 19.63 seconds
Started Aug 27 07:21:07 AM UTC 24
Finished Aug 27 07:21:28 AM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422492348 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.3422492348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.102151579
Short name T1206
Test name
Test status
Simulation time 2967491003 ps
CPU time 8.72 seconds
Started Aug 27 07:21:11 AM UTC 24
Finished Aug 27 07:21:21 AM UTC 24
Peak memory 262344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102151579 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.102151579
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.4119783428
Short name T1211
Test name
Test status
Simulation time 18499423841 ps
CPU time 8.47 seconds
Started Aug 27 07:21:15 AM UTC 24
Finished Aug 27 07:21:25 AM UTC 24
Peak memory 227048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119783
428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.4119783428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_alert_test.4194160219
Short name T1254
Test name
Test status
Simulation time 50383908 ps
CPU time 0.92 seconds
Started Aug 27 07:22:01 AM UTC 24
Finished Aug 27 07:22:03 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194160219 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.4194160219
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.853871988
Short name T1235
Test name
Test status
Simulation time 1596020958 ps
CPU time 5.82 seconds
Started Aug 27 07:21:40 AM UTC 24
Finished Aug 27 07:21:47 AM UTC 24
Peak memory 243780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853871988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.853871988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.4115316807
Short name T1237
Test name
Test status
Simulation time 461220933 ps
CPU time 12.39 seconds
Started Aug 27 07:21:35 AM UTC 24
Finished Aug 27 07:21:49 AM UTC 24
Peak memory 243648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115316807 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.4115316807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.2010345407
Short name T1290
Test name
Test status
Simulation time 5372082057 ps
CPU time 64.12 seconds
Started Aug 27 07:21:36 AM UTC 24
Finished Aug 27 07:22:42 AM UTC 24
Peak memory 581840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010345407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2010345407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.1367054039
Short name T1273
Test name
Test status
Simulation time 4477981794 ps
CPU time 55.81 seconds
Started Aug 27 07:21:34 AM UTC 24
Finished Aug 27 07:22:31 AM UTC 24
Peak memory 714952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367054039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1367054039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.2411943810
Short name T1226
Test name
Test status
Simulation time 108331603 ps
CPU time 1.79 seconds
Started Aug 27 07:21:34 AM UTC 24
Finished Aug 27 07:21:37 AM UTC 24
Peak memory 215200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411943810 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.2411943810
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.1579365398
Short name T1229
Test name
Test status
Simulation time 252181937 ps
CPU time 6.43 seconds
Started Aug 27 07:21:35 AM UTC 24
Finished Aug 27 07:21:43 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579365398 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.1579365398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.2347421520
Short name T1364
Test name
Test status
Simulation time 12556862394 ps
CPU time 174.04 seconds
Started Aug 27 07:21:33 AM UTC 24
Finished Aug 27 07:24:30 AM UTC 24
Peak memory 989400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347421520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2347421520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1912709086
Short name T1246
Test name
Test status
Simulation time 386023363 ps
CPU time 3.79 seconds
Started Aug 27 07:21:54 AM UTC 24
Finished Aug 27 07:21:59 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912709086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1912709086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.690870366
Short name T1248
Test name
Test status
Simulation time 274623344 ps
CPU time 7.05 seconds
Started Aug 27 07:21:52 AM UTC 24
Finished Aug 27 07:22:00 AM UTC 24
Peak memory 243832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690870366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.690870366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_override.4229942384
Short name T1224
Test name
Test status
Simulation time 27861329 ps
CPU time 1.03 seconds
Started Aug 27 07:21:33 AM UTC 24
Finished Aug 27 07:21:35 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229942384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.4229942384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_perf.4125286719
Short name T1230
Test name
Test status
Simulation time 1172989218 ps
CPU time 6.13 seconds
Started Aug 27 07:21:36 AM UTC 24
Finished Aug 27 07:21:44 AM UTC 24
Peak memory 237712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125286719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4125286719
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.1034650137
Short name T1233
Test name
Test status
Simulation time 238390139 ps
CPU time 6.26 seconds
Started Aug 27 07:21:37 AM UTC 24
Finished Aug 27 07:21:45 AM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034650137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.1034650137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.1136389792
Short name T1245
Test name
Test status
Simulation time 2983214455 ps
CPU time 23.41 seconds
Started Aug 27 07:21:32 AM UTC 24
Finished Aug 27 07:21:56 AM UTC 24
Peak memory 309516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136389792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1136389792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.4128272425
Short name T1240
Test name
Test status
Simulation time 945313563 ps
CPU time 12.72 seconds
Started Aug 27 07:21:37 AM UTC 24
Finished Aug 27 07:21:51 AM UTC 24
Peak memory 232912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128272425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4128272425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.968941498
Short name T1243
Test name
Test status
Simulation time 10555442497 ps
CPU time 3.54 seconds
Started Aug 27 07:21:52 AM UTC 24
Finished Aug 27 07:21:56 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=968941498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.968941498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3857103254
Short name T1238
Test name
Test status
Simulation time 660221062 ps
CPU time 2.3 seconds
Started Aug 27 07:21:47 AM UTC 24
Finished Aug 27 07:21:51 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857103
254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3857103254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.1466239789
Short name T1239
Test name
Test status
Simulation time 337523780 ps
CPU time 1.68 seconds
Started Aug 27 07:21:48 AM UTC 24
Finished Aug 27 07:21:51 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466239
789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.1466239789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.2389624932
Short name T1253
Test name
Test status
Simulation time 566529985 ps
CPU time 3.99 seconds
Started Aug 27 07:21:57 AM UTC 24
Finished Aug 27 07:22:02 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389624
932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermar
ks_acq.2389624932
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2308295152
Short name T1250
Test name
Test status
Simulation time 482204979 ps
CPU time 2.04 seconds
Started Aug 27 07:21:57 AM UTC 24
Finished Aug 27 07:22:00 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308295
152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_tx.2308295152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.192424505
Short name T1241
Test name
Test status
Simulation time 996584288 ps
CPU time 6.92 seconds
Started Aug 27 07:21:45 AM UTC 24
Finished Aug 27 07:21:53 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192424
505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.192424505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3790980785
Short name T1597
Test name
Test status
Simulation time 24902362591 ps
CPU time 492.97 seconds
Started Aug 27 07:21:46 AM UTC 24
Finished Aug 27 07:30:05 AM UTC 24
Peak memory 4558996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3790980785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stres
s_wr.3790980785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.3268048109
Short name T1258
Test name
Test status
Simulation time 2025863369 ps
CPU time 4.81 seconds
Started Aug 27 07:21:59 AM UTC 24
Finished Aug 27 07:22:05 AM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268048
109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.3268048109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.1859885726
Short name T1257
Test name
Test status
Simulation time 935513758 ps
CPU time 2.49 seconds
Started Aug 27 07:22:01 AM UTC 24
Finished Aug 27 07:22:04 AM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859885
726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_ad
dr.1859885726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3597873913
Short name T1244
Test name
Test status
Simulation time 3413429054 ps
CPU time 5.79 seconds
Started Aug 27 07:21:50 AM UTC 24
Finished Aug 27 07:21:56 AM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597873
913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.3597873913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.2754112252
Short name T1252
Test name
Test status
Simulation time 953183848 ps
CPU time 3.54 seconds
Started Aug 27 07:21:57 AM UTC 24
Finished Aug 27 07:22:02 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754112
252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.2754112252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.1741512683
Short name T1281
Test name
Test status
Simulation time 10604841245 ps
CPU time 52.7 seconds
Started Aug 27 07:21:44 AM UTC 24
Finished Aug 27 07:22:38 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741512683 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.1741512683
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.3692653890
Short name T1755
Test name
Test status
Simulation time 67487747320 ps
CPU time 1634.22 seconds
Started Aug 27 07:21:51 AM UTC 24
Finished Aug 27 07:49:19 AM UTC 24
Peak memory 13686944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369265
3890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.3692653890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.3446523105
Short name T1266
Test name
Test status
Simulation time 1795518705 ps
CPU time 35.79 seconds
Started Aug 27 07:21:45 AM UTC 24
Finished Aug 27 07:22:22 AM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446523105 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.3446523105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.154650549
Short name T1723
Test name
Test status
Simulation time 44524884936 ps
CPU time 702.56 seconds
Started Aug 27 07:21:45 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 6566100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154650549 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.154650549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.3427678568
Short name T1284
Test name
Test status
Simulation time 4737910126 ps
CPU time 52.74 seconds
Started Aug 27 07:21:45 AM UTC 24
Finished Aug 27 07:22:39 AM UTC 24
Peak memory 1003744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427678568 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.3427678568
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.3675439523
Short name T1242
Test name
Test status
Simulation time 2542521503 ps
CPU time 7.66 seconds
Started Aug 27 07:21:47 AM UTC 24
Finished Aug 27 07:21:56 AM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675439
523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.3675439523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.184859293
Short name T1251
Test name
Test status
Simulation time 50855529 ps
CPU time 2.02 seconds
Started Aug 27 07:21:57 AM UTC 24
Finished Aug 27 07:22:00 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848592
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.184859293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_alert_test.2349362605
Short name T1286
Test name
Test status
Simulation time 116226308 ps
CPU time 0.91 seconds
Started Aug 27 07:22:38 AM UTC 24
Finished Aug 27 07:22:40 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349362605 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2349362605
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.198797531
Short name T1264
Test name
Test status
Simulation time 387729251 ps
CPU time 4.45 seconds
Started Aug 27 07:22:09 AM UTC 24
Finished Aug 27 07:22:14 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198797531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.198797531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.691110748
Short name T1262
Test name
Test status
Simulation time 193854963 ps
CPU time 4.76 seconds
Started Aug 27 07:22:04 AM UTC 24
Finished Aug 27 07:22:10 AM UTC 24
Peak memory 248096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691110748 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.691110748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.4013573077
Short name T1336
Test name
Test status
Simulation time 3500038736 ps
CPU time 104.74 seconds
Started Aug 27 07:22:05 AM UTC 24
Finished Aug 27 07:23:52 AM UTC 24
Peak memory 596432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013573077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.4013573077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.2439099105
Short name T1332
Test name
Test status
Simulation time 1414452402 ps
CPU time 101.32 seconds
Started Aug 27 07:22:03 AM UTC 24
Finished Aug 27 07:23:46 AM UTC 24
Peak memory 565344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439099105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2439099105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.2763860366
Short name T1259
Test name
Test status
Simulation time 83054800 ps
CPU time 1.64 seconds
Started Aug 27 07:22:03 AM UTC 24
Finished Aug 27 07:22:06 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763860366 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.2763860366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.1474252959
Short name T1263
Test name
Test status
Simulation time 587977803 ps
CPU time 6.08 seconds
Started Aug 27 07:22:05 AM UTC 24
Finished Aug 27 07:22:12 AM UTC 24
Peak memory 243788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474252959 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.1474252959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.2495315056
Short name T1304
Test name
Test status
Simulation time 3608158389 ps
CPU time 66.48 seconds
Started Aug 27 07:22:03 AM UTC 24
Finished Aug 27 07:23:11 AM UTC 24
Peak memory 1118364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495315056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2495315056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.3263884703
Short name T1292
Test name
Test status
Simulation time 596328086 ps
CPU time 11.39 seconds
Started Aug 27 07:22:32 AM UTC 24
Finished Aug 27 07:22:45 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263884703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3263884703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_override.2035192108
Short name T1256
Test name
Test status
Simulation time 43608262 ps
CPU time 1.05 seconds
Started Aug 27 07:22:02 AM UTC 24
Finished Aug 27 07:22:04 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035192108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2035192108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_perf.65025191
Short name T1666
Test name
Test status
Simulation time 26376309952 ps
CPU time 594.15 seconds
Started Aug 27 07:22:06 AM UTC 24
Finished Aug 27 07:32:08 AM UTC 24
Peak memory 2842892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65025191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.65025191
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.1836907519
Short name T1261
Test name
Test status
Simulation time 71728330 ps
CPU time 2.05 seconds
Started Aug 27 07:22:06 AM UTC 24
Finished Aug 27 07:22:09 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836907519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1836907519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.488192300
Short name T1293
Test name
Test status
Simulation time 5059280709 ps
CPU time 44.26 seconds
Started Aug 27 07:22:01 AM UTC 24
Finished Aug 27 07:22:46 AM UTC 24
Peak memory 379172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488192300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.488192300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.566930104
Short name T1268
Test name
Test status
Simulation time 1388118501 ps
CPU time 16.82 seconds
Started Aug 27 07:22:07 AM UTC 24
Finished Aug 27 07:22:25 AM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566930104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.566930104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.1953079654
Short name T1278
Test name
Test status
Simulation time 1385034395 ps
CPU time 5.13 seconds
Started Aug 27 07:22:30 AM UTC 24
Finished Aug 27 07:22:36 AM UTC 24
Peak memory 229056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1953079654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.1953079654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.536357691
Short name T1269
Test name
Test status
Simulation time 286587716 ps
CPU time 1.23 seconds
Started Aug 27 07:22:25 AM UTC 24
Finished Aug 27 07:22:28 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5363576
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.536357691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.1032728077
Short name T1272
Test name
Test status
Simulation time 231570344 ps
CPU time 2.5 seconds
Started Aug 27 07:22:28 AM UTC 24
Finished Aug 27 07:22:31 AM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032728
077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.1032728077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.378310369
Short name T1280
Test name
Test status
Simulation time 935831603 ps
CPU time 3.86 seconds
Started Aug 27 07:22:32 AM UTC 24
Finished Aug 27 07:22:37 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783103
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermark
s_acq.378310369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.899741184
Short name T1279
Test name
Test status
Simulation time 577717104 ps
CPU time 2.25 seconds
Started Aug 27 07:22:33 AM UTC 24
Finished Aug 27 07:22:36 AM UTC 24
Peak memory 216388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8997411
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermarks
_tx.899741184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_hrst.3602964417
Short name T1277
Test name
Test status
Simulation time 2463290257 ps
CPU time 3.06 seconds
Started Aug 27 07:22:30 AM UTC 24
Finished Aug 27 07:22:34 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602964
417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_hrst.3602964417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.970635087
Short name T1271
Test name
Test status
Simulation time 3979644074 ps
CPU time 9.07 seconds
Started Aug 27 07:22:19 AM UTC 24
Finished Aug 27 07:22:29 AM UTC 24
Peak memory 227188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970635
087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.970635087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.2922067676
Short name T1387
Test name
Test status
Simulation time 21540905925 ps
CPU time 161.52 seconds
Started Aug 27 07:22:23 AM UTC 24
Finished Aug 27 07:25:07 AM UTC 24
Peak memory 2566296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2922067676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stres
s_wr.2922067676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.3645587838
Short name T1287
Test name
Test status
Simulation time 2211733755 ps
CPU time 4.63 seconds
Started Aug 27 07:22:34 AM UTC 24
Finished Aug 27 07:22:40 AM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645587
838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.3645587838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.3405544616
Short name T1288
Test name
Test status
Simulation time 9285208867 ps
CPU time 4.3 seconds
Started Aug 27 07:22:36 AM UTC 24
Finished Aug 27 07:22:41 AM UTC 24
Peak memory 216916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405544
616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.3405544616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.537886813
Short name T1285
Test name
Test status
Simulation time 149473196 ps
CPU time 1.86 seconds
Started Aug 27 07:22:37 AM UTC 24
Finished Aug 27 07:22:39 AM UTC 24
Peak memory 232580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5378868
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_txstretch.537886813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_perf.3021496154
Short name T1274
Test name
Test status
Simulation time 2725174330 ps
CPU time 3.68 seconds
Started Aug 27 07:22:28 AM UTC 24
Finished Aug 27 07:22:32 AM UTC 24
Peak memory 227208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021496
154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.3021496154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.501566475
Short name T1283
Test name
Test status
Simulation time 441911095 ps
CPU time 3.53 seconds
Started Aug 27 07:22:34 AM UTC 24
Finished Aug 27 07:22:39 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5015664
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.501566475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.339491769
Short name T1270
Test name
Test status
Simulation time 4596085101 ps
CPU time 17.01 seconds
Started Aug 27 07:22:11 AM UTC 24
Finished Aug 27 07:22:29 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339491769 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.339491769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.3857235738
Short name T1347
Test name
Test status
Simulation time 44561620921 ps
CPU time 94.15 seconds
Started Aug 27 07:22:29 AM UTC 24
Finished Aug 27 07:24:06 AM UTC 24
Peak memory 403632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385723
5738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.3857235738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.1267273401
Short name T1276
Test name
Test status
Simulation time 2521117964 ps
CPU time 19.49 seconds
Started Aug 27 07:22:13 AM UTC 24
Finished Aug 27 07:22:34 AM UTC 24
Peak memory 243916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267273401 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.1267273401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.2328899666
Short name T1479
Test name
Test status
Simulation time 63017229453 ps
CPU time 298.88 seconds
Started Aug 27 07:22:12 AM UTC 24
Finished Aug 27 07:27:15 AM UTC 24
Peak memory 2853272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328899666 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.2328899666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.3780456460
Short name T1265
Test name
Test status
Simulation time 197543329 ps
CPU time 1.93 seconds
Started Aug 27 07:22:15 AM UTC 24
Finished Aug 27 07:22:18 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780456460 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.3780456460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.1350138223
Short name T1275
Test name
Test status
Simulation time 14564433347 ps
CPU time 8.8 seconds
Started Aug 27 07:22:23 AM UTC 24
Finished Aug 27 07:22:33 AM UTC 24
Peak memory 233924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350138
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.1350138223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.1032473241
Short name T1282
Test name
Test status
Simulation time 165965865 ps
CPU time 2.88 seconds
Started Aug 27 07:22:34 AM UTC 24
Finished Aug 27 07:22:38 AM UTC 24
Peak memory 233160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032473
241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.1032473241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_alert_test.3260877648
Short name T1316
Test name
Test status
Simulation time 46619051 ps
CPU time 0.89 seconds
Started Aug 27 07:23:22 AM UTC 24
Finished Aug 27 07:23:24 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260877648 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3260877648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.864760565
Short name T1294
Test name
Test status
Simulation time 594739429 ps
CPU time 2.54 seconds
Started Aug 27 07:22:44 AM UTC 24
Finished Aug 27 07:22:48 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864760565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.864760565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.3338559256
Short name T1298
Test name
Test status
Simulation time 2472083439 ps
CPU time 22.02 seconds
Started Aug 27 07:22:40 AM UTC 24
Finished Aug 27 07:23:03 AM UTC 24
Peak memory 297288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338559256 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.3338559256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.121882889
Short name T1409
Test name
Test status
Simulation time 11686338856 ps
CPU time 172.94 seconds
Started Aug 27 07:22:41 AM UTC 24
Finished Aug 27 07:25:37 AM UTC 24
Peak memory 706832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121882889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.121882889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.825974882
Short name T1378
Test name
Test status
Simulation time 1971735655 ps
CPU time 140.02 seconds
Started Aug 27 07:22:40 AM UTC 24
Finished Aug 27 07:25:02 AM UTC 24
Peak memory 708944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825974882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.825974882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.1617907271
Short name T1291
Test name
Test status
Simulation time 78209424 ps
CPU time 1.43 seconds
Started Aug 27 07:22:40 AM UTC 24
Finished Aug 27 07:22:43 AM UTC 24
Peak memory 216168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617907271 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.1617907271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.708859146
Short name T1296
Test name
Test status
Simulation time 761328169 ps
CPU time 12.51 seconds
Started Aug 27 07:22:40 AM UTC 24
Finished Aug 27 07:22:54 AM UTC 24
Peak memory 251824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708859146 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.708859146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.3722949022
Short name T1368
Test name
Test status
Simulation time 41712254311 ps
CPU time 125.31 seconds
Started Aug 27 07:22:39 AM UTC 24
Finished Aug 27 07:24:46 AM UTC 24
Peak memory 1528080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722949022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3722949022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.3597171653
Short name T1324
Test name
Test status
Simulation time 475365742 ps
CPU time 11.88 seconds
Started Aug 27 07:23:16 AM UTC 24
Finished Aug 27 07:23:29 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597171653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3597171653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_override.3328104528
Short name T1289
Test name
Test status
Simulation time 21174440 ps
CPU time 1.04 seconds
Started Aug 27 07:22:39 AM UTC 24
Finished Aug 27 07:22:41 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328104528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3328104528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_perf.2598886217
Short name T1295
Test name
Test status
Simulation time 1544212784 ps
CPU time 8.32 seconds
Started Aug 27 07:22:41 AM UTC 24
Finished Aug 27 07:22:51 AM UTC 24
Peak memory 249956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598886217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2598886217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.3281897360
Short name T1496
Test name
Test status
Simulation time 24331344189 ps
CPU time 289.57 seconds
Started Aug 27 07:22:41 AM UTC 24
Finished Aug 27 07:27:35 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281897360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.3281897360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.3378932070
Short name T1325
Test name
Test status
Simulation time 1271827204 ps
CPU time 51.07 seconds
Started Aug 27 07:22:38 AM UTC 24
Finished Aug 27 07:23:30 AM UTC 24
Peak memory 309336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378932070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3378932070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.425023862
Short name T1297
Test name
Test status
Simulation time 2187980744 ps
CPU time 11.57 seconds
Started Aug 27 07:22:43 AM UTC 24
Finished Aug 27 07:22:55 AM UTC 24
Peak memory 233600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425023862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.425023862
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.1767541430
Short name T1311
Test name
Test status
Simulation time 933368467 ps
CPU time 6.55 seconds
Started Aug 27 07:23:12 AM UTC 24
Finished Aug 27 07:23:19 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1767541430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad
dr.1767541430
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.3509791590
Short name T1305
Test name
Test status
Simulation time 392412340 ps
CPU time 2.26 seconds
Started Aug 27 07:23:07 AM UTC 24
Finished Aug 27 07:23:11 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509791
590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.3509791590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.943114404
Short name T1306
Test name
Test status
Simulation time 196893745 ps
CPU time 1.91 seconds
Started Aug 27 07:23:11 AM UTC 24
Finished Aug 27 07:23:13 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9431144
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.943114404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.1820602805
Short name T1314
Test name
Test status
Simulation time 587732903 ps
CPU time 3.56 seconds
Started Aug 27 07:23:16 AM UTC 24
Finished Aug 27 07:23:21 AM UTC 24
Peak memory 216440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820602
805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar
ks_acq.1820602805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.992650504
Short name T1313
Test name
Test status
Simulation time 113753119 ps
CPU time 2.26 seconds
Started Aug 27 07:23:17 AM UTC 24
Finished Aug 27 07:23:20 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9926505
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermarks
_tx.992650504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.3115749329
Short name T1308
Test name
Test status
Simulation time 703499198 ps
CPU time 2.12 seconds
Started Aug 27 07:23:12 AM UTC 24
Finished Aug 27 07:23:15 AM UTC 24
Peak memory 226552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115749
329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.3115749329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.160488768
Short name T1300
Test name
Test status
Simulation time 3958744285 ps
CPU time 8.02 seconds
Started Aug 27 07:22:56 AM UTC 24
Finished Aug 27 07:23:05 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160488
768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.160488768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.3027438025
Short name T1302
Test name
Test status
Simulation time 4731586588 ps
CPU time 4.06 seconds
Started Aug 27 07:23:04 AM UTC 24
Finished Aug 27 07:23:09 AM UTC 24
Peak memory 250260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3027438025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres
s_wr.3027438025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.588285524
Short name T1319
Test name
Test status
Simulation time 432261397 ps
CPU time 3.44 seconds
Started Aug 27 07:23:20 AM UTC 24
Finished Aug 27 07:23:25 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5882855
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.588285524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.1042644971
Short name T1320
Test name
Test status
Simulation time 472962322 ps
CPU time 3.93 seconds
Started Aug 27 07:23:22 AM UTC 24
Finished Aug 27 07:23:27 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042644
971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad
dr.1042644971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_nack_txstretch.2209859919
Short name T1318
Test name
Test status
Simulation time 368181736 ps
CPU time 2.23 seconds
Started Aug 27 07:23:22 AM UTC 24
Finished Aug 27 07:23:25 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209859
919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_txstretch.2209859919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_perf.3121316217
Short name T1310
Test name
Test status
Simulation time 655128262 ps
CPU time 7.31 seconds
Started Aug 27 07:23:11 AM UTC 24
Finished Aug 27 07:23:19 AM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121316
217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.3121316217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.283795244
Short name T1317
Test name
Test status
Simulation time 820250080 ps
CPU time 3.54 seconds
Started Aug 27 07:23:19 AM UTC 24
Finished Aug 27 07:23:24 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837952
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.283795244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.395963065
Short name T1303
Test name
Test status
Simulation time 1150215664 ps
CPU time 22.22 seconds
Started Aug 27 07:22:47 AM UTC 24
Finished Aug 27 07:23:10 AM UTC 24
Peak memory 233876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395963065 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.395963065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.3292883576
Short name T1402
Test name
Test status
Simulation time 23796578105 ps
CPU time 130.07 seconds
Started Aug 27 07:23:12 AM UTC 24
Finished Aug 27 07:25:24 AM UTC 24
Peak memory 1722528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329288
3576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.3292883576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.495725443
Short name T1312
Test name
Test status
Simulation time 541648565 ps
CPU time 26.88 seconds
Started Aug 27 07:22:52 AM UTC 24
Finished Aug 27 07:23:20 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495725443 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.495725443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.3088323739
Short name T1299
Test name
Test status
Simulation time 20366239139 ps
CPU time 13.82 seconds
Started Aug 27 07:22:49 AM UTC 24
Finished Aug 27 07:23:04 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088323739 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.3088323739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.2049154339
Short name T1322
Test name
Test status
Simulation time 4269990590 ps
CPU time 31.52 seconds
Started Aug 27 07:22:55 AM UTC 24
Finished Aug 27 07:23:28 AM UTC 24
Peak memory 362756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049154339 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.2049154339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3484467412
Short name T1309
Test name
Test status
Simulation time 2489636564 ps
CPU time 10.23 seconds
Started Aug 27 07:23:05 AM UTC 24
Finished Aug 27 07:23:17 AM UTC 24
Peak memory 231108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484467
412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3484467412
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3310483914
Short name T1315
Test name
Test status
Simulation time 87051668 ps
CPU time 3.44 seconds
Started Aug 27 07:23:17 AM UTC 24
Finished Aug 27 07:23:22 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310483
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3310483914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_alert_test.3875611411
Short name T1351
Test name
Test status
Simulation time 17041512 ps
CPU time 0.96 seconds
Started Aug 27 07:24:07 AM UTC 24
Finished Aug 27 07:24:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875611411 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3875611411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.1060056793
Short name T1327
Test name
Test status
Simulation time 63829038 ps
CPU time 3.3 seconds
Started Aug 27 07:23:32 AM UTC 24
Finished Aug 27 07:23:36 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060056793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1060056793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.1640253542
Short name T1329
Test name
Test status
Simulation time 1538061037 ps
CPU time 10.65 seconds
Started Aug 27 07:23:27 AM UTC 24
Finished Aug 27 07:23:39 AM UTC 24
Peak memory 260428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640253542 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.1640253542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.482198202
Short name T1362
Test name
Test status
Simulation time 7977194002 ps
CPU time 54.52 seconds
Started Aug 27 07:23:28 AM UTC 24
Finished Aug 27 07:24:24 AM UTC 24
Peak memory 446732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482198202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.482198202
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.3300765070
Short name T1374
Test name
Test status
Simulation time 2367975044 ps
CPU time 89.17 seconds
Started Aug 27 07:23:26 AM UTC 24
Finished Aug 27 07:24:57 AM UTC 24
Peak memory 786660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300765070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3300765070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.4081435185
Short name T1323
Test name
Test status
Simulation time 268506436 ps
CPU time 1.54 seconds
Started Aug 27 07:23:26 AM UTC 24
Finished Aug 27 07:23:29 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081435185 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.4081435185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.2790301767
Short name T1330
Test name
Test status
Simulation time 219222495 ps
CPU time 12 seconds
Started Aug 27 07:23:27 AM UTC 24
Finished Aug 27 07:23:40 AM UTC 24
Peak memory 258176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790301767 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.2790301767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.3604880077
Short name T1396
Test name
Test status
Simulation time 4751882116 ps
CPU time 110.49 seconds
Started Aug 27 07:23:25 AM UTC 24
Finished Aug 27 07:25:18 AM UTC 24
Peak memory 1310980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604880077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3604880077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.1162821122
Short name T1358
Test name
Test status
Simulation time 2160607491 ps
CPU time 16.92 seconds
Started Aug 27 07:23:59 AM UTC 24
Finished Aug 27 07:24:17 AM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162821122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1162821122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_override.2364640967
Short name T1321
Test name
Test status
Simulation time 380272364 ps
CPU time 0.99 seconds
Started Aug 27 07:23:25 AM UTC 24
Finished Aug 27 07:23:27 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364640967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2364640967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3926038638
Short name T1441
Test name
Test status
Simulation time 5172083555 ps
CPU time 166.33 seconds
Started Aug 27 07:23:29 AM UTC 24
Finished Aug 27 07:26:19 AM UTC 24
Peak memory 833700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926038638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3926038638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.2075463669
Short name T1328
Test name
Test status
Simulation time 144426133 ps
CPU time 8.13 seconds
Started Aug 27 07:23:29 AM UTC 24
Finished Aug 27 07:23:39 AM UTC 24
Peak memory 237640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075463669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2075463669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.56975487
Short name T1361
Test name
Test status
Simulation time 26594446045 ps
CPU time 56.91 seconds
Started Aug 27 07:23:23 AM UTC 24
Finished Aug 27 07:24:21 AM UTC 24
Peak memory 299240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56975487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.56975487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.263875303
Short name T1339
Test name
Test status
Simulation time 1072384912 ps
CPU time 23.6 seconds
Started Aug 27 07:23:31 AM UTC 24
Finished Aug 27 07:23:55 AM UTC 24
Peak memory 243992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263875303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.263875303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.3585096343
Short name T1344
Test name
Test status
Simulation time 3152862730 ps
CPU time 5.9 seconds
Started Aug 27 07:23:56 AM UTC 24
Finished Aug 27 07:24:03 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3585096343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_ad
dr.3585096343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.135746332
Short name T1340
Test name
Test status
Simulation time 993798490 ps
CPU time 2.83 seconds
Started Aug 27 07:23:53 AM UTC 24
Finished Aug 27 07:23:56 AM UTC 24
Peak memory 216540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357463
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.135746332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.566210647
Short name T1338
Test name
Test status
Simulation time 171600013 ps
CPU time 1.61 seconds
Started Aug 27 07:23:53 AM UTC 24
Finished Aug 27 07:23:55 AM UTC 24
Peak memory 214432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5662106
47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.566210647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.3086630405
Short name T1348
Test name
Test status
Simulation time 1723853222 ps
CPU time 4.01 seconds
Started Aug 27 07:24:01 AM UTC 24
Finished Aug 27 07:24:06 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086630
405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar
ks_acq.3086630405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1608813694
Short name T1346
Test name
Test status
Simulation time 705688123 ps
CPU time 1.87 seconds
Started Aug 27 07:24:02 AM UTC 24
Finished Aug 27 07:24:05 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608813
694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.1608813694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.2714739708
Short name T1334
Test name
Test status
Simulation time 1318640897 ps
CPU time 5.32 seconds
Started Aug 27 07:23:44 AM UTC 24
Finished Aug 27 07:23:51 AM UTC 24
Peak memory 228876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271473
9708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.2714739708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.2532127761
Short name T1563
Test name
Test status
Simulation time 21769539369 ps
CPU time 317.66 seconds
Started Aug 27 07:23:47 AM UTC 24
Finished Aug 27 07:29:10 AM UTC 24
Peak memory 5490836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2532127761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stres
s_wr.2532127761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.4123579602
Short name T1355
Test name
Test status
Simulation time 2329244225 ps
CPU time 4.17 seconds
Started Aug 27 07:24:06 AM UTC 24
Finished Aug 27 07:24:11 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123579
602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.4123579602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3548756470
Short name T1353
Test name
Test status
Simulation time 3672126605 ps
CPU time 3.15 seconds
Started Aug 27 07:24:06 AM UTC 24
Finished Aug 27 07:24:10 AM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548756
470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_ad
dr.3548756470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_nack_txstretch.2315938443
Short name T1354
Test name
Test status
Simulation time 1480701934 ps
CPU time 2.54 seconds
Started Aug 27 07:24:07 AM UTC 24
Finished Aug 27 07:24:10 AM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315938
443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_txstretch.2315938443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_perf.3578802748
Short name T1343
Test name
Test status
Simulation time 1284501055 ps
CPU time 7.37 seconds
Started Aug 27 07:23:54 AM UTC 24
Finished Aug 27 07:24:02 AM UTC 24
Peak memory 233256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578802
748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.3578802748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.3465535181
Short name T1350
Test name
Test status
Simulation time 422739232 ps
CPU time 4.01 seconds
Started Aug 27 07:24:04 AM UTC 24
Finished Aug 27 07:24:09 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465535
181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.3465535181
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.925722829
Short name T1352
Test name
Test status
Simulation time 3764792191 ps
CPU time 31.58 seconds
Started Aug 27 07:23:37 AM UTC 24
Finished Aug 27 07:24:10 AM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925722829 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.925722829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.1034786666
Short name T1425
Test name
Test status
Simulation time 22129985784 ps
CPU time 117.06 seconds
Started Aug 27 07:23:55 AM UTC 24
Finished Aug 27 07:25:54 AM UTC 24
Peak memory 948384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103478
6666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.1034786666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.605620116
Short name T1345
Test name
Test status
Simulation time 2846277983 ps
CPU time 23.53 seconds
Started Aug 27 07:23:40 AM UTC 24
Finished Aug 27 07:24:05 AM UTC 24
Peak memory 226844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605620116 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.605620116
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.521385956
Short name T1733
Test name
Test status
Simulation time 45997765379 ps
CPU time 642.15 seconds
Started Aug 27 07:23:40 AM UTC 24
Finished Aug 27 07:34:29 AM UTC 24
Peak memory 6615200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521385956 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.521385956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.195098825
Short name T1335
Test name
Test status
Simulation time 3136687296 ps
CPU time 9.55 seconds
Started Aug 27 07:23:41 AM UTC 24
Finished Aug 27 07:23:52 AM UTC 24
Peak memory 374932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195098825 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.195098825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.4266856806
Short name T1342
Test name
Test status
Simulation time 1393580787 ps
CPU time 7.24 seconds
Started Aug 27 07:23:50 AM UTC 24
Finished Aug 27 07:23:59 AM UTC 24
Peak memory 226796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266856
806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.4266856806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.3903789386
Short name T1349
Test name
Test status
Simulation time 235174388 ps
CPU time 3.67 seconds
Started Aug 27 07:24:03 AM UTC 24
Finished Aug 27 07:24:08 AM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903789
386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3903789386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_alert_test.3202166648
Short name T1386
Test name
Test status
Simulation time 18693752 ps
CPU time 0.91 seconds
Started Aug 27 07:25:05 AM UTC 24
Finished Aug 27 07:25:07 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202166648 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3202166648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2834339006
Short name T1363
Test name
Test status
Simulation time 64498026 ps
CPU time 2.3 seconds
Started Aug 27 07:24:22 AM UTC 24
Finished Aug 27 07:24:25 AM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834339006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2834339006
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.2747653012
Short name T1365
Test name
Test status
Simulation time 1020539588 ps
CPU time 20.23 seconds
Started Aug 27 07:24:11 AM UTC 24
Finished Aug 27 07:24:33 AM UTC 24
Peak memory 286916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747653012 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.2747653012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.1344801158
Short name T1400
Test name
Test status
Simulation time 6628752869 ps
CPU time 67.38 seconds
Started Aug 27 07:24:12 AM UTC 24
Finished Aug 27 07:25:21 AM UTC 24
Peak memory 395540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344801158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1344801158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.1470332278
Short name T1380
Test name
Test status
Simulation time 7433319957 ps
CPU time 51.41 seconds
Started Aug 27 07:24:10 AM UTC 24
Finished Aug 27 07:25:03 AM UTC 24
Peak memory 592332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470332278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1470332278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.2869177391
Short name T1357
Test name
Test status
Simulation time 664485078 ps
CPU time 1.93 seconds
Started Aug 27 07:24:10 AM UTC 24
Finished Aug 27 07:24:13 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869177391 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.2869177391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.3444194777
Short name T1360
Test name
Test status
Simulation time 1746058053 ps
CPU time 8.33 seconds
Started Aug 27 07:24:12 AM UTC 24
Finished Aug 27 07:24:21 AM UTC 24
Peak memory 246052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444194777 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.3444194777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.1262975281
Short name T1398
Test name
Test status
Simulation time 12675712879 ps
CPU time 66.91 seconds
Started Aug 27 07:24:10 AM UTC 24
Finished Aug 27 07:25:19 AM UTC 24
Peak memory 958668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262975281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1262975281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.1617308343
Short name T1397
Test name
Test status
Simulation time 1480394203 ps
CPU time 18.42 seconds
Started Aug 27 07:24:58 AM UTC 24
Finished Aug 27 07:25:18 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617308343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1617308343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.154820580
Short name T1384
Test name
Test status
Simulation time 466996155 ps
CPU time 5.06 seconds
Started Aug 27 07:24:58 AM UTC 24
Finished Aug 27 07:25:05 AM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154820580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.154820580
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_override.2575847396
Short name T1356
Test name
Test status
Simulation time 78444385 ps
CPU time 1.05 seconds
Started Aug 27 07:24:09 AM UTC 24
Finished Aug 27 07:24:11 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575847396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2575847396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1532124911
Short name T1727
Test name
Test status
Simulation time 28662647113 ps
CPU time 576.11 seconds
Started Aug 27 07:24:14 AM UTC 24
Finished Aug 27 07:33:56 AM UTC 24
Peak memory 3084708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532124911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1532124911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.4096355826
Short name T1359
Test name
Test status
Simulation time 114999683 ps
CPU time 1.49 seconds
Started Aug 27 07:24:18 AM UTC 24
Finished Aug 27 07:24:20 AM UTC 24
Peak memory 236596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096355826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.4096355826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.1046669253
Short name T1367
Test name
Test status
Simulation time 12221848114 ps
CPU time 35.74 seconds
Started Aug 27 07:24:09 AM UTC 24
Finished Aug 27 07:24:46 AM UTC 24
Peak memory 446924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046669253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1046669253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.2085011712
Short name T1394
Test name
Test status
Simulation time 1093133674 ps
CPU time 49.88 seconds
Started Aug 27 07:24:22 AM UTC 24
Finished Aug 27 07:25:13 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085011712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2085011712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.4288935378
Short name T1383
Test name
Test status
Simulation time 1371547011 ps
CPU time 10.33 seconds
Started Aug 27 07:24:52 AM UTC 24
Finished Aug 27 07:25:04 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4288935378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_ad
dr.4288935378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.1682120392
Short name T1372
Test name
Test status
Simulation time 316788282 ps
CPU time 2.09 seconds
Started Aug 27 07:24:48 AM UTC 24
Finished Aug 27 07:24:51 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682120
392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.1682120392
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.2977967669
Short name T1373
Test name
Test status
Simulation time 202952284 ps
CPU time 1.24 seconds
Started Aug 27 07:24:49 AM UTC 24
Finished Aug 27 07:24:51 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977967
669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.2977967669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.1063947533
Short name T1379
Test name
Test status
Simulation time 229916542 ps
CPU time 2.24 seconds
Started Aug 27 07:25:00 AM UTC 24
Finished Aug 27 07:25:03 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063947
533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermar
ks_acq.1063947533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.303188931
Short name T1381
Test name
Test status
Simulation time 134366458 ps
CPU time 1.98 seconds
Started Aug 27 07:25:01 AM UTC 24
Finished Aug 27 07:25:04 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031889
31 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks
_tx.303188931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.4025484092
Short name T1375
Test name
Test status
Simulation time 1158906602 ps
CPU time 3.57 seconds
Started Aug 27 07:24:52 AM UTC 24
Finished Aug 27 07:24:57 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025484
092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_hrst.4025484092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.361795044
Short name T1369
Test name
Test status
Simulation time 915614066 ps
CPU time 8.14 seconds
Started Aug 27 07:24:37 AM UTC 24
Finished Aug 27 07:24:47 AM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361795
044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.361795044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.3139830067
Short name T1382
Test name
Test status
Simulation time 19600314111 ps
CPU time 18.14 seconds
Started Aug 27 07:24:45 AM UTC 24
Finished Aug 27 07:25:04 AM UTC 24
Peak memory 320024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3139830067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres
s_wr.3139830067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.4254941845
Short name T1390
Test name
Test status
Simulation time 3825217271 ps
CPU time 4.7 seconds
Started Aug 27 07:25:04 AM UTC 24
Finished Aug 27 07:25:10 AM UTC 24
Peak memory 226632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254941
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.4254941845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.2126957431
Short name T1392
Test name
Test status
Simulation time 2144816922 ps
CPU time 4.45 seconds
Started Aug 27 07:25:05 AM UTC 24
Finished Aug 27 07:25:11 AM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126957
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_ad
dr.2126957431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.2322773481
Short name T1389
Test name
Test status
Simulation time 575114815 ps
CPU time 2.33 seconds
Started Aug 27 07:25:05 AM UTC 24
Finished Aug 27 07:25:09 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322773
481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.2322773481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_perf.3608911419
Short name T1376
Test name
Test status
Simulation time 4892619115 ps
CPU time 7.2 seconds
Started Aug 27 07:24:50 AM UTC 24
Finished Aug 27 07:24:58 AM UTC 24
Peak memory 233788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608911
419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.3608911419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.3910986970
Short name T1388
Test name
Test status
Simulation time 510773201 ps
CPU time 3.51 seconds
Started Aug 27 07:25:04 AM UTC 24
Finished Aug 27 07:25:08 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910986
970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.3910986970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.1726677802
Short name T1370
Test name
Test status
Simulation time 8871191749 ps
CPU time 22.23 seconds
Started Aug 27 07:24:25 AM UTC 24
Finished Aug 27 07:24:49 AM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726677802 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.1726677802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.3734999012
Short name T1520
Test name
Test status
Simulation time 51206392834 ps
CPU time 186.11 seconds
Started Aug 27 07:24:52 AM UTC 24
Finished Aug 27 07:28:02 AM UTC 24
Peak memory 1430000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373499
9012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.3734999012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.1043343463
Short name T1371
Test name
Test status
Simulation time 315175835 ps
CPU time 16.1 seconds
Started Aug 27 07:24:30 AM UTC 24
Finished Aug 27 07:24:50 AM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043343463 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.1043343463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.1840777662
Short name T1490
Test name
Test status
Simulation time 35140547640 ps
CPU time 175.21 seconds
Started Aug 27 07:24:26 AM UTC 24
Finished Aug 27 07:27:24 AM UTC 24
Peak memory 2759064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840777662 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.1840777662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.3657638933
Short name T1366
Test name
Test status
Simulation time 215963864 ps
CPU time 2.5 seconds
Started Aug 27 07:24:33 AM UTC 24
Finished Aug 27 07:24:37 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657638933 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.3657638933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.327058130
Short name T1377
Test name
Test status
Simulation time 4971224943 ps
CPU time 11.37 seconds
Started Aug 27 07:24:47 AM UTC 24
Finished Aug 27 07:24:59 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270581
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.327058130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.597108501
Short name T1385
Test name
Test status
Simulation time 59732570 ps
CPU time 2.24 seconds
Started Aug 27 07:25:04 AM UTC 24
Finished Aug 27 07:25:07 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5971085
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.597108501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_alert_test.2774532089
Short name T360
Test name
Test status
Simulation time 26494269 ps
CPU time 0.97 seconds
Started Aug 27 07:04:48 AM UTC 24
Finished Aug 27 07:04:50 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774532089 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2774532089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.3387787259
Short name T27
Test name
Test status
Simulation time 342341131 ps
CPU time 1.6 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:37 AM UTC 24
Peak memory 232556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387787259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3387787259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.2976468641
Short name T51
Test name
Test status
Simulation time 789553857 ps
CPU time 9.81 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:45 AM UTC 24
Peak memory 248080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976468641 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.2976468641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.1970456129
Short name T168
Test name
Test status
Simulation time 1911326446 ps
CPU time 49.22 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:05:25 AM UTC 24
Peak memory 301388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970456129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1970456129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.3592149586
Short name T111
Test name
Test status
Simulation time 2945276513 ps
CPU time 75.87 seconds
Started Aug 27 07:04:33 AM UTC 24
Finished Aug 27 07:05:51 AM UTC 24
Peak memory 489772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592149586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3592149586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.3693104852
Short name T255
Test name
Test status
Simulation time 150731446 ps
CPU time 1.72 seconds
Started Aug 27 07:04:33 AM UTC 24
Finished Aug 27 07:04:36 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693104852 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.3693104852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.1900594405
Short name T165
Test name
Test status
Simulation time 1952415018 ps
CPU time 11 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:46 AM UTC 24
Peak memory 251940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900594405 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.1900594405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.1471191980
Short name T521
Test name
Test status
Simulation time 3775322710 ps
CPU time 202.45 seconds
Started Aug 27 07:04:33 AM UTC 24
Finished Aug 27 07:07:59 AM UTC 24
Peak memory 1114316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471191980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1471191980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_override.2042570379
Short name T151
Test name
Test status
Simulation time 46923145 ps
CPU time 1 seconds
Started Aug 27 07:04:33 AM UTC 24
Finished Aug 27 07:04:35 AM UTC 24
Peak memory 215096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042570379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2042570379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_perf.2011076071
Short name T344
Test name
Test status
Simulation time 326168952 ps
CPU time 3.64 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:39 AM UTC 24
Peak memory 251992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011076071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2011076071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.3247934555
Short name T343
Test name
Test status
Simulation time 311247489 ps
CPU time 3.06 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:38 AM UTC 24
Peak memory 241628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247934555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.3247934555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.3982061919
Short name T365
Test name
Test status
Simulation time 858832742 ps
CPU time 21.35 seconds
Started Aug 27 07:04:31 AM UTC 24
Finished Aug 27 07:04:54 AM UTC 24
Peak memory 313548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982061919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3982061919
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.559201339
Short name T204
Test name
Test status
Simulation time 1435845844 ps
CPU time 11.16 seconds
Started Aug 27 07:04:34 AM UTC 24
Finished Aug 27 07:04:47 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559201339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.559201339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.667062039
Short name T207
Test name
Test status
Simulation time 188565030 ps
CPU time 1.42 seconds
Started Aug 27 07:04:48 AM UTC 24
Finished Aug 27 07:04:50 AM UTC 24
Peak memory 246792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667062039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.667062039
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.146662614
Short name T356
Test name
Test status
Simulation time 1432108518 ps
CPU time 7.1 seconds
Started Aug 27 07:04:40 AM UTC 24
Finished Aug 27 07:04:49 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=146662614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.146662614
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.2498343909
Short name T346
Test name
Test status
Simulation time 199185696 ps
CPU time 2.18 seconds
Started Aug 27 07:04:38 AM UTC 24
Finished Aug 27 07:04:41 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498343
909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.2498343909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.3940081949
Short name T345
Test name
Test status
Simulation time 747633636 ps
CPU time 1.83 seconds
Started Aug 27 07:04:38 AM UTC 24
Finished Aug 27 07:04:41 AM UTC 24
Peak memory 226564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940081
949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.3940081949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.686190013
Short name T355
Test name
Test status
Simulation time 321208322 ps
CPU time 2.56 seconds
Started Aug 27 07:04:44 AM UTC 24
Finished Aug 27 07:04:48 AM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6861900
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_acq.686190013
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.3838825305
Short name T357
Test name
Test status
Simulation time 205730963 ps
CPU time 1.71 seconds
Started Aug 27 07:04:46 AM UTC 24
Finished Aug 27 07:04:49 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838825
305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.3838825305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_hrst.2927959857
Short name T349
Test name
Test status
Simulation time 617231996 ps
CPU time 3.51 seconds
Started Aug 27 07:04:40 AM UTC 24
Finished Aug 27 07:04:45 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927959
857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.2927959857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.1444091139
Short name T352
Test name
Test status
Simulation time 724762567 ps
CPU time 8.46 seconds
Started Aug 27 07:04:37 AM UTC 24
Finished Aug 27 07:04:46 AM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144409
1139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.1444091139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.3570199362
Short name T62
Test name
Test status
Simulation time 11578356247 ps
CPU time 59.95 seconds
Started Aug 27 07:04:37 AM UTC 24
Finished Aug 27 07:05:38 AM UTC 24
Peak memory 1259928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3570199362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress
_wr.3570199362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.1167835255
Short name T363
Test name
Test status
Simulation time 489501751 ps
CPU time 3.46 seconds
Started Aug 27 07:04:47 AM UTC 24
Finished Aug 27 07:04:51 AM UTC 24
Peak memory 226736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167835
255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.1167835255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.809426814
Short name T364
Test name
Test status
Simulation time 2196370656 ps
CPU time 5.15 seconds
Started Aug 27 07:04:47 AM UTC 24
Finished Aug 27 07:04:53 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8094268
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.809426814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.3481296594
Short name T187
Test name
Test status
Simulation time 276176873 ps
CPU time 2.21 seconds
Started Aug 27 07:04:47 AM UTC 24
Finished Aug 27 07:04:50 AM UTC 24
Peak memory 233568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481296
594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.3481296594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_perf.2195137722
Short name T358
Test name
Test status
Simulation time 820141656 ps
CPU time 8.51 seconds
Started Aug 27 07:04:39 AM UTC 24
Finished Aug 27 07:04:49 AM UTC 24
Peak memory 231176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195137
722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.2195137722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.3091066163
Short name T359
Test name
Test status
Simulation time 369089768 ps
CPU time 2.64 seconds
Started Aug 27 07:04:46 AM UTC 24
Finished Aug 27 07:04:49 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091066
163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.3091066163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.2906027044
Short name T369
Test name
Test status
Simulation time 1056188815 ps
CPU time 37.95 seconds
Started Aug 27 07:04:35 AM UTC 24
Finished Aug 27 07:05:15 AM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906027044 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.2906027044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.3885501886
Short name T199
Test name
Test status
Simulation time 85488853642 ps
CPU time 129.7 seconds
Started Aug 27 07:04:39 AM UTC 24
Finished Aug 27 07:06:51 AM UTC 24
Peak memory 1485256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388550
1886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.3885501886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2375888663
Short name T179
Test name
Test status
Simulation time 25578769246 ps
CPU time 29.47 seconds
Started Aug 27 07:04:35 AM UTC 24
Finished Aug 27 07:05:06 AM UTC 24
Peak memory 244240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375888663 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2375888663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.4239219629
Short name T348
Test name
Test status
Simulation time 26457166774 ps
CPU time 7.21 seconds
Started Aug 27 07:04:35 AM UTC 24
Finished Aug 27 07:04:44 AM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239219629 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.4239219629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.1439669393
Short name T350
Test name
Test status
Simulation time 2424638374 ps
CPU time 7.14 seconds
Started Aug 27 07:04:37 AM UTC 24
Finished Aug 27 07:04:45 AM UTC 24
Peak memory 334280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439669393 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.1439669393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1563510335
Short name T354
Test name
Test status
Simulation time 2638315839 ps
CPU time 9.89 seconds
Started Aug 27 07:04:37 AM UTC 24
Finished Aug 27 07:04:48 AM UTC 24
Peak memory 233276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563510
335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.1563510335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2618602900
Short name T362
Test name
Test status
Simulation time 243953859 ps
CPU time 4.55 seconds
Started Aug 27 07:04:46 AM UTC 24
Finished Aug 27 07:04:51 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618602
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2618602900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_alert_test.1756971682
Short name T1416
Test name
Test status
Simulation time 18093978 ps
CPU time 0.95 seconds
Started Aug 27 07:25:44 AM UTC 24
Finished Aug 27 07:25:46 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756971682 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1756971682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.415429604
Short name T1401
Test name
Test status
Simulation time 164191706 ps
CPU time 4.49 seconds
Started Aug 27 07:25:18 AM UTC 24
Finished Aug 27 07:25:24 AM UTC 24
Peak memory 247912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415429604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.415429604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.581143849
Short name T1403
Test name
Test status
Simulation time 291604851 ps
CPU time 15.54 seconds
Started Aug 27 07:25:10 AM UTC 24
Finished Aug 27 07:25:26 AM UTC 24
Peak memory 276748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581143849 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.581143849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.1915300989
Short name T1488
Test name
Test status
Simulation time 7216991630 ps
CPU time 130.27 seconds
Started Aug 27 07:25:11 AM UTC 24
Finished Aug 27 07:27:24 AM UTC 24
Peak memory 835860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915300989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1915300989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.2166987083
Short name T1432
Test name
Test status
Simulation time 2118981744 ps
CPU time 55.56 seconds
Started Aug 27 07:25:08 AM UTC 24
Finished Aug 27 07:26:06 AM UTC 24
Peak memory 731220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166987083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2166987083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.2497182391
Short name T1393
Test name
Test status
Simulation time 256201644 ps
CPU time 1.25 seconds
Started Aug 27 07:25:10 AM UTC 24
Finished Aug 27 07:25:12 AM UTC 24
Peak memory 215172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497182391 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.2497182391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.1705671337
Short name T1395
Test name
Test status
Simulation time 130175720 ps
CPU time 4.97 seconds
Started Aug 27 07:25:11 AM UTC 24
Finished Aug 27 07:25:17 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705671337 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.1705671337
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.1079503391
Short name T1497
Test name
Test status
Simulation time 5313403696 ps
CPU time 144.34 seconds
Started Aug 27 07:25:08 AM UTC 24
Finished Aug 27 07:27:35 AM UTC 24
Peak memory 1603784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079503391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1079503391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.255846375
Short name T267
Test name
Test status
Simulation time 2109349102 ps
CPU time 9.1 seconds
Started Aug 27 07:25:39 AM UTC 24
Finished Aug 27 07:25:50 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255846375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.255846375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_override.2448778299
Short name T1391
Test name
Test status
Simulation time 46300883 ps
CPU time 0.87 seconds
Started Aug 27 07:25:08 AM UTC 24
Finished Aug 27 07:25:10 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448778299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2448778299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_perf.104935026
Short name T1749
Test name
Test status
Simulation time 25172353578 ps
CPU time 893.93 seconds
Started Aug 27 07:25:12 AM UTC 24
Finished Aug 27 07:40:16 AM UTC 24
Peak memory 374984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104935026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.104935026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.2876011302
Short name T1410
Test name
Test status
Simulation time 1854086940 ps
CPU time 23.44 seconds
Started Aug 27 07:25:13 AM UTC 24
Finished Aug 27 07:25:38 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876011302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.2876011302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.1783614023
Short name T1424
Test name
Test status
Simulation time 21135449418 ps
CPU time 47.05 seconds
Started Aug 27 07:25:05 AM UTC 24
Finished Aug 27 07:25:54 AM UTC 24
Peak memory 346336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783614023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1783614023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.2052545774
Short name T1406
Test name
Test status
Simulation time 1017358795 ps
CPU time 18.26 seconds
Started Aug 27 07:25:14 AM UTC 24
Finished Aug 27 07:25:34 AM UTC 24
Peak memory 232960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052545774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2052545774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.2717701192
Short name T1341
Test name
Test status
Simulation time 1161338656 ps
CPU time 6.72 seconds
Started Aug 27 07:25:35 AM UTC 24
Finished Aug 27 07:25:43 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2717701192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_ad
dr.2717701192
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.2062165747
Short name T1407
Test name
Test status
Simulation time 467713841 ps
CPU time 2.45 seconds
Started Aug 27 07:25:30 AM UTC 24
Finished Aug 27 07:25:34 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062165
747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.2062165747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.68775416
Short name T1408
Test name
Test status
Simulation time 1546724544 ps
CPU time 2.02 seconds
Started Aug 27 07:25:32 AM UTC 24
Finished Aug 27 07:25:35 AM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6877541
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.68775416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.2622125668
Short name T1414
Test name
Test status
Simulation time 323938183 ps
CPU time 3.07 seconds
Started Aug 27 07:25:39 AM UTC 24
Finished Aug 27 07:25:44 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622125
668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermar
ks_acq.2622125668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.1001610102
Short name T1415
Test name
Test status
Simulation time 132830335 ps
CPU time 1.85 seconds
Started Aug 27 07:25:41 AM UTC 24
Finished Aug 27 07:25:44 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001610
102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_tx.1001610102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_hrst.1620360114
Short name T1413
Test name
Test status
Simulation time 573611085 ps
CPU time 3.43 seconds
Started Aug 27 07:25:36 AM UTC 24
Finished Aug 27 07:25:41 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620360
114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_hrst.1620360114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.2874914090
Short name T1404
Test name
Test status
Simulation time 2020962605 ps
CPU time 4.44 seconds
Started Aug 27 07:25:24 AM UTC 24
Finished Aug 27 07:25:29 AM UTC 24
Peak memory 233508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287491
4090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.2874914090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.2681069691
Short name T1435
Test name
Test status
Simulation time 30755328785 ps
CPU time 43.41 seconds
Started Aug 27 07:25:25 AM UTC 24
Finished Aug 27 07:26:10 AM UTC 24
Peak memory 823496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2681069691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stres
s_wr.2681069691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.1882392162
Short name T1420
Test name
Test status
Simulation time 2163706083 ps
CPU time 5.28 seconds
Started Aug 27 07:25:42 AM UTC 24
Finished Aug 27 07:25:49 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882392
162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.1882392162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.3198695793
Short name T56
Test name
Test status
Simulation time 1523188203 ps
CPU time 3.4 seconds
Started Aug 27 07:25:44 AM UTC 24
Finished Aug 27 07:25:49 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198695
793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.3198695793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.1594391749
Short name T1417
Test name
Test status
Simulation time 164416442 ps
CPU time 1.74 seconds
Started Aug 27 07:25:44 AM UTC 24
Finished Aug 27 07:25:47 AM UTC 24
Peak memory 232584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594391
749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.1594391749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_perf.3831231742
Short name T1412
Test name
Test status
Simulation time 1347713302 ps
CPU time 5.11 seconds
Started Aug 27 07:25:33 AM UTC 24
Finished Aug 27 07:25:39 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831231
742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.3831231742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.3133890271
Short name T1418
Test name
Test status
Simulation time 395140813 ps
CPU time 4.13 seconds
Started Aug 27 07:25:42 AM UTC 24
Finished Aug 27 07:25:48 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133890
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.3133890271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.4223531577
Short name T1426
Test name
Test status
Simulation time 1816105294 ps
CPU time 32.18 seconds
Started Aug 27 07:25:19 AM UTC 24
Finished Aug 27 07:25:55 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223531577 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.4223531577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.2661637531
Short name T1466
Test name
Test status
Simulation time 35223584243 ps
CPU time 66.93 seconds
Started Aug 27 07:25:34 AM UTC 24
Finished Aug 27 07:26:43 AM UTC 24
Peak memory 555336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266163
7531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.2661637531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.2725546433
Short name T1422
Test name
Test status
Simulation time 1368180828 ps
CPU time 27.74 seconds
Started Aug 27 07:25:23 AM UTC 24
Finished Aug 27 07:25:52 AM UTC 24
Peak memory 244004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725546433 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.2725546433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.988702663
Short name T1478
Test name
Test status
Simulation time 35465992174 ps
CPU time 111.44 seconds
Started Aug 27 07:25:19 AM UTC 24
Finished Aug 27 07:27:15 AM UTC 24
Peak memory 2089048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988702663 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.988702663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.2920120386
Short name T1405
Test name
Test status
Simulation time 1142592256 ps
CPU time 8.61 seconds
Started Aug 27 07:25:23 AM UTC 24
Finished Aug 27 07:25:32 AM UTC 24
Peak memory 287004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920120386 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.2920120386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.1078127138
Short name T1411
Test name
Test status
Simulation time 1466825326 ps
CPU time 12.13 seconds
Started Aug 27 07:25:25 AM UTC 24
Finished Aug 27 07:25:38 AM UTC 24
Peak memory 233604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078127
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.1078127138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3888811596
Short name T1419
Test name
Test status
Simulation time 222414391 ps
CPU time 6.59 seconds
Started Aug 27 07:25:41 AM UTC 24
Finished Aug 27 07:25:49 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888811
596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3888811596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_alert_test.4075325090
Short name T1457
Test name
Test status
Simulation time 16157859 ps
CPU time 0.96 seconds
Started Aug 27 07:26:26 AM UTC 24
Finished Aug 27 07:26:28 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075325090 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.4075325090
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.172036380
Short name T1430
Test name
Test status
Simulation time 304168647 ps
CPU time 5.07 seconds
Started Aug 27 07:25:55 AM UTC 24
Finished Aug 27 07:26:01 AM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172036380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.172036380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.3837955516
Short name T1427
Test name
Test status
Simulation time 253152741 ps
CPU time 5.6 seconds
Started Aug 27 07:25:50 AM UTC 24
Finished Aug 27 07:25:56 AM UTC 24
Peak memory 270476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837955516 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.3837955516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.1306959694
Short name T1537
Test name
Test status
Simulation time 7104164495 ps
CPU time 151.58 seconds
Started Aug 27 07:25:52 AM UTC 24
Finished Aug 27 07:28:26 AM UTC 24
Peak memory 637140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306959694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1306959694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.1144175715
Short name T1486
Test name
Test status
Simulation time 1302903665 ps
CPU time 91.23 seconds
Started Aug 27 07:25:50 AM UTC 24
Finished Aug 27 07:27:23 AM UTC 24
Peak memory 397460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144175715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1144175715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.823885414
Short name T1423
Test name
Test status
Simulation time 551713204 ps
CPU time 1.93 seconds
Started Aug 27 07:25:50 AM UTC 24
Finished Aug 27 07:25:53 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823885414 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.823885414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.2738930835
Short name T1429
Test name
Test status
Simulation time 139787534 ps
CPU time 9.02 seconds
Started Aug 27 07:25:51 AM UTC 24
Finished Aug 27 07:26:01 AM UTC 24
Peak memory 241996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738930835 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.2738930835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.1781757446
Short name T1527
Test name
Test status
Simulation time 9534740409 ps
CPU time 135.27 seconds
Started Aug 27 07:25:49 AM UTC 24
Finished Aug 27 07:28:06 AM UTC 24
Peak memory 1433820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781757446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1781757446
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.4093399320
Short name T1454
Test name
Test status
Simulation time 1201334070 ps
CPU time 6.52 seconds
Started Aug 27 07:26:20 AM UTC 24
Finished Aug 27 07:26:27 AM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093399320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.4093399320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_mode_toggle.1319854865
Short name T1447
Test name
Test status
Simulation time 347923051 ps
CPU time 3.69 seconds
Started Aug 27 07:26:17 AM UTC 24
Finished Aug 27 07:26:21 AM UTC 24
Peak memory 233572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319854865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1319854865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_override.1966815449
Short name T1421
Test name
Test status
Simulation time 82998374 ps
CPU time 1.08 seconds
Started Aug 27 07:25:49 AM UTC 24
Finished Aug 27 07:25:51 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966815449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1966815449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_perf.440466159
Short name T1431
Test name
Test status
Simulation time 360230064 ps
CPU time 8.94 seconds
Started Aug 27 07:25:53 AM UTC 24
Finished Aug 27 07:26:03 AM UTC 24
Peak memory 241764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440466159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.440466159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.1646295856
Short name T1428
Test name
Test status
Simulation time 105999264 ps
CPU time 2.23 seconds
Started Aug 27 07:25:54 AM UTC 24
Finished Aug 27 07:25:57 AM UTC 24
Peak memory 239248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646295856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.1646295856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.2239914174
Short name T1468
Test name
Test status
Simulation time 2453726206 ps
CPU time 61.37 seconds
Started Aug 27 07:25:47 AM UTC 24
Finished Aug 27 07:26:50 AM UTC 24
Peak memory 327904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239914174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2239914174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.943830069
Short name T1433
Test name
Test status
Simulation time 1133485396 ps
CPU time 11.59 seconds
Started Aug 27 07:25:54 AM UTC 24
Finished Aug 27 07:26:07 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943830069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.943830069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.2283046294
Short name T1448
Test name
Test status
Simulation time 922807978 ps
CPU time 7.35 seconds
Started Aug 27 07:26:14 AM UTC 24
Finished Aug 27 07:26:23 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2283046294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad
dr.2283046294
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.4133517196
Short name T1437
Test name
Test status
Simulation time 211116567 ps
CPU time 1.52 seconds
Started Aug 27 07:26:10 AM UTC 24
Finished Aug 27 07:26:13 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133517
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.4133517196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.2535888752
Short name T1440
Test name
Test status
Simulation time 410687632 ps
CPU time 1.05 seconds
Started Aug 27 07:26:12 AM UTC 24
Finished Aug 27 07:26:14 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535888
752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.2535888752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.113033338
Short name T1450
Test name
Test status
Simulation time 1927748867 ps
CPU time 3.12 seconds
Started Aug 27 07:26:21 AM UTC 24
Finished Aug 27 07:26:25 AM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130333
38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_acq.113033338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.1007475108
Short name T1452
Test name
Test status
Simulation time 315515436 ps
CPU time 2.17 seconds
Started Aug 27 07:26:22 AM UTC 24
Finished Aug 27 07:26:25 AM UTC 24
Peak memory 216188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007475
108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_tx.1007475108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.110532319
Short name T1444
Test name
Test status
Simulation time 377176791 ps
CPU time 4.19 seconds
Started Aug 27 07:26:16 AM UTC 24
Finished Aug 27 07:26:21 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105323
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.110532319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.241687409
Short name T1436
Test name
Test status
Simulation time 1412633477 ps
CPU time 6.2 seconds
Started Aug 27 07:26:04 AM UTC 24
Finished Aug 27 07:26:11 AM UTC 24
Peak memory 233160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241687
409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.241687409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.330064625
Short name T1576
Test name
Test status
Simulation time 14317006640 ps
CPU time 216.63 seconds
Started Aug 27 07:26:07 AM UTC 24
Finished Aug 27 07:29:47 AM UTC 24
Peak memory 3539160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=330064625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress
_wr.330064625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.2759818563
Short name T1455
Test name
Test status
Simulation time 445421133 ps
CPU time 4.21 seconds
Started Aug 27 07:26:22 AM UTC 24
Finished Aug 27 07:26:27 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759818
563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.2759818563
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.2085605954
Short name T1459
Test name
Test status
Simulation time 491979983 ps
CPU time 3.98 seconds
Started Aug 27 07:26:24 AM UTC 24
Finished Aug 27 07:26:29 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085605
954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_ad
dr.2085605954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.4048215520
Short name T1456
Test name
Test status
Simulation time 404016770 ps
CPU time 1.94 seconds
Started Aug 27 07:26:25 AM UTC 24
Finished Aug 27 07:26:28 AM UTC 24
Peak memory 232568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048215
520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.4048215520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_perf.1382060551
Short name T1446
Test name
Test status
Simulation time 1094775146 ps
CPU time 7.08 seconds
Started Aug 27 07:26:13 AM UTC 24
Finished Aug 27 07:26:21 AM UTC 24
Peak memory 233376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382060
551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.1382060551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.3581722944
Short name T1453
Test name
Test status
Simulation time 1629177480 ps
CPU time 3.11 seconds
Started Aug 27 07:26:22 AM UTC 24
Finished Aug 27 07:26:26 AM UTC 24
Peak memory 216120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581722
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.3581722944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.1775216792
Short name T1439
Test name
Test status
Simulation time 1851967748 ps
CPU time 14.95 seconds
Started Aug 27 07:25:57 AM UTC 24
Finished Aug 27 07:26:14 AM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775216792 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.1775216792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2805342006
Short name T1735
Test name
Test status
Simulation time 124330083667 ps
CPU time 495.51 seconds
Started Aug 27 07:26:14 AM UTC 24
Finished Aug 27 07:34:35 AM UTC 24
Peak memory 4114592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280534
2006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.2805342006
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.1415544960
Short name T1443
Test name
Test status
Simulation time 1982057313 ps
CPU time 17.68 seconds
Started Aug 27 07:26:02 AM UTC 24
Finished Aug 27 07:26:20 AM UTC 24
Peak memory 233668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415544960 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.1415544960
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.840870632
Short name T1461
Test name
Test status
Simulation time 34459913044 ps
CPU time 31.43 seconds
Started Aug 27 07:25:59 AM UTC 24
Finished Aug 27 07:26:31 AM UTC 24
Peak memory 579800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840870632 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.840870632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.2625177489
Short name T1434
Test name
Test status
Simulation time 1101105921 ps
CPU time 5.66 seconds
Started Aug 27 07:26:03 AM UTC 24
Finished Aug 27 07:26:09 AM UTC 24
Peak memory 256140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625177489 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.2625177489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.1013979621
Short name T1442
Test name
Test status
Simulation time 6115573300 ps
CPU time 10.79 seconds
Started Aug 27 07:26:08 AM UTC 24
Finished Aug 27 07:26:20 AM UTC 24
Peak memory 233704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013979
621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.1013979621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_alert_test.3931730487
Short name T1449
Test name
Test status
Simulation time 69633906 ps
CPU time 0.88 seconds
Started Aug 27 07:27:22 AM UTC 24
Finished Aug 27 07:27:25 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931730487 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3931730487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.4221299891
Short name T1464
Test name
Test status
Simulation time 139380072 ps
CPU time 4.03 seconds
Started Aug 27 07:26:35 AM UTC 24
Finished Aug 27 07:26:40 AM UTC 24
Peak memory 230872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221299891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.4221299891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.1135079754
Short name T1463
Test name
Test status
Simulation time 1404158630 ps
CPU time 10.38 seconds
Started Aug 27 07:26:29 AM UTC 24
Finished Aug 27 07:26:40 AM UTC 24
Peak memory 301084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135079754 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.1135079754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.2787552909
Short name T1534
Test name
Test status
Simulation time 6045162745 ps
CPU time 105.02 seconds
Started Aug 27 07:26:30 AM UTC 24
Finished Aug 27 07:28:17 AM UTC 24
Peak memory 635152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787552909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2787552909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.1466017898
Short name T1495
Test name
Test status
Simulation time 1796416991 ps
CPU time 62.63 seconds
Started Aug 27 07:26:29 AM UTC 24
Finished Aug 27 07:27:33 AM UTC 24
Peak memory 632840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466017898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1466017898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.3947645134
Short name T1460
Test name
Test status
Simulation time 105272131 ps
CPU time 1.43 seconds
Started Aug 27 07:26:29 AM UTC 24
Finished Aug 27 07:26:31 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947645134 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.3947645134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.4046842998
Short name T1465
Test name
Test status
Simulation time 169001679 ps
CPU time 11.75 seconds
Started Aug 27 07:26:30 AM UTC 24
Finished Aug 27 07:26:43 AM UTC 24
Peak memory 243780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046842998 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.4046842998
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1821407331
Short name T1541
Test name
Test status
Simulation time 20890195951 ps
CPU time 128.96 seconds
Started Aug 27 07:26:27 AM UTC 24
Finished Aug 27 07:28:39 AM UTC 24
Peak memory 1528216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821407331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1821407331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.3883450644
Short name T1501
Test name
Test status
Simulation time 2326991355 ps
CPU time 21.93 seconds
Started Aug 27 07:27:15 AM UTC 24
Finished Aug 27 07:27:38 AM UTC 24
Peak memory 216972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883450644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3883450644
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_override.336160843
Short name T1458
Test name
Test status
Simulation time 17509832 ps
CPU time 1 seconds
Started Aug 27 07:26:26 AM UTC 24
Finished Aug 27 07:26:28 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336160843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.336160843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2181356513
Short name T1469
Test name
Test status
Simulation time 1069275668 ps
CPU time 22.67 seconds
Started Aug 27 07:26:30 AM UTC 24
Finished Aug 27 07:26:54 AM UTC 24
Peak memory 399512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181356513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2181356513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.1981077179
Short name T1462
Test name
Test status
Simulation time 101361889 ps
CPU time 1.72 seconds
Started Aug 27 07:26:32 AM UTC 24
Finished Aug 27 07:26:35 AM UTC 24
Peak memory 236596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981077179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.1981077179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.4159783319
Short name T1470
Test name
Test status
Simulation time 1967257455 ps
CPU time 27.01 seconds
Started Aug 27 07:26:26 AM UTC 24
Finished Aug 27 07:26:55 AM UTC 24
Peak memory 276572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159783319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4159783319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.1297323843
Short name T1467
Test name
Test status
Simulation time 13578139224 ps
CPU time 15.93 seconds
Started Aug 27 07:26:32 AM UTC 24
Finished Aug 27 07:26:49 AM UTC 24
Peak memory 231152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297323843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1297323843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.407387263
Short name T1480
Test name
Test status
Simulation time 4262015975 ps
CPU time 5.49 seconds
Started Aug 27 07:27:08 AM UTC 24
Finished Aug 27 07:27:16 AM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=407387263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.407387263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.3128374505
Short name T1472
Test name
Test status
Simulation time 4214452908 ps
CPU time 2.06 seconds
Started Aug 27 07:27:02 AM UTC 24
Finished Aug 27 07:27:06 AM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128374
505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.3128374505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.2948906216
Short name T1474
Test name
Test status
Simulation time 607134217 ps
CPU time 2.17 seconds
Started Aug 27 07:27:05 AM UTC 24
Finished Aug 27 07:27:08 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948906
216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.2948906216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1444861935
Short name T1485
Test name
Test status
Simulation time 2671060820 ps
CPU time 6.57 seconds
Started Aug 27 07:27:15 AM UTC 24
Finished Aug 27 07:27:23 AM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444861
935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermar
ks_acq.1444861935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.804975269
Short name T1481
Test name
Test status
Simulation time 237984734 ps
CPU time 1.49 seconds
Started Aug 27 07:27:16 AM UTC 24
Finished Aug 27 07:27:19 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8049752
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks
_tx.804975269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.566099640
Short name T1477
Test name
Test status
Simulation time 457316264 ps
CPU time 3.11 seconds
Started Aug 27 07:27:10 AM UTC 24
Finished Aug 27 07:27:14 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5660996
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.566099640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.1140970353
Short name T1471
Test name
Test status
Simulation time 834354054 ps
CPU time 8.21 seconds
Started Aug 27 07:26:51 AM UTC 24
Finished Aug 27 07:27:00 AM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114097
0353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.1140970353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.697146406
Short name T1511
Test name
Test status
Simulation time 16490356283 ps
CPU time 59.33 seconds
Started Aug 27 07:26:55 AM UTC 24
Finished Aug 27 07:27:56 AM UTC 24
Peak memory 1310936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=697146406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress
_wr.697146406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2688220230
Short name T1489
Test name
Test status
Simulation time 415913187 ps
CPU time 3.71 seconds
Started Aug 27 07:27:19 AM UTC 24
Finished Aug 27 07:27:24 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688220
230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.2688220230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.1990209942
Short name T1492
Test name
Test status
Simulation time 850751022 ps
CPU time 2.76 seconds
Started Aug 27 07:27:22 AM UTC 24
Finished Aug 27 07:27:26 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990209
942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad
dr.1990209942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_nack_txstretch.487788883
Short name T1491
Test name
Test status
Simulation time 169905773 ps
CPU time 2.36 seconds
Started Aug 27 07:27:22 AM UTC 24
Finished Aug 27 07:27:26 AM UTC 24
Peak memory 233804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4877888
83 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_txstretch.487788883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_perf.1447917270
Short name T1476
Test name
Test status
Simulation time 846664369 ps
CPU time 5.73 seconds
Started Aug 27 07:27:06 AM UTC 24
Finished Aug 27 07:27:13 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447917
270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.1447917270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.3604645790
Short name T1482
Test name
Test status
Simulation time 1424869904 ps
CPU time 2.98 seconds
Started Aug 27 07:27:17 AM UTC 24
Finished Aug 27 07:27:21 AM UTC 24
Peak memory 216636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604645
790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.3604645790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1133415619
Short name T1475
Test name
Test status
Simulation time 1919376503 ps
CPU time 29.55 seconds
Started Aug 27 07:26:41 AM UTC 24
Finished Aug 27 07:27:12 AM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133415619 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.1133415619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.749528487
Short name T1536
Test name
Test status
Simulation time 42396523937 ps
CPU time 76.4 seconds
Started Aug 27 07:27:07 AM UTC 24
Finished Aug 27 07:28:26 AM UTC 24
Peak memory 811248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749528
487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.749528487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.963814227
Short name T1500
Test name
Test status
Simulation time 6530681898 ps
CPU time 52.8 seconds
Started Aug 27 07:26:44 AM UTC 24
Finished Aug 27 07:27:38 AM UTC 24
Peak memory 227240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963814227 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.963814227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.62731027
Short name T1530
Test name
Test status
Simulation time 52269998832 ps
CPU time 83.34 seconds
Started Aug 27 07:26:44 AM UTC 24
Finished Aug 27 07:28:09 AM UTC 24
Peak memory 1321364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62731027 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.62731027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.778295995
Short name T1473
Test name
Test status
Simulation time 20477050049 ps
CPU time 9.37 seconds
Started Aug 27 07:26:56 AM UTC 24
Finished Aug 27 07:27:06 AM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7782959
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.778295995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.2450810871
Short name T1484
Test name
Test status
Simulation time 170854665 ps
CPU time 4.65 seconds
Started Aug 27 07:27:16 AM UTC 24
Finished Aug 27 07:27:22 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450810
871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.2450810871
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_alert_test.22793349
Short name T1522
Test name
Test status
Simulation time 17613634 ps
CPU time 0.88 seconds
Started Aug 27 07:28:02 AM UTC 24
Finished Aug 27 07:28:04 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22793349 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.22793349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.480437153
Short name T1498
Test name
Test status
Simulation time 78964579 ps
CPU time 2.99 seconds
Started Aug 27 07:27:31 AM UTC 24
Finished Aug 27 07:27:35 AM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480437153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.480437153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.1164912640
Short name T1504
Test name
Test status
Simulation time 2979247114 ps
CPU time 18.87 seconds
Started Aug 27 07:27:26 AM UTC 24
Finished Aug 27 07:27:46 AM UTC 24
Peak memory 360860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164912640 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.1164912640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.541364486
Short name T1539
Test name
Test status
Simulation time 22421947273 ps
CPU time 68.54 seconds
Started Aug 27 07:27:27 AM UTC 24
Finished Aug 27 07:28:37 AM UTC 24
Peak memory 583996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541364486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.541364486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.2615021521
Short name T1594
Test name
Test status
Simulation time 6490635442 ps
CPU time 150.92 seconds
Started Aug 27 07:27:25 AM UTC 24
Finished Aug 27 07:29:58 AM UTC 24
Peak memory 811112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615021521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2615021521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.3773156322
Short name T1493
Test name
Test status
Simulation time 109414715 ps
CPU time 1.82 seconds
Started Aug 27 07:27:25 AM UTC 24
Finished Aug 27 07:27:28 AM UTC 24
Peak memory 214292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773156322 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.3773156322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3895140507
Short name T1499
Test name
Test status
Simulation time 447512732 ps
CPU time 9.85 seconds
Started Aug 27 07:27:26 AM UTC 24
Finished Aug 27 07:27:37 AM UTC 24
Peak memory 264284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895140507 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.3895140507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.674506859
Short name T1581
Test name
Test status
Simulation time 10948051752 ps
CPU time 140.61 seconds
Started Aug 27 07:27:25 AM UTC 24
Finished Aug 27 07:29:48 AM UTC 24
Peak memory 884944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674506859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.674506859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.1804845166
Short name T1533
Test name
Test status
Simulation time 1961360159 ps
CPU time 20.83 seconds
Started Aug 27 07:27:55 AM UTC 24
Finished Aug 27 07:28:17 AM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804845166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1804845166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.4265442964
Short name T1514
Test name
Test status
Simulation time 414434644 ps
CPU time 3.79 seconds
Started Aug 27 07:27:54 AM UTC 24
Finished Aug 27 07:27:58 AM UTC 24
Peak memory 230916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265442964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4265442964
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_override.4241520012
Short name T1445
Test name
Test status
Simulation time 16151457 ps
CPU time 1.01 seconds
Started Aug 27 07:27:24 AM UTC 24
Finished Aug 27 07:27:26 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241520012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.4241520012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_perf.2438326846
Short name T1671
Test name
Test status
Simulation time 72478511029 ps
CPU time 287.74 seconds
Started Aug 27 07:27:27 AM UTC 24
Finished Aug 27 07:32:19 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438326846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2438326846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.3460898955
Short name T1494
Test name
Test status
Simulation time 62341958 ps
CPU time 2.56 seconds
Started Aug 27 07:27:27 AM UTC 24
Finished Aug 27 07:27:31 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460898955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3460898955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.3609869054
Short name T1503
Test name
Test status
Simulation time 950791265 ps
CPU time 16.96 seconds
Started Aug 27 07:27:23 AM UTC 24
Finished Aug 27 07:27:42 AM UTC 24
Peak memory 266276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609869054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3609869054
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_stress_all.4254521483
Short name T293
Test name
Test status
Simulation time 67616422756 ps
CPU time 1087.15 seconds
Started Aug 27 07:27:33 AM UTC 24
Finished Aug 27 07:45:53 AM UTC 24
Peak memory 1923284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254521483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.4254521483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.1058995282
Short name T1502
Test name
Test status
Simulation time 1061166902 ps
CPU time 10.34 seconds
Started Aug 27 07:27:28 AM UTC 24
Finished Aug 27 07:27:40 AM UTC 24
Peak memory 233080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058995282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1058995282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3821002945
Short name T1513
Test name
Test status
Simulation time 5319630375 ps
CPU time 6.54 seconds
Started Aug 27 07:27:51 AM UTC 24
Finished Aug 27 07:27:58 AM UTC 24
Peak memory 229200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3821002945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_ad
dr.3821002945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.4213879684
Short name T1506
Test name
Test status
Simulation time 407950050 ps
CPU time 1.62 seconds
Started Aug 27 07:27:45 AM UTC 24
Finished Aug 27 07:27:48 AM UTC 24
Peak memory 226612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213879
684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.4213879684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.1913510211
Short name T1508
Test name
Test status
Simulation time 118590441 ps
CPU time 1.87 seconds
Started Aug 27 07:27:47 AM UTC 24
Finished Aug 27 07:27:50 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913510
211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.1913510211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.1485196944
Short name T1519
Test name
Test status
Simulation time 1931174657 ps
CPU time 4.03 seconds
Started Aug 27 07:27:57 AM UTC 24
Finished Aug 27 07:28:02 AM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485196
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermar
ks_acq.1485196944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.2796731933
Short name T1517
Test name
Test status
Simulation time 318185991 ps
CPU time 1.82 seconds
Started Aug 27 07:27:59 AM UTC 24
Finished Aug 27 07:28:02 AM UTC 24
Peak memory 215024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796731
933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.2796731933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.873366785
Short name T1505
Test name
Test status
Simulation time 1160299994 ps
CPU time 7.39 seconds
Started Aug 27 07:27:39 AM UTC 24
Finished Aug 27 07:27:47 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873366
785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.873366785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.2000566766
Short name T1510
Test name
Test status
Simulation time 5623293213 ps
CPU time 13.98 seconds
Started Aug 27 07:27:39 AM UTC 24
Finished Aug 27 07:27:54 AM UTC 24
Peak memory 413908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2000566766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stres
s_wr.2000566766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.3652513814
Short name T1526
Test name
Test status
Simulation time 521000174 ps
CPU time 4.69 seconds
Started Aug 27 07:28:00 AM UTC 24
Finished Aug 27 07:28:06 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652513
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.3652513814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.2509392496
Short name T1523
Test name
Test status
Simulation time 562439691 ps
CPU time 3.38 seconds
Started Aug 27 07:28:00 AM UTC 24
Finished Aug 27 07:28:05 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509392
496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_ad
dr.2509392496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.802216906
Short name T1524
Test name
Test status
Simulation time 205404457 ps
CPU time 2.16 seconds
Started Aug 27 07:28:02 AM UTC 24
Finished Aug 27 07:28:05 AM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8022169
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_txstretch.802216906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_perf.1029363834
Short name T1516
Test name
Test status
Simulation time 2410524906 ps
CPU time 9.73 seconds
Started Aug 27 07:27:48 AM UTC 24
Finished Aug 27 07:27:59 AM UTC 24
Peak memory 233352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029363
834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.1029363834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.2506794160
Short name T1521
Test name
Test status
Simulation time 862420445 ps
CPU time 3.31 seconds
Started Aug 27 07:27:59 AM UTC 24
Finished Aug 27 07:28:03 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506794
160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.2506794160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.3690280097
Short name T1507
Test name
Test status
Simulation time 997204857 ps
CPU time 12.68 seconds
Started Aug 27 07:27:35 AM UTC 24
Finished Aug 27 07:27:49 AM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690280097 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.3690280097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.217476408
Short name T1672
Test name
Test status
Simulation time 55502507617 ps
CPU time 269.26 seconds
Started Aug 27 07:27:48 AM UTC 24
Finished Aug 27 07:32:21 AM UTC 24
Peak memory 1685676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217476
408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.217476408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.2845277765
Short name T1515
Test name
Test status
Simulation time 1678286697 ps
CPU time 21.16 seconds
Started Aug 27 07:27:37 AM UTC 24
Finished Aug 27 07:27:59 AM UTC 24
Peak memory 233656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845277765 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.2845277765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.3459488385
Short name T1695
Test name
Test status
Simulation time 35184966337 ps
CPU time 313.47 seconds
Started Aug 27 07:27:37 AM UTC 24
Finished Aug 27 07:32:54 AM UTC 24
Peak memory 3991776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459488385 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.3459488385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.3240928782
Short name T1512
Test name
Test status
Simulation time 1195410781 ps
CPU time 19.07 seconds
Started Aug 27 07:27:38 AM UTC 24
Finished Aug 27 07:27:58 AM UTC 24
Peak memory 464960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240928782 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.3240928782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.2879659747
Short name T1509
Test name
Test status
Simulation time 1890866998 ps
CPU time 10.26 seconds
Started Aug 27 07:27:41 AM UTC 24
Finished Aug 27 07:27:52 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879659
747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.2879659747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.3232518456
Short name T1528
Test name
Test status
Simulation time 407732701 ps
CPU time 7.44 seconds
Started Aug 27 07:27:59 AM UTC 24
Finished Aug 27 07:28:08 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232518
456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.3232518456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_alert_test.3572078180
Short name T1555
Test name
Test status
Simulation time 19320015 ps
CPU time 0.94 seconds
Started Aug 27 07:28:54 AM UTC 24
Finished Aug 27 07:28:56 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572078180 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3572078180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.4260960261
Short name T1532
Test name
Test status
Simulation time 201921814 ps
CPU time 2.63 seconds
Started Aug 27 07:28:09 AM UTC 24
Finished Aug 27 07:28:13 AM UTC 24
Peak memory 227260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260960261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.4260960261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.3081466047
Short name T1535
Test name
Test status
Simulation time 3394663161 ps
CPU time 10.13 seconds
Started Aug 27 07:28:07 AM UTC 24
Finished Aug 27 07:28:18 AM UTC 24
Peak memory 299236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081466047 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.3081466047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.3036671629
Short name T1573
Test name
Test status
Simulation time 3695716126 ps
CPU time 94.04 seconds
Started Aug 27 07:28:07 AM UTC 24
Finished Aug 27 07:29:43 AM UTC 24
Peak memory 272592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036671629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3036671629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.3052042612
Short name T1566
Test name
Test status
Simulation time 9585667057 ps
CPU time 71.66 seconds
Started Aug 27 07:28:05 AM UTC 24
Finished Aug 27 07:29:18 AM UTC 24
Peak memory 827560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052042612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3052042612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.228978813
Short name T1529
Test name
Test status
Simulation time 133423531 ps
CPU time 1.42 seconds
Started Aug 27 07:28:06 AM UTC 24
Finished Aug 27 07:28:08 AM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228978813 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.228978813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.854505877
Short name T1531
Test name
Test status
Simulation time 481839738 ps
CPU time 3.12 seconds
Started Aug 27 07:28:07 AM UTC 24
Finished Aug 27 07:28:11 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854505877 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.854505877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.3936207514
Short name T1518
Test name
Test status
Simulation time 3093933606 ps
CPU time 79.55 seconds
Started Aug 27 07:28:05 AM UTC 24
Finished Aug 27 07:29:26 AM UTC 24
Peak memory 975264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936207514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.3936207514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.3569539514
Short name T1550
Test name
Test status
Simulation time 293011141 ps
CPU time 5.55 seconds
Started Aug 27 07:28:45 AM UTC 24
Finished Aug 27 07:28:52 AM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569539514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3569539514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_override.3061552093
Short name T1525
Test name
Test status
Simulation time 21113406 ps
CPU time 1.07 seconds
Started Aug 27 07:28:04 AM UTC 24
Finished Aug 27 07:28:06 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061552093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3061552093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_perf.2169809702
Short name T1602
Test name
Test status
Simulation time 12824610395 ps
CPU time 122.26 seconds
Started Aug 27 07:28:07 AM UTC 24
Finished Aug 27 07:30:12 AM UTC 24
Peak memory 250272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169809702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2169809702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2643389137
Short name T1538
Test name
Test status
Simulation time 445714070 ps
CPU time 18.87 seconds
Started Aug 27 07:28:08 AM UTC 24
Finished Aug 27 07:28:28 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643389137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2643389137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.1864283547
Short name T1562
Test name
Test status
Simulation time 1292116833 ps
CPU time 56.1 seconds
Started Aug 27 07:28:04 AM UTC 24
Finished Aug 27 07:29:01 AM UTC 24
Peak memory 325728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864283547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1864283547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.82843020
Short name T1545
Test name
Test status
Simulation time 11949001618 ps
CPU time 32.97 seconds
Started Aug 27 07:28:09 AM UTC 24
Finished Aug 27 07:28:44 AM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82843020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.82843020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.4279493671
Short name T1552
Test name
Test status
Simulation time 3998210361 ps
CPU time 9.29 seconds
Started Aug 27 07:28:42 AM UTC 24
Finished Aug 27 07:28:52 AM UTC 24
Peak memory 226920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4279493671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad
dr.4279493671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.386502907
Short name T1540
Test name
Test status
Simulation time 475302930 ps
CPU time 1.78 seconds
Started Aug 27 07:28:34 AM UTC 24
Finished Aug 27 07:28:37 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865029
07 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.386502907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.2353551338
Short name T1544
Test name
Test status
Simulation time 243926731 ps
CPU time 2.58 seconds
Started Aug 27 07:28:38 AM UTC 24
Finished Aug 27 07:28:42 AM UTC 24
Peak memory 216712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353551
338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.2353551338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.3448028720
Short name T1548
Test name
Test status
Simulation time 282984079 ps
CPU time 3.12 seconds
Started Aug 27 07:28:46 AM UTC 24
Finished Aug 27 07:28:50 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448028
720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermar
ks_acq.3448028720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.265291100
Short name T1549
Test name
Test status
Simulation time 652222409 ps
CPU time 1.96 seconds
Started Aug 27 07:28:48 AM UTC 24
Finished Aug 27 07:28:51 AM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652911
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks
_tx.265291100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2048200240
Short name T1543
Test name
Test status
Simulation time 1236178162 ps
CPU time 12.53 seconds
Started Aug 27 07:28:27 AM UTC 24
Finished Aug 27 07:28:41 AM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204820
0240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.2048200240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.305440362
Short name T1553
Test name
Test status
Simulation time 7664881750 ps
CPU time 24.8 seconds
Started Aug 27 07:28:27 AM UTC 24
Finished Aug 27 07:28:53 AM UTC 24
Peak memory 286876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=305440362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stress
_wr.305440362
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.1801439477
Short name T1557
Test name
Test status
Simulation time 2355373136 ps
CPU time 3.48 seconds
Started Aug 27 07:28:52 AM UTC 24
Finished Aug 27 07:28:57 AM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801439
477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.1801439477
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.2009609341
Short name T1558
Test name
Test status
Simulation time 575977168 ps
CPU time 3.48 seconds
Started Aug 27 07:28:52 AM UTC 24
Finished Aug 27 07:28:57 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009609
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad
dr.2009609341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.3094139005
Short name T1556
Test name
Test status
Simulation time 354762291 ps
CPU time 2.21 seconds
Started Aug 27 07:28:53 AM UTC 24
Finished Aug 27 07:28:57 AM UTC 24
Peak memory 233428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094139
005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.3094139005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_perf.3197909923
Short name T1547
Test name
Test status
Simulation time 3470036129 ps
CPU time 7.52 seconds
Started Aug 27 07:28:38 AM UTC 24
Finished Aug 27 07:28:48 AM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197909
923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.3197909923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.1416594406
Short name T1554
Test name
Test status
Simulation time 6460878567 ps
CPU time 2.95 seconds
Started Aug 27 07:28:51 AM UTC 24
Finished Aug 27 07:28:55 AM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416594
406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.1416594406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.1031687193
Short name T1560
Test name
Test status
Simulation time 1289467863 ps
CPU time 45.9 seconds
Started Aug 27 07:28:14 AM UTC 24
Finished Aug 27 07:29:01 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031687193 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.1031687193
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.3521529464
Short name T1725
Test name
Test status
Simulation time 18405110175 ps
CPU time 301.82 seconds
Started Aug 27 07:28:40 AM UTC 24
Finished Aug 27 07:33:45 AM UTC 24
Peak memory 2611352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352152
9464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.3521529464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.3377979223
Short name T1565
Test name
Test status
Simulation time 2503814046 ps
CPU time 66.99 seconds
Started Aug 27 07:28:18 AM UTC 24
Finished Aug 27 07:29:26 AM UTC 24
Peak memory 228984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377979223 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.3377979223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.2946923623
Short name T1689
Test name
Test status
Simulation time 46854152778 ps
CPU time 260.42 seconds
Started Aug 27 07:28:18 AM UTC 24
Finished Aug 27 07:32:41 AM UTC 24
Peak memory 3651740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946923623 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.2946923623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.3764827745
Short name T1546
Test name
Test status
Simulation time 2992989160 ps
CPU time 26.75 seconds
Started Aug 27 07:28:19 AM UTC 24
Finished Aug 27 07:28:47 AM UTC 24
Peak memory 313596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764827745 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.3764827745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.2122609145
Short name T1542
Test name
Test status
Simulation time 1509311088 ps
CPU time 10.33 seconds
Started Aug 27 07:28:29 AM UTC 24
Finished Aug 27 07:28:41 AM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122609
145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.2122609145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.3592688075
Short name T1551
Test name
Test status
Simulation time 101029944 ps
CPU time 2.99 seconds
Started Aug 27 07:28:48 AM UTC 24
Finished Aug 27 07:28:52 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592688
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3592688075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1810188230
Short name T1584
Test name
Test status
Simulation time 31722147 ps
CPU time 0.93 seconds
Started Aug 27 07:29:49 AM UTC 24
Finished Aug 27 07:29:51 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810188230 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1810188230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.1678875547
Short name T1567
Test name
Test status
Simulation time 1270861001 ps
CPU time 20.49 seconds
Started Aug 27 07:28:58 AM UTC 24
Finished Aug 27 07:29:20 AM UTC 24
Peak memory 284800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678875547 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.1678875547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3785024236
Short name T1664
Test name
Test status
Simulation time 4782113883 ps
CPU time 176.62 seconds
Started Aug 27 07:29:02 AM UTC 24
Finished Aug 27 07:32:02 AM UTC 24
Peak memory 762132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785024236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3785024236
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2773588995
Short name T1438
Test name
Test status
Simulation time 5898774483 ps
CPU time 36.16 seconds
Started Aug 27 07:28:58 AM UTC 24
Finished Aug 27 07:29:36 AM UTC 24
Peak memory 590036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773588995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2773588995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.1702229269
Short name T1561
Test name
Test status
Simulation time 1914714329 ps
CPU time 1.86 seconds
Started Aug 27 07:28:58 AM UTC 24
Finished Aug 27 07:29:01 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702229269 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.1702229269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3694709928
Short name T1564
Test name
Test status
Simulation time 647175147 ps
CPU time 11.11 seconds
Started Aug 27 07:28:59 AM UTC 24
Finished Aug 27 07:29:11 AM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694709928 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.3694709928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.2509888825
Short name T1608
Test name
Test status
Simulation time 3971197738 ps
CPU time 85.2 seconds
Started Aug 27 07:28:57 AM UTC 24
Finished Aug 27 07:30:24 AM UTC 24
Peak memory 1190084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509888825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2509888825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.765409615
Short name T1593
Test name
Test status
Simulation time 5070748705 ps
CPU time 11.81 seconds
Started Aug 27 07:29:44 AM UTC 24
Finished Aug 27 07:29:57 AM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765409615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.765409615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.690359120
Short name T1575
Test name
Test status
Simulation time 113787948 ps
CPU time 2.74 seconds
Started Aug 27 07:29:43 AM UTC 24
Finished Aug 27 07:29:47 AM UTC 24
Peak memory 243788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690359120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.690359120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_override.2918828909
Short name T1559
Test name
Test status
Simulation time 26097013 ps
CPU time 1.09 seconds
Started Aug 27 07:28:56 AM UTC 24
Finished Aug 27 07:28:58 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918828909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2918828909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_perf.372525888
Short name T1696
Test name
Test status
Simulation time 18881364629 ps
CPU time 231.19 seconds
Started Aug 27 07:29:02 AM UTC 24
Finished Aug 27 07:32:57 AM UTC 24
Peak memory 970904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372525888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.372525888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1613662309
Short name T1577
Test name
Test status
Simulation time 5782752191 ps
CPU time 43.02 seconds
Started Aug 27 07:29:02 AM UTC 24
Finished Aug 27 07:29:47 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613662309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1613662309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.2154171259
Short name T1598
Test name
Test status
Simulation time 5876677318 ps
CPU time 69.39 seconds
Started Aug 27 07:28:55 AM UTC 24
Finished Aug 27 07:30:06 AM UTC 24
Peak memory 331944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154171259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2154171259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.158326108
Short name T1756
Test name
Test status
Simulation time 44415964740 ps
CPU time 1840.7 seconds
Started Aug 27 07:29:17 AM UTC 24
Finished Aug 27 08:00:14 AM UTC 24
Peak memory 4811008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158326108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.158326108
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.3952619256
Short name T1571
Test name
Test status
Simulation time 1174721021 ps
CPU time 29.24 seconds
Started Aug 27 07:29:11 AM UTC 24
Finished Aug 27 07:29:42 AM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952619256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3952619256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.578695228
Short name T1585
Test name
Test status
Simulation time 1633511788 ps
CPU time 7.06 seconds
Started Aug 27 07:29:43 AM UTC 24
Finished Aug 27 07:29:51 AM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=578695228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.578695228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.3543496265
Short name T1569
Test name
Test status
Simulation time 282253343 ps
CPU time 1.67 seconds
Started Aug 27 07:29:36 AM UTC 24
Finished Aug 27 07:29:39 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543496
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.3543496265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.1184163080
Short name T1572
Test name
Test status
Simulation time 148999656 ps
CPU time 1.57 seconds
Started Aug 27 07:29:40 AM UTC 24
Finished Aug 27 07:29:42 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184163
080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.1184163080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1748432091
Short name T1582
Test name
Test status
Simulation time 756757207 ps
CPU time 3.76 seconds
Started Aug 27 07:29:44 AM UTC 24
Finished Aug 27 07:29:49 AM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748432
091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.1748432091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1562615349
Short name T1580
Test name
Test status
Simulation time 223746208 ps
CPU time 2.81 seconds
Started Aug 27 07:29:44 AM UTC 24
Finished Aug 27 07:29:48 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562615
349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermark
s_tx.1562615349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.270562324
Short name T1579
Test name
Test status
Simulation time 1218263323 ps
CPU time 3.72 seconds
Started Aug 27 07:29:43 AM UTC 24
Finished Aug 27 07:29:48 AM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705623
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.270562324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.1787769978
Short name T1399
Test name
Test status
Simulation time 1284837033 ps
CPU time 10.08 seconds
Started Aug 27 07:29:27 AM UTC 24
Finished Aug 27 07:29:38 AM UTC 24
Peak memory 232976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178776
9978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.1787769978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.1087418052
Short name T1570
Test name
Test status
Simulation time 12206497270 ps
CPU time 13.26 seconds
Started Aug 27 07:29:27 AM UTC 24
Finished Aug 27 07:29:41 AM UTC 24
Peak memory 338420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1087418052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stres
s_wr.1087418052
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.673461950
Short name T1588
Test name
Test status
Simulation time 5151451849 ps
CPU time 3.94 seconds
Started Aug 27 07:29:47 AM UTC 24
Finished Aug 27 07:29:52 AM UTC 24
Peak memory 226736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6734619
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.673461950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3645866867
Short name T1592
Test name
Test status
Simulation time 935973429 ps
CPU time 5.25 seconds
Started Aug 27 07:29:49 AM UTC 24
Finished Aug 27 07:29:55 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645866
867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.3645866867
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.227705185
Short name T1586
Test name
Test status
Simulation time 132743311 ps
CPU time 2.05 seconds
Started Aug 27 07:29:49 AM UTC 24
Finished Aug 27 07:29:52 AM UTC 24
Peak memory 233552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277051
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_txstretch.227705185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_perf.4045255257
Short name T1583
Test name
Test status
Simulation time 1875646770 ps
CPU time 9.17 seconds
Started Aug 27 07:29:40 AM UTC 24
Finished Aug 27 07:29:50 AM UTC 24
Peak memory 233200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045255
257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.4045255257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.569988944
Short name T1589
Test name
Test status
Simulation time 554031454 ps
CPU time 4.24 seconds
Started Aug 27 07:29:47 AM UTC 24
Finished Aug 27 07:29:52 AM UTC 24
Peak memory 216100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5699889
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.569988944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.354073232
Short name T1568
Test name
Test status
Simulation time 1048154365 ps
CPU time 14.4 seconds
Started Aug 27 07:29:17 AM UTC 24
Finished Aug 27 07:29:32 AM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354073232 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.354073232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.881159738
Short name T1644
Test name
Test status
Simulation time 61731921552 ps
CPU time 106.48 seconds
Started Aug 27 07:29:42 AM UTC 24
Finished Aug 27 07:31:30 AM UTC 24
Peak memory 1370516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881159
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.881159738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3647392165
Short name T1578
Test name
Test status
Simulation time 1237384283 ps
CPU time 24.98 seconds
Started Aug 27 07:29:21 AM UTC 24
Finished Aug 27 07:29:47 AM UTC 24
Peak memory 243844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647392165 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.3647392165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1472701455
Short name T1625
Test name
Test status
Simulation time 25083105149 ps
CPU time 84.21 seconds
Started Aug 27 07:29:19 AM UTC 24
Finished Aug 27 07:30:45 AM UTC 24
Peak memory 1296604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472701455 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.1472701455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3983038087
Short name T1483
Test name
Test status
Simulation time 3241171614 ps
CPU time 12.13 seconds
Started Aug 27 07:29:22 AM UTC 24
Finished Aug 27 07:29:35 AM UTC 24
Peak memory 248080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983038087 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.3983038087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.2926884355
Short name T1574
Test name
Test status
Simulation time 2002323698 ps
CPU time 9.18 seconds
Started Aug 27 07:29:33 AM UTC 24
Finished Aug 27 07:29:44 AM UTC 24
Peak memory 233796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926884
355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.2926884355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2952585635
Short name T1590
Test name
Test status
Simulation time 164310717 ps
CPU time 5.4 seconds
Started Aug 27 07:29:47 AM UTC 24
Finished Aug 27 07:29:54 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952585
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2952585635
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2775832775
Short name T1620
Test name
Test status
Simulation time 44367063 ps
CPU time 0.99 seconds
Started Aug 27 07:30:34 AM UTC 24
Finished Aug 27 07:30:36 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775832775 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2775832775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.332956633
Short name T1601
Test name
Test status
Simulation time 303991491 ps
CPU time 14.47 seconds
Started Aug 27 07:29:56 AM UTC 24
Finished Aug 27 07:30:11 AM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332956633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.332956633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2163479036
Short name T1599
Test name
Test status
Simulation time 584775960 ps
CPU time 12.99 seconds
Started Aug 27 07:29:52 AM UTC 24
Finished Aug 27 07:30:06 AM UTC 24
Peak memory 315488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163479036 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.2163479036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1053451384
Short name T1692
Test name
Test status
Simulation time 4197673388 ps
CPU time 169.11 seconds
Started Aug 27 07:29:53 AM UTC 24
Finished Aug 27 07:32:45 AM UTC 24
Peak memory 735440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053451384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1053451384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3136152779
Short name T1634
Test name
Test status
Simulation time 7532519098 ps
CPU time 78.37 seconds
Started Aug 27 07:29:52 AM UTC 24
Finished Aug 27 07:31:12 AM UTC 24
Peak memory 735316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136152779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3136152779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.3520534449
Short name T1591
Test name
Test status
Simulation time 398609033 ps
CPU time 1.27 seconds
Started Aug 27 07:29:52 AM UTC 24
Finished Aug 27 07:29:54 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520534449 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.3520534449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2747533178
Short name T1595
Test name
Test status
Simulation time 529473541 ps
CPU time 6.13 seconds
Started Aug 27 07:29:53 AM UTC 24
Finished Aug 27 07:30:00 AM UTC 24
Peak memory 237572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747533178 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.2747533178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1547656122
Short name T1738
Test name
Test status
Simulation time 19436488726 ps
CPU time 314.33 seconds
Started Aug 27 07:29:51 AM UTC 24
Finished Aug 27 07:35:09 AM UTC 24
Peak memory 1528164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547656122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1547656122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.377403349
Short name T1619
Test name
Test status
Simulation time 2693443888 ps
CPU time 9.02 seconds
Started Aug 27 07:30:25 AM UTC 24
Finished Aug 27 07:30:36 AM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377403349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.377403349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_override.199006067
Short name T1587
Test name
Test status
Simulation time 47914893 ps
CPU time 0.97 seconds
Started Aug 27 07:29:50 AM UTC 24
Finished Aug 27 07:29:52 AM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199006067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.199006067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_perf.222573754
Short name T1596
Test name
Test status
Simulation time 1080255301 ps
CPU time 6.98 seconds
Started Aug 27 07:29:53 AM UTC 24
Finished Aug 27 07:30:01 AM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222573754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.222573754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.3964233266
Short name T1751
Test name
Test status
Simulation time 23246244276 ps
CPU time 876.36 seconds
Started Aug 27 07:29:54 AM UTC 24
Finished Aug 27 07:44:40 AM UTC 24
Peak memory 3782812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964233266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3964233266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1004293485
Short name T1641
Test name
Test status
Simulation time 1665194938 ps
CPU time 95.32 seconds
Started Aug 27 07:29:49 AM UTC 24
Finished Aug 27 07:31:26 AM UTC 24
Peak memory 380964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004293485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1004293485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2042292726
Short name T1614
Test name
Test status
Simulation time 606908738 ps
CPU time 33.87 seconds
Started Aug 27 07:29:56 AM UTC 24
Finished Aug 27 07:30:31 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042292726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2042292726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2957932656
Short name T1611
Test name
Test status
Simulation time 2833861199 ps
CPU time 9.43 seconds
Started Aug 27 07:30:19 AM UTC 24
Finished Aug 27 07:30:29 AM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2957932656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.2957932656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.384488896
Short name T1603
Test name
Test status
Simulation time 182756977 ps
CPU time 1.96 seconds
Started Aug 27 07:30:12 AM UTC 24
Finished Aug 27 07:30:16 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844888
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.384488896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1733215308
Short name T1605
Test name
Test status
Simulation time 185523977 ps
CPU time 1.78 seconds
Started Aug 27 07:30:16 AM UTC 24
Finished Aug 27 07:30:18 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733215
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.1733215308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3350423301
Short name T1613
Test name
Test status
Simulation time 448525556 ps
CPU time 3.8 seconds
Started Aug 27 07:30:25 AM UTC 24
Finished Aug 27 07:30:30 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350423
301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar
ks_acq.3350423301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2608808798
Short name T1612
Test name
Test status
Simulation time 135439694 ps
CPU time 1.71 seconds
Started Aug 27 07:30:27 AM UTC 24
Finished Aug 27 07:30:30 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608808
798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermark
s_tx.2608808798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2991042300
Short name T1610
Test name
Test status
Simulation time 419150631 ps
CPU time 4.8 seconds
Started Aug 27 07:30:20 AM UTC 24
Finished Aug 27 07:30:26 AM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991042
300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_hrst.2991042300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3760078242
Short name T1606
Test name
Test status
Simulation time 1227162675 ps
CPU time 10.91 seconds
Started Aug 27 07:30:07 AM UTC 24
Finished Aug 27 07:30:19 AM UTC 24
Peak memory 233480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376007
8242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.3760078242
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.3486768899
Short name T1743
Test name
Test status
Simulation time 19819951009 ps
CPU time 348.22 seconds
Started Aug 27 07:30:07 AM UTC 24
Finished Aug 27 07:36:00 AM UTC 24
Peak memory 4802712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3486768899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stres
s_wr.3486768899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1953014185
Short name T1618
Test name
Test status
Simulation time 518767477 ps
CPU time 3.93 seconds
Started Aug 27 07:30:31 AM UTC 24
Finished Aug 27 07:30:35 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953014
185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.1953014185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2213778261
Short name T1621
Test name
Test status
Simulation time 473247291 ps
CPU time 4.67 seconds
Started Aug 27 07:30:32 AM UTC 24
Finished Aug 27 07:30:37 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213778
261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_ad
dr.2213778261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3433027756
Short name T1607
Test name
Test status
Simulation time 408672798 ps
CPU time 5.7 seconds
Started Aug 27 07:30:17 AM UTC 24
Finished Aug 27 07:30:23 AM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433027
756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.3433027756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.4270691041
Short name T1616
Test name
Test status
Simulation time 759966476 ps
CPU time 3.38 seconds
Started Aug 27 07:30:30 AM UTC 24
Finished Aug 27 07:30:35 AM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270691
041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.4270691041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.4156629310
Short name T1604
Test name
Test status
Simulation time 3734730664 ps
CPU time 17.9 seconds
Started Aug 27 07:29:59 AM UTC 24
Finished Aug 27 07:30:18 AM UTC 24
Peak memory 228976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156629310 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.4156629310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3104201562
Short name T1636
Test name
Test status
Simulation time 27689631334 ps
CPU time 57.04 seconds
Started Aug 27 07:30:19 AM UTC 24
Finished Aug 27 07:31:17 AM UTC 24
Peak memory 315556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310420
1562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.3104201562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.3080422104
Short name T1624
Test name
Test status
Simulation time 12767199067 ps
CPU time 39.71 seconds
Started Aug 27 07:30:02 AM UTC 24
Finished Aug 27 07:30:43 AM UTC 24
Peak memory 250088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080422104 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.3080422104
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.750638654
Short name T1600
Test name
Test status
Simulation time 8491082658 ps
CPU time 9.12 seconds
Started Aug 27 07:30:01 AM UTC 24
Finished Aug 27 07:30:11 AM UTC 24
Peak memory 216944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750638654 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.750638654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.4202743180
Short name T1627
Test name
Test status
Simulation time 4100902045 ps
CPU time 39.29 seconds
Started Aug 27 07:30:06 AM UTC 24
Finished Aug 27 07:30:47 AM UTC 24
Peak memory 641240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202743180 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.4202743180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1893789692
Short name T1609
Test name
Test status
Simulation time 5756335004 ps
CPU time 10.52 seconds
Started Aug 27 07:30:12 AM UTC 24
Finished Aug 27 07:30:24 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893789
692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.1893789692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.2728900272
Short name T1615
Test name
Test status
Simulation time 79227091 ps
CPU time 3.13 seconds
Started Aug 27 07:30:28 AM UTC 24
Finished Aug 27 07:30:33 AM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728900
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.2728900272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_alert_test.3749425135
Short name T1649
Test name
Test status
Simulation time 39941415 ps
CPU time 0.85 seconds
Started Aug 27 07:31:35 AM UTC 24
Finished Aug 27 07:31:37 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749425135 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3749425135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2551214460
Short name T1630
Test name
Test status
Simulation time 380879639 ps
CPU time 2.76 seconds
Started Aug 27 07:30:48 AM UTC 24
Finished Aug 27 07:30:52 AM UTC 24
Peak memory 233920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551214460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2551214460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2363294157
Short name T1631
Test name
Test status
Simulation time 1069989949 ps
CPU time 15.75 seconds
Started Aug 27 07:30:38 AM UTC 24
Finished Aug 27 07:30:55 AM UTC 24
Peak memory 335896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363294157 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.2363294157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1002500274
Short name T1718
Test name
Test status
Simulation time 6648539048 ps
CPU time 167.65 seconds
Started Aug 27 07:30:40 AM UTC 24
Finished Aug 27 07:33:31 AM UTC 24
Peak memory 653472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002500274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1002500274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.2308588655
Short name T1655
Test name
Test status
Simulation time 3095380236 ps
CPU time 61.96 seconds
Started Aug 27 07:30:37 AM UTC 24
Finished Aug 27 07:31:41 AM UTC 24
Peak memory 600276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308588655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2308588655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3551812789
Short name T1623
Test name
Test status
Simulation time 482143429 ps
CPU time 1.68 seconds
Started Aug 27 07:30:37 AM UTC 24
Finished Aug 27 07:30:40 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551812789 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.3551812789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2231543558
Short name T1628
Test name
Test status
Simulation time 715172151 ps
CPU time 7.16 seconds
Started Aug 27 07:30:39 AM UTC 24
Finished Aug 27 07:30:47 AM UTC 24
Peak memory 249928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231543558 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.2231543558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.383677177
Short name T1697
Test name
Test status
Simulation time 11300540084 ps
CPU time 138.35 seconds
Started Aug 27 07:30:36 AM UTC 24
Finished Aug 27 07:32:57 AM UTC 24
Peak memory 1618120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383677177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.383677177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2252227356
Short name T1658
Test name
Test status
Simulation time 510944258 ps
CPU time 19.09 seconds
Started Aug 27 07:31:26 AM UTC 24
Finished Aug 27 07:31:47 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252227356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2252227356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_override.385992022
Short name T1622
Test name
Test status
Simulation time 18552107 ps
CPU time 0.92 seconds
Started Aug 27 07:30:36 AM UTC 24
Finished Aug 27 07:30:38 AM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385992022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.385992022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_perf.4151364426
Short name T1632
Test name
Test status
Simulation time 7155426798 ps
CPU time 20.21 seconds
Started Aug 27 07:30:44 AM UTC 24
Finished Aug 27 07:31:05 AM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151364426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.4151364426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.640024864
Short name T1629
Test name
Test status
Simulation time 44375014 ps
CPU time 1.53 seconds
Started Aug 27 07:30:46 AM UTC 24
Finished Aug 27 07:30:48 AM UTC 24
Peak memory 238580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640024864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.640024864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.3885653485
Short name T1660
Test name
Test status
Simulation time 1586449321 ps
CPU time 77.6 seconds
Started Aug 27 07:30:36 AM UTC 24
Finished Aug 27 07:31:55 AM UTC 24
Peak memory 416136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885653485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3885653485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.3407459567
Short name T297
Test name
Test status
Simulation time 34676833331 ps
CPU time 1034.94 seconds
Started Aug 27 07:30:49 AM UTC 24
Finished Aug 27 07:48:15 AM UTC 24
Peak memory 2117904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407459567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3407459567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3521239844
Short name T1633
Test name
Test status
Simulation time 9162542024 ps
CPU time 22.53 seconds
Started Aug 27 07:30:47 AM UTC 24
Finished Aug 27 07:31:10 AM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521239844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3521239844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2941036089
Short name T1642
Test name
Test status
Simulation time 823991183 ps
CPU time 4.41 seconds
Started Aug 27 07:31:22 AM UTC 24
Finished Aug 27 07:31:27 AM UTC 24
Peak memory 226832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2941036089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad
dr.2941036089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3328636739
Short name T1639
Test name
Test status
Simulation time 154050057 ps
CPU time 1.25 seconds
Started Aug 27 07:31:20 AM UTC 24
Finished Aug 27 07:31:22 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328636
739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.3328636739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3675338814
Short name T1640
Test name
Test status
Simulation time 165287754 ps
CPU time 1.59 seconds
Started Aug 27 07:31:21 AM UTC 24
Finished Aug 27 07:31:23 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675338
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.3675338814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.603735602
Short name T1645
Test name
Test status
Simulation time 443492473 ps
CPU time 2.61 seconds
Started Aug 27 07:31:28 AM UTC 24
Finished Aug 27 07:31:32 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6037356
02 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_acq.603735602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.527435287
Short name T1646
Test name
Test status
Simulation time 570172151 ps
CPU time 2.09 seconds
Started Aug 27 07:31:29 AM UTC 24
Finished Aug 27 07:31:33 AM UTC 24
Peak memory 216384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5274352
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermarks
_tx.527435287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2920335169
Short name T1638
Test name
Test status
Simulation time 3582265772 ps
CPU time 7.84 seconds
Started Aug 27 07:31:11 AM UTC 24
Finished Aug 27 07:31:20 AM UTC 24
Peak memory 231232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292033
5169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.2920335169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3862336073
Short name T1647
Test name
Test status
Simulation time 18386264244 ps
CPU time 19.16 seconds
Started Aug 27 07:31:13 AM UTC 24
Finished Aug 27 07:31:34 AM UTC 24
Peak memory 346256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3862336073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.3862336073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1404724157
Short name T1652
Test name
Test status
Simulation time 554581230 ps
CPU time 4.27 seconds
Started Aug 27 07:31:33 AM UTC 24
Finished Aug 27 07:31:38 AM UTC 24
Peak memory 226964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404724
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.1404724157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1817032470
Short name T1654
Test name
Test status
Simulation time 469394892 ps
CPU time 4.7 seconds
Started Aug 27 07:31:34 AM UTC 24
Finished Aug 27 07:31:40 AM UTC 24
Peak memory 216724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817032
470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad
dr.1817032470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3859337329
Short name T1650
Test name
Test status
Simulation time 338810022 ps
CPU time 1.57 seconds
Started Aug 27 07:31:35 AM UTC 24
Finished Aug 27 07:31:38 AM UTC 24
Peak memory 232584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859337
329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.3859337329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4090868725
Short name T1643
Test name
Test status
Simulation time 3340942902 ps
CPU time 6.99 seconds
Started Aug 27 07:31:21 AM UTC 24
Finished Aug 27 07:31:29 AM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090868
725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.4090868725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.818505144
Short name T1648
Test name
Test status
Simulation time 492648275 ps
CPU time 3.59 seconds
Started Aug 27 07:31:32 AM UTC 24
Finished Aug 27 07:31:36 AM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8185051
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.818505144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.2409385576
Short name T96
Test name
Test status
Simulation time 983382598 ps
CPU time 30.61 seconds
Started Aug 27 07:30:49 AM UTC 24
Finished Aug 27 07:31:21 AM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409385576 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.2409385576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.658290893
Short name T1744
Test name
Test status
Simulation time 27236207013 ps
CPU time 366.61 seconds
Started Aug 27 07:31:22 AM UTC 24
Finished Aug 27 07:37:33 AM UTC 24
Peak memory 2955532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658290
893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.658290893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.1161470244
Short name T1635
Test name
Test status
Simulation time 362043192 ps
CPU time 18.99 seconds
Started Aug 27 07:30:56 AM UTC 24
Finished Aug 27 07:31:16 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161470244 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.1161470244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.2280639499
Short name T1741
Test name
Test status
Simulation time 52473796369 ps
CPU time 298.04 seconds
Started Aug 27 07:30:52 AM UTC 24
Finished Aug 27 07:35:54 AM UTC 24
Peak memory 4026784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280639499 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.2280639499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.2812899139
Short name T1663
Test name
Test status
Simulation time 2956123623 ps
CPU time 53.73 seconds
Started Aug 27 07:31:05 AM UTC 24
Finished Aug 27 07:32:00 AM UTC 24
Peak memory 901272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812899139 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.2812899139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.183099987
Short name T1617
Test name
Test status
Simulation time 6516203836 ps
CPU time 11.77 seconds
Started Aug 27 07:31:18 AM UTC 24
Finished Aug 27 07:31:30 AM UTC 24
Peak memory 233960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830999
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.183099987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3368236049
Short name T1651
Test name
Test status
Simulation time 341655892 ps
CPU time 6.21 seconds
Started Aug 27 07:31:31 AM UTC 24
Finished Aug 27 07:31:38 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368236
049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3368236049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3779897273
Short name T1682
Test name
Test status
Simulation time 15680742 ps
CPU time 0.89 seconds
Started Aug 27 07:32:31 AM UTC 24
Finished Aug 27 07:32:33 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779897273 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3779897273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1359757228
Short name T1659
Test name
Test status
Simulation time 2816428353 ps
CPU time 10.42 seconds
Started Aug 27 07:31:41 AM UTC 24
Finished Aug 27 07:31:52 AM UTC 24
Peak memory 254176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359757228 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.1359757228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1436184027
Short name T1719
Test name
Test status
Simulation time 1911210183 ps
CPU time 107.53 seconds
Started Aug 27 07:31:42 AM UTC 24
Finished Aug 27 07:33:31 AM UTC 24
Peak memory 438372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436184027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1436184027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3061179492
Short name T1694
Test name
Test status
Simulation time 45129798599 ps
CPU time 71.11 seconds
Started Aug 27 07:31:39 AM UTC 24
Finished Aug 27 07:32:52 AM UTC 24
Peak memory 758040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061179492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3061179492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.4093482310
Short name T1656
Test name
Test status
Simulation time 329283120 ps
CPU time 1.26 seconds
Started Aug 27 07:31:39 AM UTC 24
Finished Aug 27 07:31:42 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093482310 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.4093482310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.4084847505
Short name T1657
Test name
Test status
Simulation time 100275434 ps
CPU time 4.15 seconds
Started Aug 27 07:31:41 AM UTC 24
Finished Aug 27 07:31:46 AM UTC 24
Peak memory 229580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084847505 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.4084847505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.1553522789
Short name T1710
Test name
Test status
Simulation time 15704206086 ps
CPU time 104.66 seconds
Started Aug 27 07:31:38 AM UTC 24
Finished Aug 27 07:33:25 AM UTC 24
Peak memory 1179836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553522789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.1553522789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2188639423
Short name T1679
Test name
Test status
Simulation time 324635203 ps
CPU time 5.44 seconds
Started Aug 27 07:32:24 AM UTC 24
Finished Aug 27 07:32:30 AM UTC 24
Peak memory 216836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188639423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2188639423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_override.3518992156
Short name T1653
Test name
Test status
Simulation time 49821886 ps
CPU time 1.08 seconds
Started Aug 27 07:31:37 AM UTC 24
Finished Aug 27 07:31:39 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518992156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3518992156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_perf.609258077
Short name T1750
Test name
Test status
Simulation time 51462773583 ps
CPU time 594.06 seconds
Started Aug 27 07:31:43 AM UTC 24
Finished Aug 27 07:41:43 AM UTC 24
Peak memory 2879704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609258077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.609258077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.3006400490
Short name T1677
Test name
Test status
Simulation time 6263051954 ps
CPU time 38.58 seconds
Started Aug 27 07:31:47 AM UTC 24
Finished Aug 27 07:32:27 AM UTC 24
Peak memory 585884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006400490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.3006400490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.739141217
Short name T1661
Test name
Test status
Simulation time 1355313757 ps
CPU time 19.79 seconds
Started Aug 27 07:31:37 AM UTC 24
Finished Aug 27 07:31:58 AM UTC 24
Peak memory 350316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739141217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.739141217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_stress_all.3016190274
Short name T1754
Test name
Test status
Simulation time 14692986793 ps
CPU time 954.58 seconds
Started Aug 27 07:31:56 AM UTC 24
Finished Aug 27 07:48:02 AM UTC 24
Peak memory 2773168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016190274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3016190274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1045543698
Short name T1662
Test name
Test status
Simulation time 434662599 ps
CPU time 10.62 seconds
Started Aug 27 07:31:48 AM UTC 24
Finished Aug 27 07:32:00 AM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045543698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1045543698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3761133132
Short name T1675
Test name
Test status
Simulation time 2846622182 ps
CPU time 4.25 seconds
Started Aug 27 07:32:18 AM UTC 24
Finished Aug 27 07:32:24 AM UTC 24
Peak memory 231024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3761133132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad
dr.3761133132
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.4093905143
Short name T1668
Test name
Test status
Simulation time 182203307 ps
CPU time 2.03 seconds
Started Aug 27 07:32:12 AM UTC 24
Finished Aug 27 07:32:15 AM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093905
143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.4093905143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1119296106
Short name T1669
Test name
Test status
Simulation time 331811930 ps
CPU time 1.77 seconds
Started Aug 27 07:32:14 AM UTC 24
Finished Aug 27 07:32:17 AM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119296
106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.1119296106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3885439264
Short name T1680
Test name
Test status
Simulation time 456806527 ps
CPU time 4.39 seconds
Started Aug 27 07:32:25 AM UTC 24
Finished Aug 27 07:32:30 AM UTC 24
Peak memory 216828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885439
264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar
ks_acq.3885439264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.4140648186
Short name T1678
Test name
Test status
Simulation time 610412646 ps
CPU time 2.21 seconds
Started Aug 27 07:32:25 AM UTC 24
Finished Aug 27 07:32:28 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140648
186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.4140648186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3600680779
Short name T1673
Test name
Test status
Simulation time 1188793893 ps
CPU time 2.67 seconds
Started Aug 27 07:32:19 AM UTC 24
Finished Aug 27 07:32:23 AM UTC 24
Peak memory 227112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600680
779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_hrst.3600680779
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.112783228
Short name T1667
Test name
Test status
Simulation time 911818118 ps
CPU time 5.95 seconds
Started Aug 27 07:32:03 AM UTC 24
Finished Aug 27 07:32:10 AM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112783
228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.112783228
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.4280251479
Short name T1687
Test name
Test status
Simulation time 13615742432 ps
CPU time 26.97 seconds
Started Aug 27 07:32:09 AM UTC 24
Finished Aug 27 07:32:37 AM UTC 24
Peak memory 454896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4280251479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres
s_wr.4280251479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.612792528
Short name T1684
Test name
Test status
Simulation time 899360701 ps
CPU time 4.7 seconds
Started Aug 27 07:32:28 AM UTC 24
Finished Aug 27 07:32:34 AM UTC 24
Peak memory 226732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6127925
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.612792528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2496302511
Short name T1685
Test name
Test status
Simulation time 564972479 ps
CPU time 3.75 seconds
Started Aug 27 07:32:29 AM UTC 24
Finished Aug 27 07:32:34 AM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496302
511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_ad
dr.2496302511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_perf.93478671
Short name T1674
Test name
Test status
Simulation time 1199836777 ps
CPU time 6.29 seconds
Started Aug 27 07:32:16 AM UTC 24
Finished Aug 27 07:32:24 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9347867
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.93478671
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3542119888
Short name T1681
Test name
Test status
Simulation time 1018405730 ps
CPU time 3.76 seconds
Started Aug 27 07:32:26 AM UTC 24
Finished Aug 27 07:32:31 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542119
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.3542119888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.1154135826
Short name T1670
Test name
Test status
Simulation time 973741186 ps
CPU time 19.05 seconds
Started Aug 27 07:31:57 AM UTC 24
Finished Aug 27 07:32:18 AM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154135826 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.1154135826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1465427815
Short name T1708
Test name
Test status
Simulation time 153095892996 ps
CPU time 63.72 seconds
Started Aug 27 07:32:17 AM UTC 24
Finished Aug 27 07:33:23 AM UTC 24
Peak memory 317716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146542
7815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.1465427815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3223085310
Short name T1701
Test name
Test status
Simulation time 1489992874 ps
CPU time 68.28 seconds
Started Aug 27 07:32:00 AM UTC 24
Finished Aug 27 07:33:11 AM UTC 24
Peak memory 230856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223085310 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.3223085310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1526561
Short name T1753
Test name
Test status
Simulation time 57259184188 ps
CPU time 930.31 seconds
Started Aug 27 07:31:59 AM UTC 24
Finished Aug 27 07:47:39 AM UTC 24
Peak memory 9220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526561 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1526561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.3855414259
Short name T1665
Test name
Test status
Simulation time 3021681698 ps
CPU time 5.07 seconds
Started Aug 27 07:32:02 AM UTC 24
Finished Aug 27 07:32:08 AM UTC 24
Peak memory 252124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855414259 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.3855414259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.817699713
Short name T1676
Test name
Test status
Simulation time 1457489188 ps
CPU time 14.96 seconds
Started Aug 27 07:32:09 AM UTC 24
Finished Aug 27 07:32:25 AM UTC 24
Peak memory 243820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8176997
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.817699713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.2934233534
Short name T1683
Test name
Test status
Simulation time 292775412 ps
CPU time 6.65 seconds
Started Aug 27 07:32:26 AM UTC 24
Finished Aug 27 07:32:34 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934233
534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2934233534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_alert_test.664362560
Short name T1721
Test name
Test status
Simulation time 136546502 ps
CPU time 0.84 seconds
Started Aug 27 07:33:31 AM UTC 24
Finished Aug 27 07:33:32 AM UTC 24
Peak memory 215820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664362560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.664362560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.3819276250
Short name T1693
Test name
Test status
Simulation time 145451589 ps
CPU time 2.45 seconds
Started Aug 27 07:32:45 AM UTC 24
Finished Aug 27 07:32:49 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819276250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3819276250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1833976175
Short name T1690
Test name
Test status
Simulation time 293751145 ps
CPU time 6.97 seconds
Started Aug 27 07:32:35 AM UTC 24
Finished Aug 27 07:32:43 AM UTC 24
Peak memory 276568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833976175 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.1833976175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2440628873
Short name T1726
Test name
Test status
Simulation time 2282670320 ps
CPU time 74.57 seconds
Started Aug 27 07:32:38 AM UTC 24
Finished Aug 27 07:33:54 AM UTC 24
Peak memory 688292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440628873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2440628873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1800459237
Short name T1736
Test name
Test status
Simulation time 4222444144 ps
CPU time 122.16 seconds
Started Aug 27 07:32:35 AM UTC 24
Finished Aug 27 07:34:39 AM UTC 24
Peak memory 711072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800459237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1800459237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2100916384
Short name T1688
Test name
Test status
Simulation time 491949780 ps
CPU time 1.79 seconds
Started Aug 27 07:32:35 AM UTC 24
Finished Aug 27 07:32:38 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100916384 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.2100916384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1900652331
Short name T1691
Test name
Test status
Simulation time 177933278 ps
CPU time 5.12 seconds
Started Aug 27 07:32:38 AM UTC 24
Finished Aug 27 07:32:44 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900652331 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.1900652331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2202469309
Short name T1739
Test name
Test status
Simulation time 14514634486 ps
CPU time 169.92 seconds
Started Aug 27 07:32:35 AM UTC 24
Finished Aug 27 07:35:27 AM UTC 24
Peak memory 889012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202469309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2202469309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2760940251
Short name T1724
Test name
Test status
Simulation time 397943456 ps
CPU time 16.34 seconds
Started Aug 27 07:33:23 AM UTC 24
Finished Aug 27 07:33:40 AM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760940251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2760940251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2067174630
Short name T1707
Test name
Test status
Simulation time 388906973 ps
CPU time 1.75 seconds
Started Aug 27 07:33:19 AM UTC 24
Finished Aug 27 07:33:22 AM UTC 24
Peak memory 226516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067174630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2067174630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_override.2895734814
Short name T1686
Test name
Test status
Simulation time 16135871 ps
CPU time 1.08 seconds
Started Aug 27 07:32:35 AM UTC 24
Finished Aug 27 07:32:37 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895734814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2895734814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_perf.179443066
Short name T1698
Test name
Test status
Simulation time 14770578520 ps
CPU time 19.36 seconds
Started Aug 27 07:32:38 AM UTC 24
Finished Aug 27 07:32:59 AM UTC 24
Peak memory 436424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179443066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.179443066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3689830853
Short name T1731
Test name
Test status
Simulation time 5801775302 ps
CPU time 95.55 seconds
Started Aug 27 07:32:42 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 216952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689830853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3689830853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1576885151
Short name T1730
Test name
Test status
Simulation time 8586521471 ps
CPU time 106.49 seconds
Started Aug 27 07:32:31 AM UTC 24
Finished Aug 27 07:34:20 AM UTC 24
Peak memory 350420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576885151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1576885151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.2160991267
Short name T1699
Test name
Test status
Simulation time 3590381787 ps
CPU time 15.43 seconds
Started Aug 27 07:32:44 AM UTC 24
Finished Aug 27 07:33:01 AM UTC 24
Peak memory 243668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160991267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2160991267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.112687109
Short name T1714
Test name
Test status
Simulation time 1241605635 ps
CPU time 11.33 seconds
Started Aug 27 07:33:17 AM UTC 24
Finished Aug 27 07:33:29 AM UTC 24
Peak memory 233552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=112687109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.112687109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1335330285
Short name T1703
Test name
Test status
Simulation time 168608450 ps
CPU time 1.96 seconds
Started Aug 27 07:33:11 AM UTC 24
Finished Aug 27 07:33:15 AM UTC 24
Peak memory 226552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335330
285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.1335330285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.196790667
Short name T1705
Test name
Test status
Simulation time 258608327 ps
CPU time 1.4 seconds
Started Aug 27 07:33:14 AM UTC 24
Finished Aug 27 07:33:17 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967906
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.196790667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.3886094629
Short name T1717
Test name
Test status
Simulation time 1124760114 ps
CPU time 5 seconds
Started Aug 27 07:33:24 AM UTC 24
Finished Aug 27 07:33:30 AM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886094
629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermar
ks_acq.3886094629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.4072496250
Short name T1713
Test name
Test status
Simulation time 85488840 ps
CPU time 1.3 seconds
Started Aug 27 07:33:25 AM UTC 24
Finished Aug 27 07:33:27 AM UTC 24
Peak memory 214508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072496
250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark
s_tx.4072496250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1455445311
Short name T1700
Test name
Test status
Simulation time 1017115002 ps
CPU time 9.89 seconds
Started Aug 27 07:32:58 AM UTC 24
Finished Aug 27 07:33:09 AM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145544
5311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.1455445311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1044324681
Short name T1732
Test name
Test status
Simulation time 8309490344 ps
CPU time 86.73 seconds
Started Aug 27 07:32:59 AM UTC 24
Finished Aug 27 07:34:28 AM UTC 24
Peak memory 2234652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1044324681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stres
s_wr.1044324681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1768137704
Short name T1711
Test name
Test status
Simulation time 522171537 ps
CPU time 3.46 seconds
Started Aug 27 07:33:28 AM UTC 24
Finished Aug 27 07:33:33 AM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768137
704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.1768137704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2390848492
Short name T1722
Test name
Test status
Simulation time 2048266555 ps
CPU time 4.21 seconds
Started Aug 27 07:33:29 AM UTC 24
Finished Aug 27 07:33:35 AM UTC 24
Peak memory 216668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390848
492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.2390848492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1201530968
Short name T1716
Test name
Test status
Simulation time 810618324 ps
CPU time 2.42 seconds
Started Aug 27 07:33:30 AM UTC 24
Finished Aug 27 07:33:34 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201530
968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.1201530968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_perf.270233985
Short name T1709
Test name
Test status
Simulation time 861200230 ps
CPU time 7.79 seconds
Started Aug 27 07:33:15 AM UTC 24
Finished Aug 27 07:33:25 AM UTC 24
Peak memory 232944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702339
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.270233985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.4197081863
Short name T1720
Test name
Test status
Simulation time 1874834829 ps
CPU time 3.5 seconds
Started Aug 27 07:33:27 AM UTC 24
Finished Aug 27 07:33:32 AM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197081
863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.4197081863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.914927803
Short name T97
Test name
Test status
Simulation time 1234630851 ps
CPU time 37.4 seconds
Started Aug 27 07:32:52 AM UTC 24
Finished Aug 27 07:33:30 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914927803 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.914927803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.3767758819
Short name T1747
Test name
Test status
Simulation time 30108949904 ps
CPU time 401.76 seconds
Started Aug 27 07:33:15 AM UTC 24
Finished Aug 27 07:40:02 AM UTC 24
Peak memory 3770776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376775
8819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.3767758819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3980371484
Short name T1704
Test name
Test status
Simulation time 882682945 ps
CPU time 19.4 seconds
Started Aug 27 07:32:55 AM UTC 24
Finished Aug 27 07:33:16 AM UTC 24
Peak memory 233544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980371484 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.3980371484
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.503069319
Short name T1729
Test name
Test status
Simulation time 37615716728 ps
CPU time 83.12 seconds
Started Aug 27 07:32:53 AM UTC 24
Finished Aug 27 07:34:18 AM UTC 24
Peak memory 1311132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503069319 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.503069319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1728488026
Short name T1706
Test name
Test status
Simulation time 1219193409 ps
CPU time 18.65 seconds
Started Aug 27 07:32:58 AM UTC 24
Finished Aug 27 07:33:18 AM UTC 24
Peak memory 458764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728488026 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.1728488026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.1823981928
Short name T1702
Test name
Test status
Simulation time 2177241440 ps
CPU time 11.33 seconds
Started Aug 27 07:33:02 AM UTC 24
Finished Aug 27 07:33:14 AM UTC 24
Peak memory 226980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823981
928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.1823981928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.892116404
Short name T1715
Test name
Test status
Simulation time 62090676 ps
CPU time 2.37 seconds
Started Aug 27 07:33:26 AM UTC 24
Finished Aug 27 07:33:29 AM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8921164
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.892116404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_alert_test.1156070877
Short name T130
Test name
Test status
Simulation time 16086767 ps
CPU time 0.99 seconds
Started Aug 27 07:05:10 AM UTC 24
Finished Aug 27 07:05:12 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156070877 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1156070877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.913691157
Short name T32
Test name
Test status
Simulation time 407978256 ps
CPU time 5.13 seconds
Started Aug 27 07:04:53 AM UTC 24
Finished Aug 27 07:04:59 AM UTC 24
Peak memory 246120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913691157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.913691157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.3868659093
Short name T371
Test name
Test status
Simulation time 398095626 ps
CPU time 26.73 seconds
Started Aug 27 07:04:50 AM UTC 24
Finished Aug 27 07:05:18 AM UTC 24
Peak memory 305092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868659093 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.3868659093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.2325802137
Short name T48
Test name
Test status
Simulation time 9152397377 ps
CPU time 113.26 seconds
Started Aug 27 07:04:51 AM UTC 24
Finished Aug 27 07:06:47 AM UTC 24
Peak memory 401496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325802137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2325802137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2130443031
Short name T481
Test name
Test status
Simulation time 11824194629 ps
CPU time 157.44 seconds
Started Aug 27 07:04:49 AM UTC 24
Finished Aug 27 07:07:29 AM UTC 24
Peak memory 823572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130443031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2130443031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.1054899531
Short name T178
Test name
Test status
Simulation time 129354623 ps
CPU time 9.43 seconds
Started Aug 27 07:04:50 AM UTC 24
Finished Aug 27 07:05:01 AM UTC 24
Peak memory 237580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054899531 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.1054899531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.1429599620
Short name T90
Test name
Test status
Simulation time 7515863355 ps
CPU time 95.72 seconds
Started Aug 27 07:04:49 AM UTC 24
Finished Aug 27 07:06:27 AM UTC 24
Peak memory 1368284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429599620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1429599620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.727555461
Short name T272
Test name
Test status
Simulation time 1134192802 ps
CPU time 7.05 seconds
Started Aug 27 07:05:06 AM UTC 24
Finished Aug 27 07:05:14 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727555461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.727555461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_mode_toggle.3377635901
Short name T28
Test name
Test status
Simulation time 909962662 ps
CPU time 2.07 seconds
Started Aug 27 07:05:05 AM UTC 24
Finished Aug 27 07:05:08 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377635901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3377635901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_override.213153032
Short name T361
Test name
Test status
Simulation time 46758060 ps
CPU time 0.98 seconds
Started Aug 27 07:04:49 AM UTC 24
Finished Aug 27 07:04:51 AM UTC 24
Peak memory 214224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213153032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.213153032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_perf.1903318975
Short name T18
Test name
Test status
Simulation time 7419471281 ps
CPU time 27.29 seconds
Started Aug 27 07:04:51 AM UTC 24
Finished Aug 27 07:05:20 AM UTC 24
Peak memory 231236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903318975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1903318975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.2516778583
Short name T19
Test name
Test status
Simulation time 5855006774 ps
CPU time 59.71 seconds
Started Aug 27 07:04:51 AM UTC 24
Finished Aug 27 07:05:53 AM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516778583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2516778583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.1935970749
Short name T370
Test name
Test status
Simulation time 1526999914 ps
CPU time 27.51 seconds
Started Aug 27 07:04:49 AM UTC 24
Finished Aug 27 07:05:18 AM UTC 24
Peak memory 315464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935970749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1935970749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.679002063
Short name T368
Test name
Test status
Simulation time 530332066 ps
CPU time 20.64 seconds
Started Aug 27 07:04:53 AM UTC 24
Finished Aug 27 07:05:14 AM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679002063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.679002063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.2795427646
Short name T194
Test name
Test status
Simulation time 1601583845 ps
CPU time 5.52 seconds
Started Aug 27 07:05:02 AM UTC 24
Finished Aug 27 07:05:09 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2795427646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2795427646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.3702084042
Short name T347
Test name
Test status
Simulation time 231063267 ps
CPU time 2.24 seconds
Started Aug 27 07:05:00 AM UTC 24
Finished Aug 27 07:05:03 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702084
042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.3702084042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.3266565911
Short name T182
Test name
Test status
Simulation time 947618460 ps
CPU time 3.33 seconds
Started Aug 27 07:05:01 AM UTC 24
Finished Aug 27 07:05:05 AM UTC 24
Peak memory 220936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266565
911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.3266565911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.565343587
Short name T367
Test name
Test status
Simulation time 1767310935 ps
CPU time 2.7 seconds
Started Aug 27 07:05:06 AM UTC 24
Finished Aug 27 07:05:10 AM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5653435
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_acq.565343587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.1173809487
Short name T183
Test name
Test status
Simulation time 70166349 ps
CPU time 1.13 seconds
Started Aug 27 07:05:06 AM UTC 24
Finished Aug 27 07:05:08 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173809
487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_tx.1173809487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.4270204732
Short name T331
Test name
Test status
Simulation time 1535897317 ps
CPU time 8.64 seconds
Started Aug 27 07:04:55 AM UTC 24
Finished Aug 27 07:05:04 AM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427020
4732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.4270204732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.287883230
Short name T129
Test name
Test status
Simulation time 541818964 ps
CPU time 3.28 seconds
Started Aug 27 07:05:08 AM UTC 24
Finished Aug 27 07:05:12 AM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878832
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.287883230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.1542376625
Short name T135
Test name
Test status
Simulation time 517384156 ps
CPU time 4.02 seconds
Started Aug 27 07:05:08 AM UTC 24
Finished Aug 27 07:05:13 AM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542376
625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.1542376625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.2819470975
Short name T131
Test name
Test status
Simulation time 887161676 ps
CPU time 2.27 seconds
Started Aug 27 07:05:09 AM UTC 24
Finished Aug 27 07:05:12 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819470
975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_txstretch.2819470975
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_perf.2345427495
Short name T338
Test name
Test status
Simulation time 654965616 ps
CPU time 6.87 seconds
Started Aug 27 07:05:01 AM UTC 24
Finished Aug 27 07:05:09 AM UTC 24
Peak memory 229064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345427
495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.2345427495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.625989367
Short name T128
Test name
Test status
Simulation time 1255239161 ps
CPU time 3.3 seconds
Started Aug 27 07:05:07 AM UTC 24
Finished Aug 27 07:05:12 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6259893
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.625989367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.239610531
Short name T136
Test name
Test status
Simulation time 936196163 ps
CPU time 17.89 seconds
Started Aug 27 07:04:54 AM UTC 24
Finished Aug 27 07:05:13 AM UTC 24
Peak memory 226860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239610531 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.239610531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.2361768548
Short name T549
Test name
Test status
Simulation time 24193833971 ps
CPU time 204.6 seconds
Started Aug 27 07:05:02 AM UTC 24
Finished Aug 27 07:08:30 AM UTC 24
Peak memory 2599068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236176
8548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.2361768548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1046655651
Short name T324
Test name
Test status
Simulation time 279908077 ps
CPU time 6.89 seconds
Started Aug 27 07:04:54 AM UTC 24
Finished Aug 27 07:05:02 AM UTC 24
Peak memory 216548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046655651 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.1046655651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.1977995961
Short name T180
Test name
Test status
Simulation time 16239603132 ps
CPU time 6.67 seconds
Started Aug 27 07:04:54 AM UTC 24
Finished Aug 27 07:05:01 AM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977995961 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.1977995961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.1280174
Short name T351
Test name
Test status
Simulation time 6344022558 ps
CPU time 11.05 seconds
Started Aug 27 07:04:55 AM UTC 24
Finished Aug 27 07:05:07 AM UTC 24
Peak memory 387296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280174 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.1280174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2181495645
Short name T327
Test name
Test status
Simulation time 1825450884 ps
CPU time 6.96 seconds
Started Aug 27 07:04:58 AM UTC 24
Finished Aug 27 07:05:06 AM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181495
645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.2181495645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_alert_test.2990277326
Short name T379
Test name
Test status
Simulation time 45654809 ps
CPU time 0.93 seconds
Started Aug 27 07:05:26 AM UTC 24
Finished Aug 27 07:05:28 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990277326 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2990277326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.509675587
Short name T22
Test name
Test status
Simulation time 267559652 ps
CPU time 3.8 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:05:18 AM UTC 24
Peak memory 250088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509675587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.509675587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.3399579003
Short name T394
Test name
Test status
Simulation time 1585281000 ps
CPU time 25.85 seconds
Started Aug 27 07:05:12 AM UTC 24
Finished Aug 27 07:05:39 AM UTC 24
Peak memory 327972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399579003 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.3399579003
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.1290287335
Short name T462
Test name
Test status
Simulation time 12567606474 ps
CPU time 115.2 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:07:11 AM UTC 24
Peak memory 866468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290287335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1290287335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.3497794439
Short name T453
Test name
Test status
Simulation time 25126980508 ps
CPU time 106.91 seconds
Started Aug 27 07:05:11 AM UTC 24
Finished Aug 27 07:07:00 AM UTC 24
Peak memory 667880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497794439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3497794439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.833585796
Short name T254
Test name
Test status
Simulation time 238145555 ps
CPU time 1.51 seconds
Started Aug 27 07:05:12 AM UTC 24
Finished Aug 27 07:05:14 AM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833585796 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.833585796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.271151131
Short name T190
Test name
Test status
Simulation time 169724493 ps
CPU time 4.75 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:05:19 AM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271151131 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.271151131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.3731771920
Short name T637
Test name
Test status
Simulation time 5969094280 ps
CPU time 280.8 seconds
Started Aug 27 07:05:10 AM UTC 24
Finished Aug 27 07:09:55 AM UTC 24
Peak memory 1358140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731771920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3731771920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.3681276591
Short name T40
Test name
Test status
Simulation time 217533585 ps
CPU time 4.06 seconds
Started Aug 27 07:05:22 AM UTC 24
Finished Aug 27 07:05:28 AM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681276591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3681276591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_override.1730811311
Short name T132
Test name
Test status
Simulation time 27736419 ps
CPU time 1.06 seconds
Started Aug 27 07:05:10 AM UTC 24
Finished Aug 27 07:05:12 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730811311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1730811311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_perf.2019647524
Short name T883
Test name
Test status
Simulation time 98991582462 ps
CPU time 513.15 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:13:53 AM UTC 24
Peak memory 2961628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019647524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2019647524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.1798454970
Short name T249
Test name
Test status
Simulation time 215840047 ps
CPU time 10.95 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:05:25 AM UTC 24
Peak memory 241788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798454970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1798454970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.3516390734
Short name T282
Test name
Test status
Simulation time 5773476250 ps
CPU time 29.12 seconds
Started Aug 27 07:05:10 AM UTC 24
Finished Aug 27 07:05:40 AM UTC 24
Peak memory 364804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516390734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3516390734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.3379166763
Short name T391
Test name
Test status
Simulation time 990103829 ps
CPU time 21.44 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:05:36 AM UTC 24
Peak memory 232984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379166763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3379166763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.2074791942
Short name T382
Test name
Test status
Simulation time 1168366034 ps
CPU time 7.64 seconds
Started Aug 27 07:05:20 AM UTC 24
Finished Aug 27 07:05:29 AM UTC 24
Peak memory 226852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2074791942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2074791942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.1885616921
Short name T372
Test name
Test status
Simulation time 173501808 ps
CPU time 1.19 seconds
Started Aug 27 07:05:17 AM UTC 24
Finished Aug 27 07:05:19 AM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885616
921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.1885616921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.2778700623
Short name T374
Test name
Test status
Simulation time 194183026 ps
CPU time 1.34 seconds
Started Aug 27 07:05:19 AM UTC 24
Finished Aug 27 07:05:21 AM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778700
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.2778700623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.4003683847
Short name T380
Test name
Test status
Simulation time 3776142705 ps
CPU time 3.67 seconds
Started Aug 27 07:05:24 AM UTC 24
Finished Aug 27 07:05:28 AM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003683
847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark
s_acq.4003683847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1889012306
Short name T378
Test name
Test status
Simulation time 63299543 ps
CPU time 1.49 seconds
Started Aug 27 07:05:25 AM UTC 24
Finished Aug 27 07:05:27 AM UTC 24
Peak memory 216344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889012
306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_tx.1889012306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_hrst.2438232472
Short name T377
Test name
Test status
Simulation time 289875176 ps
CPU time 3.89 seconds
Started Aug 27 07:05:20 AM UTC 24
Finished Aug 27 07:05:25 AM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438232
472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_hrst.2438232472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.252887668
Short name T375
Test name
Test status
Simulation time 680639123 ps
CPU time 6.65 seconds
Started Aug 27 07:05:16 AM UTC 24
Finished Aug 27 07:05:23 AM UTC 24
Peak memory 230792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252887
668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.252887668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.3949460909
Short name T703
Test name
Test status
Simulation time 20145446198 ps
CPU time 340.26 seconds
Started Aug 27 07:05:16 AM UTC 24
Finished Aug 27 07:11:00 AM UTC 24
Peak memory 5093656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3949460909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress
_wr.3949460909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.4100624305
Short name T59
Test name
Test status
Simulation time 604203078 ps
CPU time 5.09 seconds
Started Aug 27 07:05:26 AM UTC 24
Finished Aug 27 07:05:32 AM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100624
305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.4100624305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.1444526942
Short name T386
Test name
Test status
Simulation time 1719280829 ps
CPU time 4.5 seconds
Started Aug 27 07:05:26 AM UTC 24
Finished Aug 27 07:05:31 AM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444526
942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.1444526942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.2179080239
Short name T188
Test name
Test status
Simulation time 218494323 ps
CPU time 2.35 seconds
Started Aug 27 07:05:26 AM UTC 24
Finished Aug 27 07:05:29 AM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179080
239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.2179080239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_perf.679629428
Short name T376
Test name
Test status
Simulation time 6125884449 ps
CPU time 4.47 seconds
Started Aug 27 07:05:19 AM UTC 24
Finished Aug 27 07:05:25 AM UTC 24
Peak memory 218872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6796294
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.679629428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2803050724
Short name T384
Test name
Test status
Simulation time 1137151039 ps
CPU time 3.04 seconds
Started Aug 27 07:05:26 AM UTC 24
Finished Aug 27 07:05:30 AM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803050
724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.2803050724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1055765874
Short name T198
Test name
Test status
Simulation time 854263785 ps
CPU time 11.85 seconds
Started Aug 27 07:05:13 AM UTC 24
Finished Aug 27 07:05:26 AM UTC 24
Peak memory 226400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055765874 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.1055765874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.3958894166
Short name T640
Test name
Test status
Simulation time 30351058797 ps
CPU time 276.72 seconds
Started Aug 27 07:05:19 AM UTC 24
Finished Aug 27 07:09:59 AM UTC 24
Peak memory 2904212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395889
4166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.3958894166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.3545825127
Short name T390
Test name
Test status
Simulation time 1387323943 ps
CPU time 19.24 seconds
Started Aug 27 07:05:15 AM UTC 24
Finished Aug 27 07:05:35 AM UTC 24
Peak memory 243808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545825127 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.3545825127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.1091413367
Short name T575
Test name
Test status
Simulation time 60229322665 ps
CPU time 212.96 seconds
Started Aug 27 07:05:14 AM UTC 24
Finished Aug 27 07:08:50 AM UTC 24
Peak memory 2578712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091413367 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.1091413367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.1030743761
Short name T283
Test name
Test status
Simulation time 2753865043 ps
CPU time 8.16 seconds
Started Aug 27 07:05:15 AM UTC 24
Finished Aug 27 07:05:24 AM UTC 24
Peak memory 280716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030743761 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.1030743761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.1630107541
Short name T385
Test name
Test status
Simulation time 2802539882 ps
CPU time 12.34 seconds
Started Aug 27 07:05:17 AM UTC 24
Finished Aug 27 07:05:31 AM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630107
541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.1630107541
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.4033314212
Short name T381
Test name
Test status
Simulation time 99751199 ps
CPU time 2.86 seconds
Started Aug 27 07:05:25 AM UTC 24
Finished Aug 27 07:05:28 AM UTC 24
Peak memory 216420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033314
212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.4033314212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_alert_test.2088779040
Short name T389
Test name
Test status
Simulation time 33116576 ps
CPU time 1 seconds
Started Aug 27 07:05:49 AM UTC 24
Finished Aug 27 07:05:51 AM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088779040 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2088779040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.3934682180
Short name T34
Test name
Test status
Simulation time 117478796 ps
CPU time 2.27 seconds
Started Aug 27 07:05:32 AM UTC 24
Finished Aug 27 07:05:35 AM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934682180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3934682180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.660873265
Short name T393
Test name
Test status
Simulation time 461150208 ps
CPU time 7.23 seconds
Started Aug 27 07:05:29 AM UTC 24
Finished Aug 27 07:05:37 AM UTC 24
Peak memory 295252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660873265 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.660873265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.1260673653
Short name T572
Test name
Test status
Simulation time 13309331420 ps
CPU time 192.96 seconds
Started Aug 27 07:05:30 AM UTC 24
Finished Aug 27 07:08:46 AM UTC 24
Peak memory 780552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260673653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1260673653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.961225047
Short name T514
Test name
Test status
Simulation time 7727154490 ps
CPU time 141.31 seconds
Started Aug 27 07:05:28 AM UTC 24
Finished Aug 27 07:07:52 AM UTC 24
Peak memory 723404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961225047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.961225047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2988281994
Short name T387
Test name
Test status
Simulation time 311666003 ps
CPU time 1.48 seconds
Started Aug 27 07:05:29 AM UTC 24
Finished Aug 27 07:05:32 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988281994 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.2988281994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.507119169
Short name T191
Test name
Test status
Simulation time 273353125 ps
CPU time 3.83 seconds
Started Aug 27 07:05:29 AM UTC 24
Finished Aug 27 07:05:34 AM UTC 24
Peak memory 239756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507119169 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.507119169
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.2143390529
Short name T122
Test name
Test status
Simulation time 10666467830 ps
CPU time 103.55 seconds
Started Aug 27 07:05:28 AM UTC 24
Finished Aug 27 07:07:14 AM UTC 24
Peak memory 1556616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143390529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2143390529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_mode_toggle.3011489782
Short name T29
Test name
Test status
Simulation time 134318338 ps
CPU time 1.69 seconds
Started Aug 27 07:05:43 AM UTC 24
Finished Aug 27 07:05:45 AM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011489782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3011489782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_override.2915171472
Short name T383
Test name
Test status
Simulation time 90380187 ps
CPU time 0.97 seconds
Started Aug 27 07:05:27 AM UTC 24
Finished Aug 27 07:05:29 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915171472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2915171472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_perf.3607274734
Short name T392
Test name
Test status
Simulation time 852518713 ps
CPU time 5.86 seconds
Started Aug 27 07:05:30 AM UTC 24
Finished Aug 27 07:05:37 AM UTC 24
Peak memory 242044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607274734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3607274734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.1765151937
Short name T388
Test name
Test status
Simulation time 42978915 ps
CPU time 2.03 seconds
Started Aug 27 07:05:30 AM UTC 24
Finished Aug 27 07:05:33 AM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765151937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.1765151937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.2156676735
Short name T454
Test name
Test status
Simulation time 2251184387 ps
CPU time 91.9 seconds
Started Aug 27 07:05:27 AM UTC 24
Finished Aug 27 07:07:01 AM UTC 24
Peak memory 325792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156676735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2156676735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.2574992589
Short name T398
Test name
Test status
Simulation time 1192534568 ps
CPU time 11.88 seconds
Started Aug 27 07:05:31 AM UTC 24
Finished Aug 27 07:05:44 AM UTC 24
Peak memory 232916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574992589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2574992589
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1797949527
Short name T181
Test name
Test status
Simulation time 1305520768 ps
CPU time 9.79 seconds
Started Aug 27 07:05:39 AM UTC 24
Finished Aug 27 07:05:50 AM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1797949527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1797949527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.4232153969
Short name T395
Test name
Test status
Simulation time 206638854 ps
CPU time 2.24 seconds
Started Aug 27 07:05:38 AM UTC 24
Finished Aug 27 07:05:41 AM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232153
969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.4232153969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.4204485272
Short name T396
Test name
Test status
Simulation time 912170859 ps
CPU time 2.91 seconds
Started Aug 27 07:05:38 AM UTC 24
Finished Aug 27 07:05:42 AM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204485
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.4204485272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.1116962431
Short name T401
Test name
Test status
Simulation time 4248200156 ps
CPU time 6.78 seconds
Started Aug 27 07:05:44 AM UTC 24
Finished Aug 27 07:05:52 AM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116962
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark
s_acq.1116962431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.1015897955
Short name T403
Test name
Test status
Simulation time 218487355 ps
CPU time 1.92 seconds
Started Aug 27 07:05:45 AM UTC 24
Finished Aug 27 07:05:48 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015897
955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_tx.1015897955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.2151823685
Short name T399
Test name
Test status
Simulation time 286889511 ps
CPU time 3.49 seconds
Started Aug 27 07:05:40 AM UTC 24
Finished Aug 27 07:05:45 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151823
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.2151823685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.2230944514
Short name T400
Test name
Test status
Simulation time 1411318168 ps
CPU time 9.25 seconds
Started Aug 27 07:05:36 AM UTC 24
Finished Aug 27 07:05:46 AM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223094
4514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.2230944514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.3743659931
Short name T64
Test name
Test status
Simulation time 11145161933 ps
CPU time 11.88 seconds
Started Aug 27 07:05:36 AM UTC 24
Finished Aug 27 07:05:49 AM UTC 24
Peak memory 311700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3743659931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress
_wr.3743659931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.894156542
Short name T184
Test name
Test status
Simulation time 2844332428 ps
CPU time 4.66 seconds
Started Aug 27 07:05:46 AM UTC 24
Finished Aug 27 07:05:52 AM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8941565
42 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.894156542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.2509822538
Short name T134
Test name
Test status
Simulation time 505989487 ps
CPU time 3.45 seconds
Started Aug 27 07:05:47 AM UTC 24
Finished Aug 27 07:05:52 AM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509822
538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.2509822538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_perf.3220977886
Short name T402
Test name
Test status
Simulation time 8925273143 ps
CPU time 6.24 seconds
Started Aug 27 07:05:39 AM UTC 24
Finished Aug 27 07:05:47 AM UTC 24
Peak memory 233992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220977
886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.3220977886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.280339904
Short name T133
Test name
Test status
Simulation time 1125436456 ps
CPU time 2.63 seconds
Started Aug 27 07:05:46 AM UTC 24
Finished Aug 27 07:05:50 AM UTC 24
Peak memory 216108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803399
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.280339904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.1699650591
Short name T397
Test name
Test status
Simulation time 1389979713 ps
CPU time 9.14 seconds
Started Aug 27 07:05:33 AM UTC 24
Finished Aug 27 07:05:43 AM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699650591 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.1699650591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.382992060
Short name T1185
Test name
Test status
Simulation time 46081397053 ps
CPU time 907.67 seconds
Started Aug 27 07:05:39 AM UTC 24
Finished Aug 27 07:20:56 AM UTC 24
Peak memory 8030540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382992
060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.382992060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.1239805607
Short name T411
Test name
Test status
Simulation time 14074086506 ps
CPU time 24.27 seconds
Started Aug 27 07:05:34 AM UTC 24
Finished Aug 27 07:05:59 AM UTC 24
Peak memory 250116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239805607 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.1239805607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.2996617273
Short name T767
Test name
Test status
Simulation time 54795704750 ps
CPU time 384.7 seconds
Started Aug 27 07:05:33 AM UTC 24
Finished Aug 27 07:12:02 AM UTC 24
Peak memory 4501724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996617273 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.2996617273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.4148437165
Short name T409
Test name
Test status
Simulation time 1343493626 ps
CPU time 20.98 seconds
Started Aug 27 07:05:35 AM UTC 24
Finished Aug 27 07:05:57 AM UTC 24
Peak memory 446784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148437165 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.4148437165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.2157154386
Short name T404
Test name
Test status
Simulation time 15255244159 ps
CPU time 12.61 seconds
Started Aug 27 07:05:36 AM UTC 24
Finished Aug 27 07:05:50 AM UTC 24
Peak memory 233716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157154
386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.2157154386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.2786348976
Short name T407
Test name
Test status
Simulation time 384139441 ps
CPU time 7.77 seconds
Started Aug 27 07:05:46 AM UTC 24
Finished Aug 27 07:05:55 AM UTC 24
Peak memory 216396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786348
976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2786348976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_alert_test.1586799042
Short name T423
Test name
Test status
Simulation time 38594614 ps
CPU time 0.97 seconds
Started Aug 27 07:06:12 AM UTC 24
Finished Aug 27 07:06:14 AM UTC 24
Peak memory 215084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586799042 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1586799042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.330469197
Short name T37
Test name
Test status
Simulation time 177646867 ps
CPU time 2.08 seconds
Started Aug 27 07:05:53 AM UTC 24
Finished Aug 27 07:05:56 AM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330469197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.330469197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.350704356
Short name T431
Test name
Test status
Simulation time 447746372 ps
CPU time 26.45 seconds
Started Aug 27 07:05:51 AM UTC 24
Finished Aug 27 07:06:19 AM UTC 24
Peak memory 317536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350704356 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.350704356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.3655103009
Short name T170
Test name
Test status
Simulation time 5028376463 ps
CPU time 64.65 seconds
Started Aug 27 07:05:52 AM UTC 24
Finished Aug 27 07:06:58 AM UTC 24
Peak memory 573644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655103009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3655103009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.2955234444
Short name T528
Test name
Test status
Simulation time 2254117053 ps
CPU time 134.53 seconds
Started Aug 27 07:05:50 AM UTC 24
Finished Aug 27 07:08:07 AM UTC 24
Peak memory 770284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955234444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2955234444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.2120010575
Short name T406
Test name
Test status
Simulation time 301175827 ps
CPU time 1.85 seconds
Started Aug 27 07:05:50 AM UTC 24
Finished Aug 27 07:05:53 AM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120010575 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.2120010575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.2874204703
Short name T410
Test name
Test status
Simulation time 145729502 ps
CPU time 5.48 seconds
Started Aug 27 07:05:51 AM UTC 24
Finished Aug 27 07:05:58 AM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874204703 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.2874204703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.97701393
Short name T673
Test name
Test status
Simulation time 9780771284 ps
CPU time 278.05 seconds
Started Aug 27 07:05:50 AM UTC 24
Finished Aug 27 07:10:32 AM UTC 24
Peak memory 1497116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97701393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.97701393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.742045482
Short name T47
Test name
Test status
Simulation time 1125953966 ps
CPU time 24.53 seconds
Started Aug 27 07:06:07 AM UTC 24
Finished Aug 27 07:06:33 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742045482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.742045482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.3279304262
Short name T85
Test name
Test status
Simulation time 381750379 ps
CPU time 5.02 seconds
Started Aug 27 07:06:05 AM UTC 24
Finished Aug 27 07:06:11 AM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279304262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3279304262
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_override.37776856
Short name T373
Test name
Test status
Simulation time 72895549 ps
CPU time 1.07 seconds
Started Aug 27 07:05:50 AM UTC 24
Finished Aug 27 07:05:52 AM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37776856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.37776856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_perf.419102437
Short name T251
Test name
Test status
Simulation time 3632523213 ps
CPU time 30.13 seconds
Started Aug 27 07:05:52 AM UTC 24
Finished Aug 27 07:06:23 AM UTC 24
Peak memory 250252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419102437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.419102437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.1248234599
Short name T408
Test name
Test status
Simulation time 165612824 ps
CPU time 1.68 seconds
Started Aug 27 07:05:53 AM UTC 24
Finished Aug 27 07:05:55 AM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248234599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.1248234599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.294390113
Short name T422
Test name
Test status
Simulation time 6014405235 ps
CPU time 23.84 seconds
Started Aug 27 07:05:49 AM UTC 24
Finished Aug 27 07:06:14 AM UTC 24
Peak memory 415976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294390113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.294390113
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.551368802
Short name T432
Test name
Test status
Simulation time 1198583414 ps
CPU time 25.92 seconds
Started Aug 27 07:05:53 AM UTC 24
Finished Aug 27 07:06:20 AM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551368802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.551368802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.3966832956
Short name T418
Test name
Test status
Simulation time 676185375 ps
CPU time 6.36 seconds
Started Aug 27 07:06:03 AM UTC 24
Finished Aug 27 07:06:10 AM UTC 24
Peak memory 233032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3966832956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3966832956
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.1723434574
Short name T413
Test name
Test status
Simulation time 192889482 ps
CPU time 2.12 seconds
Started Aug 27 07:05:59 AM UTC 24
Finished Aug 27 07:06:03 AM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723434
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.1723434574
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.4080600251
Short name T414
Test name
Test status
Simulation time 225603926 ps
CPU time 1.23 seconds
Started Aug 27 07:06:00 AM UTC 24
Finished Aug 27 07:06:03 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080600
251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.4080600251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.1748813210
Short name T417
Test name
Test status
Simulation time 1030964804 ps
CPU time 1.88 seconds
Started Aug 27 07:06:07 AM UTC 24
Finished Aug 27 07:06:10 AM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748813
210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermark
s_acq.1748813210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.2894186428
Short name T421
Test name
Test status
Simulation time 140024959 ps
CPU time 2.02 seconds
Started Aug 27 07:06:10 AM UTC 24
Finished Aug 27 07:06:13 AM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894186
428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_tx.2894186428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_hrst.2019632373
Short name T405
Test name
Test status
Simulation time 403347566 ps
CPU time 2.87 seconds
Started Aug 27 07:06:03 AM UTC 24
Finished Aug 27 07:06:07 AM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019632
373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_hrst.2019632373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.3392769060
Short name T412
Test name
Test status
Simulation time 622671043 ps
CPU time 4.61 seconds
Started Aug 27 07:05:56 AM UTC 24
Finished Aug 27 07:06:02 AM UTC 24
Peak memory 220808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339276
9060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.3392769060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.2604451856
Short name T429
Test name
Test status
Simulation time 17060895627 ps
CPU time 18.66 seconds
Started Aug 27 07:05:57 AM UTC 24
Finished Aug 27 07:06:17 AM UTC 24
Peak memory 331964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2604451856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.2604451856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.64761341
Short name T428
Test name
Test status
Simulation time 495475927 ps
CPU time 4.66 seconds
Started Aug 27 07:06:11 AM UTC 24
Finished Aug 27 07:06:17 AM UTC 24
Peak memory 226700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6476134
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.64761341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.176337762
Short name T427
Test name
Test status
Simulation time 1934268225 ps
CPU time 4.49 seconds
Started Aug 27 07:06:11 AM UTC 24
Finished Aug 27 07:06:17 AM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763377
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.176337762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.3840214523
Short name T189
Test name
Test status
Simulation time 164722423 ps
CPU time 2.49 seconds
Started Aug 27 07:06:11 AM UTC 24
Finished Aug 27 07:06:15 AM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840214
523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.3840214523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_perf.1877706557
Short name T420
Test name
Test status
Simulation time 736019737 ps
CPU time 8.59 seconds
Started Aug 27 07:06:00 AM UTC 24
Finished Aug 27 07:06:10 AM UTC 24
Peak memory 228872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877706
557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.1877706557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.2625504433
Short name T424
Test name
Test status
Simulation time 504818239 ps
CPU time 2.6 seconds
Started Aug 27 07:06:11 AM UTC 24
Finished Aug 27 07:06:15 AM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625504
433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.2625504433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.4091358065
Short name T416
Test name
Test status
Simulation time 2095058580 ps
CPU time 14.52 seconds
Started Aug 27 07:05:54 AM UTC 24
Finished Aug 27 07:06:10 AM UTC 24
Peak memory 226912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091358065 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.4091358065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.1169635889
Short name T286
Test name
Test status
Simulation time 21012708083 ps
CPU time 140.72 seconds
Started Aug 27 07:06:02 AM UTC 24
Finished Aug 27 07:08:25 AM UTC 24
Peak memory 2527456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116963
5889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.1169635889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.4077404514
Short name T435
Test name
Test status
Simulation time 1596194985 ps
CPU time 32 seconds
Started Aug 27 07:05:55 AM UTC 24
Finished Aug 27 07:06:28 AM UTC 24
Peak memory 243868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077404514 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.4077404514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.1707466947
Short name T541
Test name
Test status
Simulation time 48803035746 ps
CPU time 141.9 seconds
Started Aug 27 07:05:54 AM UTC 24
Finished Aug 27 07:08:18 AM UTC 24
Peak memory 1923168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707466947 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.1707466947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2321657258
Short name T415
Test name
Test status
Simulation time 1662210200 ps
CPU time 6.11 seconds
Started Aug 27 07:05:56 AM UTC 24
Finished Aug 27 07:06:04 AM UTC 24
Peak memory 284736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321657258 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.2321657258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.3200016567
Short name T419
Test name
Test status
Simulation time 4926337891 ps
CPU time 10.72 seconds
Started Aug 27 07:05:58 AM UTC 24
Finished Aug 27 07:06:10 AM UTC 24
Peak memory 233096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200016
567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.3200016567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.953842910
Short name T425
Test name
Test status
Simulation time 113436226 ps
CPU time 3.52 seconds
Started Aug 27 07:06:11 AM UTC 24
Finished Aug 27 07:06:16 AM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9538429
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.953842910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_alert_test.1405954831
Short name T445
Test name
Test status
Simulation time 16777943 ps
CPU time 0.95 seconds
Started Aug 27 07:06:52 AM UTC 24
Finished Aug 27 07:06:54 AM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405954831 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1405954831
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3335209783
Short name T23
Test name
Test status
Simulation time 71101972 ps
CPU time 1.75 seconds
Started Aug 27 07:06:19 AM UTC 24
Finished Aug 27 07:06:22 AM UTC 24
Peak memory 226372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335209783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3335209783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.2086889100
Short name T434
Test name
Test status
Simulation time 326324051 ps
CPU time 7.11 seconds
Started Aug 27 07:06:16 AM UTC 24
Finished Aug 27 07:06:24 AM UTC 24
Peak memory 280964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086889100 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.2086889100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.4074471400
Short name T483
Test name
Test status
Simulation time 2875733593 ps
CPU time 74.6 seconds
Started Aug 27 07:06:18 AM UTC 24
Finished Aug 27 07:07:34 AM UTC 24
Peak memory 432584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074471400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.4074471400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1541227854
Short name T529
Test name
Test status
Simulation time 2685097160 ps
CPU time 110.54 seconds
Started Aug 27 07:06:16 AM UTC 24
Finished Aug 27 07:08:08 AM UTC 24
Peak memory 700460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541227854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1541227854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.3493753099
Short name T430
Test name
Test status
Simulation time 564306655 ps
CPU time 1.77 seconds
Started Aug 27 07:06:16 AM UTC 24
Finished Aug 27 07:06:18 AM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493753099 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.3493753099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.261142753
Short name T433
Test name
Test status
Simulation time 141233738 ps
CPU time 3.81 seconds
Started Aug 27 07:06:17 AM UTC 24
Finished Aug 27 07:06:22 AM UTC 24
Peak memory 239760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261142753 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.261142753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.1305324352
Short name T711
Test name
Test status
Simulation time 4990114101 ps
CPU time 286.9 seconds
Started Aug 27 07:06:16 AM UTC 24
Finished Aug 27 07:11:07 AM UTC 24
Peak memory 1282276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305324352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1305324352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.848740173
Short name T261
Test name
Test status
Simulation time 2940152355 ps
CPU time 8.05 seconds
Started Aug 27 07:06:44 AM UTC 24
Finished Aug 27 07:06:53 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848740173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.848740173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_mode_toggle.530637472
Short name T436
Test name
Test status
Simulation time 96907829 ps
CPU time 3.82 seconds
Started Aug 27 07:06:43 AM UTC 24
Finished Aug 27 07:06:48 AM UTC 24
Peak memory 232984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530637472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.530637472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_override.1786484445
Short name T426
Test name
Test status
Simulation time 148429725 ps
CPU time 1.09 seconds
Started Aug 27 07:06:14 AM UTC 24
Finished Aug 27 07:06:16 AM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786484445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1786484445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_perf.3591375125
Short name T439
Test name
Test status
Simulation time 6197931151 ps
CPU time 30.99 seconds
Started Aug 27 07:06:18 AM UTC 24
Finished Aug 27 07:06:50 AM UTC 24
Peak memory 565576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591375125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3591375125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.2524375758
Short name T786
Test name
Test status
Simulation time 6071769697 ps
CPU time 353.65 seconds
Started Aug 27 07:06:18 AM UTC 24
Finished Aug 27 07:12:16 AM UTC 24
Peak memory 1614172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524375758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.2524375758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.473662766
Short name T145
Test name
Test status
Simulation time 3150297039 ps
CPU time 26.15 seconds
Started Aug 27 07:06:12 AM UTC 24
Finished Aug 27 07:06:40 AM UTC 24
Peak memory 325528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473662766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.473662766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.4188887676
Short name T442
Test name
Test status
Simulation time 572811594 ps
CPU time 32.73 seconds
Started Aug 27 07:06:18 AM UTC 24
Finished Aug 27 07:06:52 AM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188887676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.4188887676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.1230893515
Short name T147
Test name
Test status
Simulation time 2750868043 ps
CPU time 5.92 seconds
Started Aug 27 07:06:35 AM UTC 24
Finished Aug 27 07:06:42 AM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1230893515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1230893515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.1677485845
Short name T143
Test name
Test status
Simulation time 251770571 ps
CPU time 1.25 seconds
Started Aug 27 07:06:32 AM UTC 24
Finished Aug 27 07:06:34 AM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677485
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.1677485845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.1791005935
Short name T144
Test name
Test status
Simulation time 295553775 ps
CPU time 2.32 seconds
Started Aug 27 07:06:33 AM UTC 24
Finished Aug 27 07:06:36 AM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791005
935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.1791005935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.2473309240
Short name T438
Test name
Test status
Simulation time 2333862031 ps
CPU time 4.47 seconds
Started Aug 27 07:06:44 AM UTC 24
Finished Aug 27 07:06:50 AM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473309
240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermark
s_acq.2473309240
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.4000892157
Short name T440
Test name
Test status
Simulation time 151790940 ps
CPU time 2 seconds
Started Aug 27 07:06:47 AM UTC 24
Finished Aug 27 07:06:50 AM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000892
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_tx.4000892157
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.712564306
Short name T142
Test name
Test status
Simulation time 1790298718 ps
CPU time 7.51 seconds
Started Aug 27 07:06:24 AM UTC 24
Finished Aug 27 07:06:33 AM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712564
306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.712564306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1628095591
Short name T66
Test name
Test status
Simulation time 16523239796 ps
CPU time 27.94 seconds
Started Aug 27 07:06:24 AM UTC 24
Finished Aug 27 07:06:54 AM UTC 24
Peak memory 604464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1628095591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress
_wr.1628095591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.766039146
Short name T450
Test name
Test status
Simulation time 2293269862 ps
CPU time 4.83 seconds
Started Aug 27 07:06:51 AM UTC 24
Finished Aug 27 07:06:57 AM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7660391
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.766039146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3363893830
Short name T449
Test name
Test status
Simulation time 1803077045 ps
CPU time 2.94 seconds
Started Aug 27 07:06:51 AM UTC 24
Finished Aug 27 07:06:55 AM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363893
830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3363893830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_perf.2047378214
Short name T148
Test name
Test status
Simulation time 1265935915 ps
CPU time 8.31 seconds
Started Aug 27 07:06:34 AM UTC 24
Finished Aug 27 07:06:43 AM UTC 24
Peak memory 232900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047378
214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.2047378214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.2534735934
Short name T443
Test name
Test status
Simulation time 564074447 ps
CPU time 2.9 seconds
Started Aug 27 07:06:49 AM UTC 24
Finished Aug 27 07:06:52 AM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534735
934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.2534735934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.3305541512
Short name T448
Test name
Test status
Simulation time 951778751 ps
CPU time 32.02 seconds
Started Aug 27 07:06:21 AM UTC 24
Finished Aug 27 07:06:55 AM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305541512 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.3305541512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.1763337414
Short name T456
Test name
Test status
Simulation time 9284030299 ps
CPU time 29.17 seconds
Started Aug 27 07:06:34 AM UTC 24
Finished Aug 27 07:07:04 AM UTC 24
Peak memory 282848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176333
7414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.1763337414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.2460190829
Short name T441
Test name
Test status
Simulation time 536627673 ps
CPU time 27.07 seconds
Started Aug 27 07:06:22 AM UTC 24
Finished Aug 27 07:06:51 AM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460190829 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.2460190829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.2464671826
Short name T1060
Test name
Test status
Simulation time 54048189113 ps
CPU time 660.05 seconds
Started Aug 27 07:06:21 AM UTC 24
Finished Aug 27 07:17:28 AM UTC 24
Peak memory 7233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464671826 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.2464671826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.2170543459
Short name T458
Test name
Test status
Simulation time 4597915572 ps
CPU time 42.96 seconds
Started Aug 27 07:06:22 AM UTC 24
Finished Aug 27 07:07:07 AM UTC 24
Peak memory 602240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170543459 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.2170543459
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.2851879743
Short name T146
Test name
Test status
Simulation time 3203418764 ps
CPU time 12.14 seconds
Started Aug 27 07:06:28 AM UTC 24
Finished Aug 27 07:06:41 AM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851879
743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.2851879743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.2053727370
Short name T447
Test name
Test status
Simulation time 154794909 ps
CPU time 5.57 seconds
Started Aug 27 07:06:47 AM UTC 24
Finished Aug 27 07:06:54 AM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053727
370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2053727370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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