| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1631281157 |
|
|
Aug 28 10:46:27 PM UTC 24 |
Aug 28 10:46:33 PM UTC 24 |
926042503 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1030910936 |
|
|
Aug 28 10:44:08 PM UTC 24 |
Aug 28 10:46:33 PM UTC 24 |
19592368774 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_perf.919023627 |
|
|
Aug 28 10:44:38 PM UTC 24 |
Aug 28 10:46:33 PM UTC 24 |
2580445392 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_override.2057552743 |
|
|
Aug 28 10:46:32 PM UTC 24 |
Aug 28 10:46:34 PM UTC 24 |
55273946 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2410490575 |
|
|
Aug 28 10:45:11 PM UTC 24 |
Aug 28 10:46:36 PM UTC 24 |
5588230820 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2079766747 |
|
|
Aug 28 10:46:21 PM UTC 24 |
Aug 28 10:46:36 PM UTC 24 |
1386912731 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2252139592 |
|
|
Aug 28 10:46:33 PM UTC 24 |
Aug 28 10:46:37 PM UTC 24 |
163558958 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2116903250 |
|
|
Aug 28 10:46:34 PM UTC 24 |
Aug 28 10:46:37 PM UTC 24 |
234013226 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.238791325 |
|
|
Aug 28 10:44:36 PM UTC 24 |
Aug 28 10:46:39 PM UTC 24 |
18730113910 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3591511254 |
|
|
Aug 28 10:46:33 PM UTC 24 |
Aug 28 10:46:40 PM UTC 24 |
275464938 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.2376349954 |
|
|
Aug 28 10:40:12 PM UTC 24 |
Aug 28 10:46:41 PM UTC 24 |
28437750414 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.2361336202 |
|
|
Aug 28 10:46:36 PM UTC 24 |
Aug 28 10:46:43 PM UTC 24 |
297222982 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2875075608 |
|
|
Aug 28 10:46:34 PM UTC 24 |
Aug 28 10:46:44 PM UTC 24 |
231449448 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2980332018 |
|
|
Aug 28 10:46:42 PM UTC 24 |
Aug 28 10:46:50 PM UTC 24 |
1061418912 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3836182633 |
|
|
Aug 28 10:46:37 PM UTC 24 |
Aug 28 10:46:50 PM UTC 24 |
2512515785 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1522039494 |
|
|
Aug 28 10:46:41 PM UTC 24 |
Aug 28 10:46:51 PM UTC 24 |
3053574263 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.67892674 |
|
|
Aug 28 10:47:51 PM UTC 24 |
Aug 28 10:47:57 PM UTC 24 |
310148822 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.716235897 |
|
|
Aug 28 10:43:40 PM UTC 24 |
Aug 28 10:46:51 PM UTC 24 |
6050283381 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2301255395 |
|
|
Aug 28 10:46:35 PM UTC 24 |
Aug 28 10:46:52 PM UTC 24 |
668130351 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2478503335 |
|
|
Aug 28 10:45:57 PM UTC 24 |
Aug 28 10:46:53 PM UTC 24 |
2852353755 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2933270188 |
|
|
Aug 28 10:45:12 PM UTC 24 |
Aug 28 10:46:53 PM UTC 24 |
7823841449 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.427606456 |
|
|
Aug 28 10:46:51 PM UTC 24 |
Aug 28 10:46:54 PM UTC 24 |
454373602 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1970052957 |
|
|
Aug 28 10:46:52 PM UTC 24 |
Aug 28 10:46:55 PM UTC 24 |
310561886 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.1157847004 |
|
|
Aug 28 10:43:41 PM UTC 24 |
Aug 28 10:46:56 PM UTC 24 |
61726398481 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1973892438 |
|
|
Aug 28 10:47:46 PM UTC 24 |
Aug 28 10:47:50 PM UTC 24 |
254926775 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2577989344 |
|
|
Aug 28 10:46:53 PM UTC 24 |
Aug 28 10:46:57 PM UTC 24 |
1172466581 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.898417072 |
|
|
Aug 28 10:46:56 PM UTC 24 |
Aug 28 10:46:58 PM UTC 24 |
206429255 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.3131138272 |
|
|
Aug 28 10:46:45 PM UTC 24 |
Aug 28 10:46:58 PM UTC 24 |
5259252586 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3231258987 |
|
|
Aug 28 10:46:07 PM UTC 24 |
Aug 28 10:46:59 PM UTC 24 |
2279179677 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.4007603610 |
|
|
Aug 28 10:45:55 PM UTC 24 |
Aug 28 10:46:59 PM UTC 24 |
5787891112 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3075971319 |
|
|
Aug 28 10:46:55 PM UTC 24 |
Aug 28 10:47:00 PM UTC 24 |
5129086927 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2088905176 |
|
|
Aug 28 10:46:52 PM UTC 24 |
Aug 28 10:47:00 PM UTC 24 |
2036951173 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_alert_test.459811936 |
|
|
Aug 28 10:47:00 PM UTC 24 |
Aug 28 10:47:02 PM UTC 24 |
119087143 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.2278346780 |
|
|
Aug 28 10:46:59 PM UTC 24 |
Aug 28 10:47:02 PM UTC 24 |
2521814636 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2654630845 |
|
|
Aug 28 10:46:58 PM UTC 24 |
Aug 28 10:47:03 PM UTC 24 |
6376053773 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3848494445 |
|
|
Aug 28 10:46:57 PM UTC 24 |
Aug 28 10:47:03 PM UTC 24 |
240470964 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_override.1222980747 |
|
|
Aug 28 10:47:01 PM UTC 24 |
Aug 28 10:47:03 PM UTC 24 |
88801355 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.3886264469 |
|
|
Aug 28 10:46:58 PM UTC 24 |
Aug 28 10:47:04 PM UTC 24 |
3629077414 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3205266136 |
|
|
Aug 28 10:46:53 PM UTC 24 |
Aug 28 10:47:04 PM UTC 24 |
5180031380 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.4237972420 |
|
|
Aug 28 10:44:37 PM UTC 24 |
Aug 28 10:47:04 PM UTC 24 |
7789583375 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.1052624638 |
|
|
Aug 28 10:46:55 PM UTC 24 |
Aug 28 10:47:04 PM UTC 24 |
804437359 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.257536954 |
|
|
Aug 28 10:46:59 PM UTC 24 |
Aug 28 10:47:04 PM UTC 24 |
573308909 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1166460374 |
|
|
Aug 28 10:46:40 PM UTC 24 |
Aug 28 10:47:05 PM UTC 24 |
4863181397 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.532157219 |
|
|
Aug 28 10:47:03 PM UTC 24 |
Aug 28 10:47:06 PM UTC 24 |
144490338 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.4254954449 |
|
|
Aug 28 10:47:05 PM UTC 24 |
Aug 28 10:47:07 PM UTC 24 |
74442154 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2418913729 |
|
|
Aug 28 10:47:06 PM UTC 24 |
Aug 28 10:47:09 PM UTC 24 |
85814100 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3732061084 |
|
|
Aug 28 10:47:03 PM UTC 24 |
Aug 28 10:47:12 PM UTC 24 |
242300386 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.577838758 |
|
|
Aug 28 10:47:05 PM UTC 24 |
Aug 28 10:47:13 PM UTC 24 |
401339716 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.2092968499 |
|
|
Aug 28 10:41:03 PM UTC 24 |
Aug 28 10:47:17 PM UTC 24 |
20730498805 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1591098888 |
|
|
Aug 28 10:44:55 PM UTC 24 |
Aug 28 10:47:19 PM UTC 24 |
88971551882 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.259298976 |
|
|
Aug 28 10:45:12 PM UTC 24 |
Aug 28 10:48:04 PM UTC 24 |
4805285707 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.1601289317 |
|
|
Aug 28 10:47:20 PM UTC 24 |
Aug 28 10:47:22 PM UTC 24 |
328339623 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2925046221 |
|
|
Aug 28 10:47:12 PM UTC 24 |
Aug 28 10:47:25 PM UTC 24 |
1408938180 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2563183646 |
|
|
Aug 28 10:47:23 PM UTC 24 |
Aug 28 10:47:26 PM UTC 24 |
1007192576 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.4169095114 |
|
|
Aug 28 10:47:15 PM UTC 24 |
Aug 28 10:47:27 PM UTC 24 |
1217633233 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.974356298 |
|
|
Aug 28 10:46:33 PM UTC 24 |
Aug 28 10:47:28 PM UTC 24 |
5158303295 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.3536348419 |
|
|
Aug 28 10:47:28 PM UTC 24 |
Aug 28 10:47:32 PM UTC 24 |
199379593 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_perf.624126655 |
|
|
Aug 28 10:46:34 PM UTC 24 |
Aug 28 10:47:32 PM UTC 24 |
25505107758 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4058320760 |
|
|
Aug 28 10:47:24 PM UTC 24 |
Aug 28 10:47:34 PM UTC 24 |
2785955177 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1984410330 |
|
|
Aug 28 10:47:26 PM UTC 24 |
Aug 28 10:47:35 PM UTC 24 |
1890533617 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1287966563 |
|
|
Aug 28 10:47:34 PM UTC 24 |
Aug 28 10:47:37 PM UTC 24 |
513014145 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.2515274931 |
|
|
Aug 28 10:47:33 PM UTC 24 |
Aug 28 10:47:38 PM UTC 24 |
357546241 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3365334564 |
|
|
Aug 28 10:47:14 PM UTC 24 |
Aug 28 10:47:39 PM UTC 24 |
11543687251 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.74990000 |
|
|
Aug 28 10:47:43 PM UTC 24 |
Aug 28 10:47:58 PM UTC 24 |
634264619 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2263949218 |
|
|
Aug 28 10:47:35 PM UTC 24 |
Aug 28 10:47:40 PM UTC 24 |
94261071 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.3860592211 |
|
|
Aug 28 10:47:06 PM UTC 24 |
Aug 28 10:47:40 PM UTC 24 |
3682238950 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3471027563 |
|
|
Aug 28 10:47:33 PM UTC 24 |
Aug 28 10:47:40 PM UTC 24 |
689162454 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.661514067 |
|
|
Aug 28 10:47:36 PM UTC 24 |
Aug 28 10:47:40 PM UTC 24 |
1706228774 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.4160192525 |
|
|
Aug 28 10:45:56 PM UTC 24 |
Aug 28 10:47:40 PM UTC 24 |
11640896450 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3820017164 |
|
|
Aug 28 10:47:05 PM UTC 24 |
Aug 28 10:47:42 PM UTC 24 |
783547589 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1864820947 |
|
|
Aug 28 10:47:41 PM UTC 24 |
Aug 28 10:47:43 PM UTC 24 |
19553164 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_override.549308557 |
|
|
Aug 28 10:47:41 PM UTC 24 |
Aug 28 10:47:43 PM UTC 24 |
18549821 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3567748201 |
|
|
Aug 28 10:47:40 PM UTC 24 |
Aug 28 10:47:43 PM UTC 24 |
688676580 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.133649972 |
|
|
Aug 28 10:47:08 PM UTC 24 |
Aug 28 10:47:43 PM UTC 24 |
1406342783 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1493365783 |
|
|
Aug 28 10:47:39 PM UTC 24 |
Aug 28 10:47:44 PM UTC 24 |
4276824801 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.40266261 |
|
|
Aug 28 10:47:39 PM UTC 24 |
Aug 28 10:47:44 PM UTC 24 |
2177308866 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2466625652 |
|
|
Aug 28 10:47:42 PM UTC 24 |
Aug 28 10:47:44 PM UTC 24 |
400318251 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.755389879 |
|
|
Aug 28 10:47:44 PM UTC 24 |
Aug 28 10:47:47 PM UTC 24 |
57139688 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.2869482827 |
|
|
Aug 28 10:46:17 PM UTC 24 |
Aug 28 10:47:58 PM UTC 24 |
53672164857 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2206913149 |
|
|
Aug 28 10:47:44 PM UTC 24 |
Aug 28 10:48:04 PM UTC 24 |
8823505831 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1146694798 |
|
|
Aug 28 10:47:00 PM UTC 24 |
Aug 28 10:48:07 PM UTC 24 |
1136417124 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.1095658326 |
|
|
Aug 28 10:40:53 PM UTC 24 |
Aug 28 10:48:07 PM UTC 24 |
38191505045 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.1089908701 |
|
|
Aug 28 10:36:47 PM UTC 24 |
Aug 28 10:51:23 PM UTC 24 |
182430747391 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.1399466624 |
|
|
Aug 28 10:46:52 PM UTC 24 |
Aug 28 10:48:09 PM UTC 24 |
30773440254 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.2219789092 |
|
|
Aug 28 10:48:05 PM UTC 24 |
Aug 28 10:48:09 PM UTC 24 |
422905204 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1497423054 |
|
|
Aug 28 10:47:50 PM UTC 24 |
Aug 28 10:48:10 PM UTC 24 |
16167515967 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1727766855 |
|
|
Aug 28 10:48:07 PM UTC 24 |
Aug 28 10:48:10 PM UTC 24 |
184031589 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.873425843 |
|
|
Aug 28 10:47:59 PM UTC 24 |
Aug 28 10:48:11 PM UTC 24 |
6892690462 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.3045682743 |
|
|
Aug 28 10:48:21 PM UTC 24 |
Aug 28 10:50:58 PM UTC 24 |
12765202536 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.294333814 |
|
|
Aug 28 10:47:58 PM UTC 24 |
Aug 28 10:48:12 PM UTC 24 |
7081741547 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3886080939 |
|
|
Aug 28 10:47:01 PM UTC 24 |
Aug 28 10:48:14 PM UTC 24 |
3718558966 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1626116708 |
|
|
Aug 28 10:46:31 PM UTC 24 |
Aug 28 10:48:14 PM UTC 24 |
12414104145 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2360276068 |
|
|
Aug 28 10:48:12 PM UTC 24 |
Aug 28 10:48:14 PM UTC 24 |
238149685 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.472126762 |
|
|
Aug 28 10:48:10 PM UTC 24 |
Aug 28 10:48:15 PM UTC 24 |
748441688 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_perf.1572921335 |
|
|
Aug 28 10:48:08 PM UTC 24 |
Aug 28 10:48:16 PM UTC 24 |
1040801636 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3332044314 |
|
|
Aug 28 10:48:10 PM UTC 24 |
Aug 28 10:48:16 PM UTC 24 |
2974711439 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3984179360 |
|
|
Aug 28 10:48:11 PM UTC 24 |
Aug 28 10:48:17 PM UTC 24 |
583968591 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1119008262 |
|
|
Aug 28 10:48:16 PM UTC 24 |
Aug 28 10:48:19 PM UTC 24 |
76461104 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_override.3270726572 |
|
|
Aug 28 10:48:17 PM UTC 24 |
Aug 28 10:48:19 PM UTC 24 |
18200422 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.924485954 |
|
|
Aug 28 10:48:15 PM UTC 24 |
Aug 28 10:48:19 PM UTC 24 |
295654251 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.763354315 |
|
|
Aug 28 10:48:13 PM UTC 24 |
Aug 28 10:48:19 PM UTC 24 |
8735140370 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2423714998 |
|
|
Aug 28 10:48:11 PM UTC 24 |
Aug 28 10:48:20 PM UTC 24 |
2410432036 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.4090862327 |
|
|
Aug 28 10:48:15 PM UTC 24 |
Aug 28 10:48:20 PM UTC 24 |
541226612 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.2476733711 |
|
|
Aug 28 10:48:13 PM UTC 24 |
Aug 28 10:48:21 PM UTC 24 |
177465147 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1798119230 |
|
|
Aug 28 10:46:34 PM UTC 24 |
Aug 28 10:48:21 PM UTC 24 |
3018520622 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.2440916401 |
|
|
Aug 28 10:48:15 PM UTC 24 |
Aug 28 10:48:21 PM UTC 24 |
3666942287 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2246441961 |
|
|
Aug 28 10:48:20 PM UTC 24 |
Aug 28 10:48:22 PM UTC 24 |
90046431 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2425908794 |
|
|
Aug 28 10:46:44 PM UTC 24 |
Aug 28 10:50:36 PM UTC 24 |
14842961785 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3328914723 |
|
|
Aug 28 10:48:21 PM UTC 24 |
Aug 28 10:48:24 PM UTC 24 |
84841329 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2303450266 |
|
|
Aug 28 10:47:48 PM UTC 24 |
Aug 28 10:48:25 PM UTC 24 |
977731093 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.788403865 |
|
|
Aug 28 10:48:21 PM UTC 24 |
Aug 28 10:48:27 PM UTC 24 |
601318890 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_perf.2006205085 |
|
|
Aug 28 10:47:44 PM UTC 24 |
Aug 28 10:48:29 PM UTC 24 |
3223763248 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1358692268 |
|
|
Aug 28 10:48:20 PM UTC 24 |
Aug 28 10:48:29 PM UTC 24 |
279240007 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.830308533 |
|
|
Aug 28 10:26:15 PM UTC 24 |
Aug 28 10:48:33 PM UTC 24 |
60429692292 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2062094212 |
|
|
Aug 28 10:46:39 PM UTC 24 |
Aug 28 10:48:34 PM UTC 24 |
38001230257 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.660575327 |
|
|
Aug 28 10:48:30 PM UTC 24 |
Aug 28 10:48:34 PM UTC 24 |
204128543 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.328377175 |
|
|
Aug 28 10:48:22 PM UTC 24 |
Aug 28 10:48:35 PM UTC 24 |
257989168 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.2651184775 |
|
|
Aug 28 10:48:36 PM UTC 24 |
Aug 28 10:48:40 PM UTC 24 |
224104239 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.209435932 |
|
|
Aug 28 10:43:36 PM UTC 24 |
Aug 28 10:48:41 PM UTC 24 |
39655066546 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1081858142 |
|
|
Aug 28 10:48:30 PM UTC 24 |
Aug 28 10:48:41 PM UTC 24 |
995802780 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.3321456133 |
|
|
Aug 28 10:48:40 PM UTC 24 |
Aug 28 10:48:43 PM UTC 24 |
214796506 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3758810435 |
|
|
Aug 28 10:48:35 PM UTC 24 |
Aug 28 10:48:47 PM UTC 24 |
1331949339 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3710824527 |
|
|
Aug 28 10:48:22 PM UTC 24 |
Aug 28 10:48:48 PM UTC 24 |
1769219988 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2552470546 |
|
|
Aug 28 10:47:41 PM UTC 24 |
Aug 28 10:48:48 PM UTC 24 |
6386624816 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.3423156333 |
|
|
Aug 28 10:48:41 PM UTC 24 |
Aug 28 10:48:49 PM UTC 24 |
5240517568 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.1653279396 |
|
|
Aug 28 10:45:57 PM UTC 24 |
Aug 28 10:48:49 PM UTC 24 |
6064144447 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1910005378 |
|
|
Aug 28 10:46:03 PM UTC 24 |
Aug 28 10:48:49 PM UTC 24 |
27161499638 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2689586311 |
|
|
Aug 28 10:48:40 PM UTC 24 |
Aug 28 10:48:50 PM UTC 24 |
722239998 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.4169682520 |
|
|
Aug 28 10:48:50 PM UTC 24 |
Aug 28 10:48:52 PM UTC 24 |
357980553 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3395317210 |
|
|
Aug 28 10:47:41 PM UTC 24 |
Aug 28 10:48:53 PM UTC 24 |
5274823437 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.3106289711 |
|
|
Aug 28 10:48:51 PM UTC 24 |
Aug 28 10:48:55 PM UTC 24 |
5031485284 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1999216136 |
|
|
Aug 28 10:48:50 PM UTC 24 |
Aug 28 10:48:55 PM UTC 24 |
1119775901 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2966412662 |
|
|
Aug 28 10:48:54 PM UTC 24 |
Aug 28 10:48:56 PM UTC 24 |
47629984 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.3219735842 |
|
|
Aug 28 10:48:16 PM UTC 24 |
Aug 28 10:48:56 PM UTC 24 |
3111944100 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.3521446789 |
|
|
Aug 28 10:48:51 PM UTC 24 |
Aug 28 10:48:56 PM UTC 24 |
118388019 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.4220605160 |
|
|
Aug 28 10:48:51 PM UTC 24 |
Aug 28 10:48:56 PM UTC 24 |
1002184903 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3588596939 |
|
|
Aug 28 10:48:51 PM UTC 24 |
Aug 28 10:48:57 PM UTC 24 |
541687947 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_perf.4290956888 |
|
|
Aug 28 10:48:21 PM UTC 24 |
Aug 28 10:50:39 PM UTC 24 |
30144883619 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3329401652 |
|
|
Aug 28 10:48:48 PM UTC 24 |
Aug 28 10:48:57 PM UTC 24 |
384429646 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.917577971 |
|
|
Aug 28 10:45:27 PM UTC 24 |
Aug 28 10:48:58 PM UTC 24 |
9239322255 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3459547612 |
|
|
Aug 28 10:46:32 PM UTC 24 |
Aug 28 10:50:36 PM UTC 24 |
4154934599 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.2513087546 |
|
|
Aug 28 10:43:46 PM UTC 24 |
Aug 28 10:49:00 PM UTC 24 |
17898431433 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1853950844 |
|
|
Aug 28 10:48:24 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
15077793455 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1839692969 |
|
|
Aug 28 10:47:05 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
2040209033 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1098949773 |
|
|
Aug 28 10:47:26 PM UTC 24 |
Aug 28 10:49:15 PM UTC 24 |
23304881293 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1322014597 |
|
|
Aug 28 10:48:29 PM UTC 24 |
Aug 28 10:49:23 PM UTC 24 |
4060762392 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3005572210 |
|
|
Aug 28 10:48:09 PM UTC 24 |
Aug 28 10:49:24 PM UTC 24 |
109270884072 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.1477702831 |
|
|
Aug 28 10:47:41 PM UTC 24 |
Aug 28 10:49:28 PM UTC 24 |
3374263515 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2280001675 |
|
|
Aug 28 10:47:59 PM UTC 24 |
Aug 28 10:49:37 PM UTC 24 |
15978950512 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.725052282 |
|
|
Aug 28 10:47:43 PM UTC 24 |
Aug 28 10:49:39 PM UTC 24 |
2035901203 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2836965840 |
|
|
Aug 28 10:48:20 PM UTC 24 |
Aug 28 10:49:41 PM UTC 24 |
2411913618 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.4234959136 |
|
|
Aug 28 10:47:03 PM UTC 24 |
Aug 28 10:49:48 PM UTC 24 |
3601257287 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.2646768644 |
|
|
Aug 28 10:35:42 PM UTC 24 |
Aug 28 10:49:54 PM UTC 24 |
50167166820 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_perf.1462567121 |
|
|
Aug 28 10:38:11 PM UTC 24 |
Aug 28 10:49:59 PM UTC 24 |
49950135796 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1050614173 |
|
|
Aug 28 10:47:05 PM UTC 24 |
Aug 28 10:50:01 PM UTC 24 |
7242922611 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3669698984 |
|
|
Aug 28 10:48:18 PM UTC 24 |
Aug 28 10:50:31 PM UTC 24 |
17631733267 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.2060749092 |
|
|
Aug 28 10:48:25 PM UTC 24 |
Aug 28 10:50:46 PM UTC 24 |
44229772016 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1027882129 |
|
|
Aug 28 10:48:35 PM UTC 24 |
Aug 28 10:52:06 PM UTC 24 |
27355088879 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.1547176358 |
|
|
Aug 28 10:41:34 PM UTC 24 |
Aug 28 10:52:16 PM UTC 24 |
46535347866 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.1997267006 |
|
|
Aug 28 10:43:04 PM UTC 24 |
Aug 28 10:52:31 PM UTC 24 |
44051566692 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_stress_all.1914054285 |
|
|
Aug 28 10:44:13 PM UTC 24 |
Aug 28 10:52:35 PM UTC 24 |
30149438439 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.637599326 |
|
|
Aug 28 10:45:30 PM UTC 24 |
Aug 28 10:52:42 PM UTC 24 |
65968961278 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1116736756 |
|
|
Aug 28 10:45:46 PM UTC 24 |
Aug 28 10:52:51 PM UTC 24 |
92530498696 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.2561960343 |
|
|
Aug 28 10:45:37 PM UTC 24 |
Aug 28 10:53:00 PM UTC 24 |
24990868239 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_perf.1335093783 |
|
|
Aug 28 10:44:10 PM UTC 24 |
Aug 28 10:53:09 PM UTC 24 |
51370810356 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.617671113 |
|
|
Aug 28 10:34:39 PM UTC 24 |
Aug 28 10:53:40 PM UTC 24 |
58928301672 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.2605614257 |
|
|
Aug 28 10:35:41 PM UTC 24 |
Aug 28 10:54:13 PM UTC 24 |
40169409457 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_perf.2716491057 |
|
|
Aug 28 10:36:11 PM UTC 24 |
Aug 28 10:54:40 PM UTC 24 |
51858330745 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.3807561547 |
|
|
Aug 28 10:41:56 PM UTC 24 |
Aug 28 10:54:57 PM UTC 24 |
50600417521 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.908682501 |
|
|
Aug 28 10:46:02 PM UTC 24 |
Aug 28 10:56:28 PM UTC 24 |
41212081073 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1353931107 |
|
|
Aug 28 10:47:07 PM UTC 24 |
Aug 28 10:57:59 PM UTC 24 |
47031133861 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1195111645 |
|
|
Aug 28 10:48:41 PM UTC 24 |
Aug 28 11:00:54 PM UTC 24 |
36844906961 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2376200963 |
|
|
Aug 28 10:46:08 PM UTC 24 |
Aug 28 11:01:47 PM UTC 24 |
41502276718 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.3381642614 |
|
|
Aug 28 10:40:53 PM UTC 24 |
Aug 28 11:06:15 PM UTC 24 |
64932366543 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_perf.1654345446 |
|
|
Aug 28 10:29:30 PM UTC 24 |
Aug 28 11:08:52 PM UTC 24 |
52151599245 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.231097523 |
|
|
Aug 28 10:48:56 PM UTC 24 |
Aug 28 10:48:59 PM UTC 24 |
29119453 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2738687277 |
|
|
Aug 28 10:48:57 PM UTC 24 |
Aug 28 10:48:59 PM UTC 24 |
20246864 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.2018869981 |
|
|
Aug 28 10:48:57 PM UTC 24 |
Aug 28 10:48:59 PM UTC 24 |
46467023 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.133687939 |
|
|
Aug 28 10:48:57 PM UTC 24 |
Aug 28 10:48:59 PM UTC 24 |
28768886 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1494740656 |
|
|
Aug 28 10:48:58 PM UTC 24 |
Aug 28 10:49:00 PM UTC 24 |
25514100 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.850786253 |
|
|
Aug 28 10:49:20 PM UTC 24 |
Aug 28 10:49:22 PM UTC 24 |
89381568 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1336613150 |
|
|
Aug 28 10:48:56 PM UTC 24 |
Aug 28 10:49:00 PM UTC 24 |
82402415 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1988177400 |
|
|
Aug 28 10:48:58 PM UTC 24 |
Aug 28 10:49:00 PM UTC 24 |
110919677 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1694398195 |
|
|
Aug 28 10:48:57 PM UTC 24 |
Aug 28 10:49:00 PM UTC 24 |
39630504 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2875957212 |
|
|
Aug 28 10:49:00 PM UTC 24 |
Aug 28 10:49:02 PM UTC 24 |
45394624 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2151407668 |
|
|
Aug 28 10:49:00 PM UTC 24 |
Aug 28 10:49:02 PM UTC 24 |
50181191 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2497637376 |
|
|
Aug 28 10:49:00 PM UTC 24 |
Aug 28 10:49:02 PM UTC 24 |
50837101 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.851187872 |
|
|
Aug 28 10:48:59 PM UTC 24 |
Aug 28 10:49:03 PM UTC 24 |
553104775 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1837439866 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:03 PM UTC 24 |
139614519 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.2561852433 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
61355736 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3925095517 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
90928536 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.802188557 |
|
|
Aug 28 10:48:57 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
372583851 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2659491728 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
55160747 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1692128383 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
38387994 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.3366124678 |
|
|
Aug 28 10:49:00 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
895211744 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.4179256138 |
|
|
Aug 28 10:49:03 PM UTC 24 |
Aug 28 10:49:04 PM UTC 24 |
131462105 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.466541303 |
|
|
Aug 28 10:49:02 PM UTC 24 |
Aug 28 10:49:05 PM UTC 24 |
20395290 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.1118170190 |
|
|
Aug 28 10:49:01 PM UTC 24 |
Aug 28 10:49:06 PM UTC 24 |
466569445 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3214500267 |
|
|
Aug 28 10:49:04 PM UTC 24 |
Aug 28 10:49:06 PM UTC 24 |
90431648 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1681661933 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
77599450 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.2359594867 |
|
|
Aug 28 10:49:00 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
1045173309 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3407820208 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
46594741 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.810975387 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
18667971 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1312543530 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
134040584 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4008624952 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:07 PM UTC 24 |
668582379 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3543811824 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:08 PM UTC 24 |
47744508 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4100187375 |
|
|
Aug 28 10:49:06 PM UTC 24 |
Aug 28 10:49:09 PM UTC 24 |
64124859 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.348895410 |
|
|
Aug 28 10:49:03 PM UTC 24 |
Aug 28 10:49:09 PM UTC 24 |
1173021800 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1155082539 |
|
|
Aug 28 10:49:05 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
169983744 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.72545030 |
|
|
Aug 28 10:49:08 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
46785995 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.540702245 |
|
|
Aug 28 10:49:08 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
92583627 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2141074171 |
|
|
Aug 28 10:49:08 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
384205606 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1389813916 |
|
|
Aug 28 10:49:07 PM UTC 24 |
Aug 28 10:49:10 PM UTC 24 |
178832900 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.549978948 |
|
|
Aug 28 10:49:06 PM UTC 24 |
Aug 28 10:49:11 PM UTC 24 |
128518795 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.658938700 |
|
|
Aug 28 10:49:08 PM UTC 24 |
Aug 28 10:49:11 PM UTC 24 |
185186114 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.540413993 |
|
|
Aug 28 10:49:08 PM UTC 24 |
Aug 28 10:49:11 PM UTC 24 |
117645847 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2824483777 |
|
|
Aug 28 10:49:09 PM UTC 24 |
Aug 28 10:49:11 PM UTC 24 |
36130158 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1631678909 |
|
|
Aug 28 10:49:10 PM UTC 24 |
Aug 28 10:49:12 PM UTC 24 |
27644486 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.1309653355 |
|
|
Aug 28 10:49:10 PM UTC 24 |
Aug 28 10:49:12 PM UTC 24 |
83406785 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.2802817125 |
|
|
Aug 28 10:49:10 PM UTC 24 |
Aug 28 10:49:13 PM UTC 24 |
55299746 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.69351981 |
|
|
Aug 28 10:49:09 PM UTC 24 |
Aug 28 10:49:13 PM UTC 24 |
183006572 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.4013213704 |
|
|
Aug 28 10:49:10 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
79090673 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.3291953445 |
|
|
Aug 28 10:49:06 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
138805066 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.439674817 |
|
|
Aug 28 10:49:11 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
29015017 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1072269849 |
|
|
Aug 28 10:49:11 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
32680434 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3070676905 |
|
|
Aug 28 10:49:10 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
75357928 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2548039103 |
|
|
Aug 28 10:49:12 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
160533089 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.739339610 |
|
|
Aug 28 10:49:12 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
28223334 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.4260882679 |
|
|
Aug 28 10:49:09 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
706182894 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3435533278 |
|
|
Aug 28 10:49:12 PM UTC 24 |
Aug 28 10:49:14 PM UTC 24 |
71663596 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4017404749 |
|
|
Aug 28 10:49:13 PM UTC 24 |
Aug 28 10:49:15 PM UTC 24 |
86713600 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1929428467 |
|
|
Aug 28 10:49:12 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
146786115 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.3779672197 |
|
|
Aug 28 10:49:12 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
1112693647 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2258985596 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
50407477 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4052949555 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
101747393 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1784060068 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
20422510 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3825338649 |
|
|
Aug 28 10:49:13 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
30470804 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.939925834 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:16 PM UTC 24 |
34293169 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1998886234 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:17 PM UTC 24 |
259025192 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.4092378806 |
|
|
Aug 28 10:49:13 PM UTC 24 |
Aug 28 10:49:17 PM UTC 24 |
97501261 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.3610544110 |
|
|
Aug 28 10:49:16 PM UTC 24 |
Aug 28 10:49:18 PM UTC 24 |
26793820 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.2604714449 |
|
|
Aug 28 10:49:22 PM UTC 24 |
Aug 28 10:49:24 PM UTC 24 |
27889837 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.1629180858 |
|
|
Aug 28 10:49:16 PM UTC 24 |
Aug 28 10:49:18 PM UTC 24 |
56892506 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.3378267098 |
|
|
Aug 28 10:49:17 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
20237105 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.279406611 |
|
|
Aug 28 10:49:16 PM UTC 24 |
Aug 28 10:49:18 PM UTC 24 |
58018077 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.376505390 |
|
|
Aug 28 10:49:16 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
33860601 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.4257191302 |
|
|
Aug 28 10:49:14 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
223131905 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.3258641962 |
|
|
Aug 28 10:49:16 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
121514134 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3693275610 |
|
|
Aug 28 10:49:17 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
46250314 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.4249326472 |
|
|
Aug 28 10:49:17 PM UTC 24 |
Aug 28 10:49:19 PM UTC 24 |
30810889 ps |