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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.42 97.30 89.84 97.22 72.62 94.40 98.44 90.11


Total test records in report: 1839
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T1763 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.646127019 Aug 28 10:49:17 PM UTC 24 Aug 28 10:49:20 PM UTC 24 56384449 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2925022252 Aug 28 10:49:16 PM UTC 24 Aug 28 10:49:20 PM UTC 24 302442066 ps
T1764 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1273416848 Aug 28 10:49:17 PM UTC 24 Aug 28 10:49:20 PM UTC 24 29322136 ps
T1765 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3335960722 Aug 28 10:49:17 PM UTC 24 Aug 28 10:49:20 PM UTC 24 53158557 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3130141275 Aug 28 10:49:19 PM UTC 24 Aug 28 10:49:21 PM UTC 24 76824699 ps
T1766 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3913307744 Aug 28 10:49:19 PM UTC 24 Aug 28 10:49:21 PM UTC 24 39052273 ps
T1767 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1101587976 Aug 28 10:49:19 PM UTC 24 Aug 28 10:49:21 PM UTC 24 50912474 ps
T1768 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.110187498 Aug 28 10:49:18 PM UTC 24 Aug 28 10:49:21 PM UTC 24 164910937 ps
T1769 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.607298813 Aug 28 10:49:19 PM UTC 24 Aug 28 10:49:21 PM UTC 24 201194327 ps
T1770 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2426299528 Aug 28 10:49:19 PM UTC 24 Aug 28 10:49:21 PM UTC 24 48591803 ps
T1771 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2640322817 Aug 28 10:49:17 PM UTC 24 Aug 28 10:49:21 PM UTC 24 253370448 ps
T1772 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.709246053 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:22 PM UTC 24 109967949 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3163731984 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:22 PM UTC 24 20650165 ps
T1773 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.782463462 Aug 28 10:49:22 PM UTC 24 Aug 28 10:49:24 PM UTC 24 40385821 ps
T1774 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3519635101 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:23 PM UTC 24 20393952 ps
T1775 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1659822568 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:23 PM UTC 24 27631142 ps
T1776 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3716995475 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:23 PM UTC 24 54784311 ps
T1777 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.1644721158 Aug 28 10:49:21 PM UTC 24 Aug 28 10:49:24 PM UTC 24 50852548 ps
T1778 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1578881769 Aug 28 10:49:22 PM UTC 24 Aug 28 10:49:24 PM UTC 24 177880027 ps
T1779 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2025116548 Aug 28 10:49:22 PM UTC 24 Aug 28 10:49:24 PM UTC 24 95478410 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.2798208143 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:24 PM UTC 24 151952165 ps
T1780 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3522797983 Aug 28 10:49:22 PM UTC 24 Aug 28 10:49:25 PM UTC 24 56367773 ps
T1781 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1524734370 Aug 28 10:49:20 PM UTC 24 Aug 28 10:49:25 PM UTC 24 101929102 ps
T1782 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.4268066058 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:25 PM UTC 24 83120155 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.872527302 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:25 PM UTC 24 32220420 ps
T1783 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2221236772 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:25 PM UTC 24 142631439 ps
T1784 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.2364803410 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:26 PM UTC 24 49585812 ps
T1785 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1242051978 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:26 PM UTC 24 45684639 ps
T1786 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.2822044592 Aug 28 10:49:23 PM UTC 24 Aug 28 10:49:26 PM UTC 24 31219871 ps
T1787 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2297626072 Aug 28 10:49:24 PM UTC 24 Aug 28 10:49:26 PM UTC 24 15673715 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.3365910079 Aug 28 10:49:24 PM UTC 24 Aug 28 10:49:27 PM UTC 24 29634388 ps
T1788 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.4287879729 Aug 28 10:49:25 PM UTC 24 Aug 28 10:49:27 PM UTC 24 18567380 ps
T1789 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2145911762 Aug 28 10:49:25 PM UTC 24 Aug 28 10:49:27 PM UTC 24 39681863 ps
T1790 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1362506718 Aug 28 10:49:25 PM UTC 24 Aug 28 10:49:27 PM UTC 24 35454614 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2226021846 Aug 28 10:49:24 PM UTC 24 Aug 28 10:49:27 PM UTC 24 51866353 ps
T1791 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.785009033 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:28 PM UTC 24 55406530 ps
T1792 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.3610384650 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:28 PM UTC 24 49637807 ps
T1793 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.999149740 Aug 28 10:49:24 PM UTC 24 Aug 28 10:49:28 PM UTC 24 265305182 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.2323586751 Aug 28 10:49:25 PM UTC 24 Aug 28 10:49:28 PM UTC 24 90585315 ps
T1794 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.916110215 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:28 PM UTC 24 65378069 ps
T1795 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.406042440 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:28 PM UTC 24 111703063 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.680832223 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:29 PM UTC 24 68760404 ps
T1796 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.2688299034 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:29 PM UTC 24 176509572 ps
T1797 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.425708112 Aug 28 10:49:27 PM UTC 24 Aug 28 10:49:30 PM UTC 24 31405926 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.697580479 Aug 28 10:49:27 PM UTC 24 Aug 28 10:49:30 PM UTC 24 31690120 ps
T1798 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2363065053 Aug 28 10:49:27 PM UTC 24 Aug 28 10:49:30 PM UTC 24 32661311 ps
T1799 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.382762277 Aug 28 10:49:25 PM UTC 24 Aug 28 10:49:30 PM UTC 24 209679795 ps
T1800 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.665628654 Aug 28 10:49:26 PM UTC 24 Aug 28 10:49:30 PM UTC 24 83965157 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.4208944914 Aug 28 10:49:27 PM UTC 24 Aug 28 10:49:30 PM UTC 24 82023675 ps
T1801 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2688369780 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:31 PM UTC 24 82918781 ps
T1802 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1789474789 Aug 28 10:49:27 PM UTC 24 Aug 28 10:49:31 PM UTC 24 328143548 ps
T1803 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1991784529 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:31 PM UTC 24 26960208 ps
T1804 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4113247612 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:31 PM UTC 24 26975638 ps
T1805 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1424008082 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:31 PM UTC 24 229240166 ps
T1806 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3954663448 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:32 PM UTC 24 137884272 ps
T1807 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.294591142 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 17213323 ps
T1808 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.78874274 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 20928767 ps
T1809 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.3268805297 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 20477091 ps
T1810 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3406104034 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 22003265 ps
T1811 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2186753915 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 33365848 ps
T1812 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.1204352544 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:32 PM UTC 24 20087352 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3007982301 Aug 28 10:49:30 PM UTC 24 Aug 28 10:49:33 PM UTC 24 18061924 ps
T1813 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.4271924361 Aug 28 10:49:29 PM UTC 24 Aug 28 10:49:33 PM UTC 24 1541968554 ps
T1814 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3480941099 Aug 28 10:49:31 PM UTC 24 Aug 28 10:49:34 PM UTC 24 18974509 ps
T1815 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1275168991 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 46515307 ps
T1816 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2031130137 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 40832677 ps
T1817 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.87712116 Aug 28 10:49:31 PM UTC 24 Aug 28 10:49:34 PM UTC 24 18380671 ps
T1818 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.1642510857 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 17483238 ps
T1819 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.3301410593 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 52250374 ps
T1820 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.4222570753 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 39955887 ps
T1821 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.3484147090 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 23892502 ps
T1822 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.1107119971 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 21643412 ps
T1823 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.1547692823 Aug 28 10:49:32 PM UTC 24 Aug 28 10:49:34 PM UTC 24 18448373 ps
T1824 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2482518548 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 19736918 ps
T1825 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.456789759 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 43143049 ps
T1826 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.189664140 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 44069877 ps
T1827 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1123751249 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 19266373 ps
T1828 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1304031837 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 21746784 ps
T1829 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3650830428 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 31322396 ps
T1830 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.3243438532 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 38810755 ps
T1831 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3482979611 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:35 PM UTC 24 21811288 ps
T1832 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.827541626 Aug 28 10:49:33 PM UTC 24 Aug 28 10:49:36 PM UTC 24 32471008 ps
T1833 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.766108518 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 77638148 ps
T1834 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.2629455473 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 16349461 ps
T1835 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.717681286 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 29277200 ps
T1836 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1307479476 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 19826460 ps
T1837 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.225443799 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 27209511 ps
T1838 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3359751087 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 38580662 ps
T1839 /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.4243143512 Aug 28 10:49:35 PM UTC 24 Aug 28 10:49:37 PM UTC 24 52125868 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.1584285722
Short name T4
Test name
Test status
Simulation time 5120030752 ps
CPU time 30.36 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:22:12 PM UTC 24
Peak memory 276704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158428
5722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.1584285722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.2868959636
Short name T11
Test name
Test status
Simulation time 3760001319 ps
CPU time 8.53 seconds
Started Aug 28 10:21:32 PM UTC 24
Finished Aug 28 10:21:42 PM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868959636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2868959636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.1798749149
Short name T57
Test name
Test status
Simulation time 9461386881 ps
CPU time 14.62 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:21:54 PM UTC 24
Peak memory 227464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798749149 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1798749149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.3908996636
Short name T203
Test name
Test status
Simulation time 12509605732 ps
CPU time 477.37 seconds
Started Aug 28 10:38:14 PM UTC 24
Finished Aug 28 10:46:17 PM UTC 24
Peak memory 2888212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908996636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3908996636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.851187872
Short name T109
Test name
Test status
Simulation time 553104775 ps
CPU time 2.93 seconds
Started Aug 28 10:48:59 PM UTC 24
Finished Aug 28 10:49:03 PM UTC 24
Peak memory 215252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851187872 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.851187872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.2220774758
Short name T18
Test name
Test status
Simulation time 75991535 ps
CPU time 1.98 seconds
Started Aug 28 10:22:08 PM UTC 24
Finished Aug 28 10:22:12 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220774758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2220774758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.3489401026
Short name T42
Test name
Test status
Simulation time 9970845569 ps
CPU time 53.66 seconds
Started Aug 28 10:21:47 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 931988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489401026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3489401026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.161786293
Short name T65
Test name
Test status
Simulation time 832976718 ps
CPU time 2.39 seconds
Started Aug 28 10:22:22 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 233544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617862
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_txstretch.161786293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_override.4135070163
Short name T1
Test name
Test status
Simulation time 66392892 ps
CPU time 0.97 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:21:25 PM UTC 24
Peak memory 215668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135070163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4135070163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.1561294256
Short name T204
Test name
Test status
Simulation time 62771745 ps
CPU time 1.25 seconds
Started Aug 28 10:21:35 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 246796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561294256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1561294256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.3066796098
Short name T19
Test name
Test status
Simulation time 2178526049 ps
CPU time 46.11 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:22:11 PM UTC 24
Peak memory 352720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066796098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3066796098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3108506563
Short name T52
Test name
Test status
Simulation time 915118750 ps
CPU time 4.21 seconds
Started Aug 28 10:25:04 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108506
563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3108506563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.917577971
Short name T26
Test name
Test status
Simulation time 9239322255 ps
CPU time 207.81 seconds
Started Aug 28 10:45:27 PM UTC 24
Finished Aug 28 10:48:58 PM UTC 24
Peak memory 712948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917577971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.917577971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.2121483163
Short name T40
Test name
Test status
Simulation time 123182139 ps
CPU time 6.81 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:21:45 PM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121483163 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.2121483163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.3248336486
Short name T68
Test name
Test status
Simulation time 450711512 ps
CPU time 2.67 seconds
Started Aug 28 10:21:34 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248336
486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.3248336486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3214500267
Short name T235
Test name
Test status
Simulation time 90431648 ps
CPU time 1.82 seconds
Started Aug 28 10:49:04 PM UTC 24
Finished Aug 28 10:49:06 PM UTC 24
Peak memory 214668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214500267 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3214500267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.1242615704
Short name T23
Test name
Test status
Simulation time 213515933 ps
CPU time 3.49 seconds
Started Aug 28 10:28:58 PM UTC 24
Finished Aug 28 10:29:03 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242615704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1242615704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.362773794
Short name T64
Test name
Test status
Simulation time 55205481691 ps
CPU time 97.81 seconds
Started Aug 28 10:23:17 PM UTC 24
Finished Aug 28 10:24:57 PM UTC 24
Peak memory 985608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362773
794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.362773794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.1336613150
Short name T207
Test name
Test status
Simulation time 82402415 ps
CPU time 3.14 seconds
Started Aug 28 10:48:56 PM UTC 24
Finished Aug 28 10:49:00 PM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336613150 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1336613150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.1568751469
Short name T51
Test name
Test status
Simulation time 986752748 ps
CPU time 6.77 seconds
Started Aug 28 10:21:30 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1568751469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1568751469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.1842063507
Short name T59
Test name
Test status
Simulation time 2875120453 ps
CPU time 5.87 seconds
Started Aug 28 10:38:40 PM UTC 24
Finished Aug 28 10:38:46 PM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842063
507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.1842063507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.1924414472
Short name T853
Test name
Test status
Simulation time 10060069731 ps
CPU time 625.43 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:32:25 PM UTC 24
Peak memory 1032424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924414472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1924414472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.1387452963
Short name T257
Test name
Test status
Simulation time 153913342 ps
CPU time 2.12 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:24:42 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387452963 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.1387452963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.1309653355
Short name T295
Test name
Test status
Simulation time 83406785 ps
CPU time 0.97 seconds
Started Aug 28 10:49:10 PM UTC 24
Finished Aug 28 10:49:12 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309653355 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1309653355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.2936724764
Short name T86
Test name
Test status
Simulation time 3414016931 ps
CPU time 44.48 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:22:09 PM UTC 24
Peak memory 649680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936724764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2936724764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.3138844387
Short name T289
Test name
Test status
Simulation time 2203936756 ps
CPU time 4.71 seconds
Started Aug 28 10:24:29 PM UTC 24
Finished Aug 28 10:24:35 PM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138844
387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermark
s_acq.3138844387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_alert_test.4051874595
Short name T102
Test name
Test status
Simulation time 16373998 ps
CPU time 0.91 seconds
Started Aug 28 10:21:35 PM UTC 24
Finished Aug 28 10:21:37 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051874595 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.4051874595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3908943568
Short name T14
Test name
Test status
Simulation time 28329719714 ps
CPU time 67.5 seconds
Started Aug 28 10:21:24 PM UTC 24
Finished Aug 28 10:22:33 PM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908943568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3908943568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.3378267098
Short name T303
Test name
Test status
Simulation time 20237105 ps
CPU time 0.99 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378267098 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3378267098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.649565886
Short name T12
Test name
Test status
Simulation time 3185467468 ps
CPU time 12.9 seconds
Started Aug 28 10:21:43 PM UTC 24
Finished Aug 28 10:21:57 PM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649565886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.649565886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.2316667203
Short name T89
Test name
Test status
Simulation time 1756833151 ps
CPU time 23.29 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:22:16 PM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316667203 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.2316667203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.4287879729
Short name T1788
Test name
Test status
Simulation time 18567380 ps
CPU time 1.05 seconds
Started Aug 28 10:49:25 PM UTC 24
Finished Aug 28 10:49:27 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287879729 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4287879729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.3366124678
Short name T211
Test name
Test status
Simulation time 895211744 ps
CPU time 3.68 seconds
Started Aug 28 10:49:00 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 215308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366124678 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3366124678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.629025942
Short name T134
Test name
Test status
Simulation time 1975992284 ps
CPU time 20.34 seconds
Started Aug 28 10:22:23 PM UTC 24
Finished Aug 28 10:22:45 PM UTC 24
Peak memory 346156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629025942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.629025942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.2018869981
Short name T227
Test name
Test status
Simulation time 46467023 ps
CPU time 0.96 seconds
Started Aug 28 10:48:57 PM UTC 24
Finished Aug 28 10:48:59 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018869981 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2018869981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_override.351671683
Short name T152
Test name
Test status
Simulation time 26991351 ps
CPU time 1.03 seconds
Started Aug 28 10:26:08 PM UTC 24
Finished Aug 28 10:26:10 PM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351671683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.351671683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.638270154
Short name T5
Test name
Test status
Simulation time 212156364 ps
CPU time 1.66 seconds
Started Aug 28 10:21:28 PM UTC 24
Finished Aug 28 10:21:31 PM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6382701
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.638270154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_override.1184042603
Short name T277
Test name
Test status
Simulation time 26264692 ps
CPU time 1.07 seconds
Started Aug 28 10:25:33 PM UTC 24
Finished Aug 28 10:25:35 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184042603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1184042603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.3613303096
Short name T265
Test name
Test status
Simulation time 1551213649 ps
CPU time 28.17 seconds
Started Aug 28 10:31:05 PM UTC 24
Finished Aug 28 10:31:35 PM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613303096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3613303096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.915754961
Short name T259
Test name
Test status
Simulation time 254439201 ps
CPU time 1.53 seconds
Started Aug 28 10:42:54 PM UTC 24
Finished Aug 28 10:42:56 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915754961 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.915754961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.3597784348
Short name T272
Test name
Test status
Simulation time 343114925 ps
CPU time 16.85 seconds
Started Aug 28 10:45:48 PM UTC 24
Finished Aug 28 10:46:06 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597784348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3597784348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_stress_all.908682501
Short name T296
Test name
Test status
Simulation time 41212081073 ps
CPU time 618.92 seconds
Started Aug 28 10:46:02 PM UTC 24
Finished Aug 28 10:56:28 PM UTC 24
Peak memory 2642264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908682501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.908682501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.3205266136
Short name T310
Test name
Test status
Simulation time 5180031380 ps
CPU time 9.41 seconds
Started Aug 28 10:46:53 PM UTC 24
Finished Aug 28 10:47:04 PM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3205266136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.3205266136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.3397823772
Short name T494
Test name
Test status
Simulation time 150011980 ps
CPU time 2.88 seconds
Started Aug 28 10:26:01 PM UTC 24
Finished Aug 28 10:26:04 PM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397823772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3397823772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.1692128383
Short name T214
Test name
Test status
Simulation time 38387994 ps
CPU time 1.77 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 214596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692128383 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1692128383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.4266131012
Short name T25
Test name
Test status
Simulation time 170795854 ps
CPU time 3.7 seconds
Started Aug 28 10:35:03 PM UTC 24
Finished Aug 28 10:35:08 PM UTC 24
Peak memory 237324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266131012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.4266131012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.2898897196
Short name T640
Test name
Test status
Simulation time 53870379508 ps
CPU time 115.89 seconds
Started Aug 28 10:26:24 PM UTC 24
Finished Aug 28 10:28:22 PM UTC 24
Peak memory 1118628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289889
7196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.2898897196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.2798208143
Short name T218
Test name
Test status
Simulation time 151952165 ps
CPU time 3.05 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798208143 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2798208143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_perf.2944757621
Short name T45
Test name
Test status
Simulation time 2538528227 ps
CPU time 169.56 seconds
Started Aug 28 10:30:40 PM UTC 24
Finished Aug 28 10:33:32 PM UTC 24
Peak memory 823576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944757621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2944757621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.680832223
Short name T279
Test name
Test status
Simulation time 68760404 ps
CPU time 1.77 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:29 PM UTC 24
Peak memory 214592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680832223 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.680832223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.4019005477
Short name T2
Test name
Test status
Simulation time 214725283 ps
CPU time 1.63 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:21:26 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019005477 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.4019005477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.629882062
Short name T75
Test name
Test status
Simulation time 580684120 ps
CPU time 7.29 seconds
Started Aug 28 10:21:32 PM UTC 24
Finished Aug 28 10:21:41 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6298820
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.629882062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.4141673720
Short name T268
Test name
Test status
Simulation time 449264513 ps
CPU time 16.77 seconds
Started Aug 28 10:25:28 PM UTC 24
Finished Aug 28 10:25:46 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141673720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.4141673720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.2683252954
Short name T412
Test name
Test status
Simulation time 2933317459 ps
CPU time 12.78 seconds
Started Aug 28 10:25:14 PM UTC 24
Finished Aug 28 10:25:28 PM UTC 24
Peak memory 233140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683252954 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.2683252954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.2294103920
Short name T286
Test name
Test status
Simulation time 800265486 ps
CPU time 26.54 seconds
Started Aug 28 10:34:37 PM UTC 24
Finished Aug 28 10:35:05 PM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294103920 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.2294103920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_mode_toggle.4058979020
Short name T276
Test name
Test status
Simulation time 230455963 ps
CPU time 9.57 seconds
Started Aug 28 10:35:57 PM UTC 24
Finished Aug 28 10:36:08 PM UTC 24
Peak memory 258144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058979020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4058979020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.1613236779
Short name T313
Test name
Test status
Simulation time 264223141 ps
CPU time 2.15 seconds
Started Aug 28 10:35:53 PM UTC 24
Finished Aug 28 10:35:56 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613236
779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.1613236779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.2226021846
Short name T220
Test name
Test status
Simulation time 51866353 ps
CPU time 1.83 seconds
Started Aug 28 10:49:24 PM UTC 24
Finished Aug 28 10:49:27 PM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226021846 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2226021846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.1118170190
Short name T212
Test name
Test status
Simulation time 466569445 ps
CPU time 3.19 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:06 PM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118170190 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1118170190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_hrst.550390164
Short name T199
Test name
Test status
Simulation time 810686943 ps
CPU time 1.98 seconds
Started Aug 28 10:21:41 PM UTC 24
Finished Aug 28 10:21:44 PM UTC 24
Peak memory 226500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5503901
64 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_hrst.550390164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_mode_toggle.1516991293
Short name T83
Test name
Test status
Simulation time 142608680 ps
CPU time 3.66 seconds
Started Aug 28 10:26:25 PM UTC 24
Finished Aug 28 10:26:30 PM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516991293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1516991293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.3526381650
Short name T34
Test name
Test status
Simulation time 510723358 ps
CPU time 3.59 seconds
Started Aug 28 10:31:24 PM UTC 24
Finished Aug 28 10:31:29 PM UTC 24
Peak memory 226772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526381650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3526381650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1694398195
Short name T234
Test name
Test status
Simulation time 39630504 ps
CPU time 2.03 seconds
Started Aug 28 10:48:57 PM UTC 24
Finished Aug 28 10:49:00 PM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694398195 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1694398195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.802188557
Short name T1742
Test name
Test status
Simulation time 372583851 ps
CPU time 5.39 seconds
Started Aug 28 10:48:57 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 215216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802188557 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.802188557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.133687939
Short name T159
Test name
Test status
Simulation time 28768886 ps
CPU time 1.07 seconds
Started Aug 28 10:48:57 PM UTC 24
Finished Aug 28 10:48:59 PM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133687939 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.133687939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1494740656
Short name T206
Test name
Test status
Simulation time 25514100 ps
CPU time 1.09 seconds
Started Aug 28 10:48:58 PM UTC 24
Finished Aug 28 10:49:00 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1494740656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1494740656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2738687277
Short name T137
Test name
Test status
Simulation time 20246864 ps
CPU time 1.08 seconds
Started Aug 28 10:48:57 PM UTC 24
Finished Aug 28 10:48:59 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738687277 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2738687277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1988177400
Short name T108
Test name
Test status
Simulation time 110919677 ps
CPU time 1.87 seconds
Started Aug 28 10:48:58 PM UTC 24
Finished Aug 28 10:49:00 PM UTC 24
Peak memory 214640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988177400 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.1988177400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.231097523
Short name T205
Test name
Test status
Simulation time 29119453 ps
CPU time 1.82 seconds
Started Aug 28 10:48:56 PM UTC 24
Finished Aug 28 10:48:59 PM UTC 24
Peak memory 214664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231097523 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.231097523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.2561852433
Short name T1741
Test name
Test status
Simulation time 61355736 ps
CPU time 1.6 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561852433 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2561852433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.2359594867
Short name T112
Test name
Test status
Simulation time 1045173309 ps
CPU time 6.03 seconds
Started Aug 28 10:49:00 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359594867 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2359594867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2151407668
Short name T1740
Test name
Test status
Simulation time 50181191 ps
CPU time 1.05 seconds
Started Aug 28 10:49:00 PM UTC 24
Finished Aug 28 10:49:02 PM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151407668 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2151407668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3925095517
Short name T223
Test name
Test status
Simulation time 90928536 ps
CPU time 1.57 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3925095517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3925095517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2497637376
Short name T246
Test name
Test status
Simulation time 50837101 ps
CPU time 1.16 seconds
Started Aug 28 10:49:00 PM UTC 24
Finished Aug 28 10:49:02 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497637376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2497637376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2875957212
Short name T138
Test name
Test status
Simulation time 45394624 ps
CPU time 1.03 seconds
Started Aug 28 10:49:00 PM UTC 24
Finished Aug 28 10:49:02 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875957212 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2875957212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2659491728
Short name T247
Test name
Test status
Simulation time 55160747 ps
CPU time 1.78 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 214640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659491728 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.2659491728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3913307744
Short name T1766
Test name
Test status
Simulation time 39052273 ps
CPU time 1.23 seconds
Started Aug 28 10:49:19 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3913307744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3913307744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.4249326472
Short name T243
Test name
Test status
Simulation time 30810889 ps
CPU time 0.94 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249326472 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.4249326472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.110187498
Short name T1768
Test name
Test status
Simulation time 164910937 ps
CPU time 1.55 seconds
Started Aug 28 10:49:18 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110187498 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.110187498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3335960722
Short name T1765
Test name
Test status
Simulation time 53158557 ps
CPU time 1.88 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:20 PM UTC 24
Peak memory 214668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335960722 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3335960722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2640322817
Short name T1771
Test name
Test status
Simulation time 253370448 ps
CPU time 3.17 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 215288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640322817 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2640322817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3716995475
Short name T1776
Test name
Test status
Simulation time 54784311 ps
CPU time 2.25 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:23 PM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3716995475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3716995475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.1101587976
Short name T1767
Test name
Test status
Simulation time 50912474 ps
CPU time 1.06 seconds
Started Aug 28 10:49:19 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101587976 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1101587976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3130141275
Short name T305
Test name
Test status
Simulation time 76824699 ps
CPU time 1.04 seconds
Started Aug 28 10:49:19 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130141275 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3130141275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.709246053
Short name T1772
Test name
Test status
Simulation time 109967949 ps
CPU time 1.19 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:22 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709246053 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.709246053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.607298813
Short name T1769
Test name
Test status
Simulation time 201194327 ps
CPU time 1.65 seconds
Started Aug 28 10:49:19 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607298813 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.607298813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2426299528
Short name T1770
Test name
Test status
Simulation time 48591803 ps
CPU time 1.79 seconds
Started Aug 28 10:49:19 PM UTC 24
Finished Aug 28 10:49:21 PM UTC 24
Peak memory 214640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426299528 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2426299528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1659822568
Short name T1775
Test name
Test status
Simulation time 27631142 ps
CPU time 1.36 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:23 PM UTC 24
Peak memory 214748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1659822568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1659822568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.850786253
Short name T233
Test name
Test status
Simulation time 89381568 ps
CPU time 1.14 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:22 PM UTC 24
Peak memory 214520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850786253 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.850786253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3163731984
Short name T300
Test name
Test status
Simulation time 20650165 ps
CPU time 1.06 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:22 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163731984 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3163731984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3519635101
Short name T1774
Test name
Test status
Simulation time 20393952 ps
CPU time 1.37 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:23 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519635101 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.3519635101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1524734370
Short name T1781
Test name
Test status
Simulation time 101929102 ps
CPU time 3.57 seconds
Started Aug 28 10:49:20 PM UTC 24
Finished Aug 28 10:49:25 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524734370 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1524734370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2025116548
Short name T1779
Test name
Test status
Simulation time 95478410 ps
CPU time 1.28 seconds
Started Aug 28 10:49:22 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2025116548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2025116548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.2604714449
Short name T241
Test name
Test status
Simulation time 27889837 ps
CPU time 0.99 seconds
Started Aug 28 10:49:22 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604714449 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2604714449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.782463462
Short name T1773
Test name
Test status
Simulation time 40385821 ps
CPU time 1 seconds
Started Aug 28 10:49:22 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782463462 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.782463462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1578881769
Short name T1778
Test name
Test status
Simulation time 177880027 ps
CPU time 1.37 seconds
Started Aug 28 10:49:22 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578881769 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.1578881769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.1644721158
Short name T1777
Test name
Test status
Simulation time 50852548 ps
CPU time 1.47 seconds
Started Aug 28 10:49:21 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 214636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644721158 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1644721158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3522797983
Short name T1780
Test name
Test status
Simulation time 56367773 ps
CPU time 2.02 seconds
Started Aug 28 10:49:22 PM UTC 24
Finished Aug 28 10:49:25 PM UTC 24
Peak memory 215204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522797983 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3522797983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1242051978
Short name T1785
Test name
Test status
Simulation time 45684639 ps
CPU time 1.79 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:26 PM UTC 24
Peak memory 231844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1242051978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1242051978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.872527302
Short name T244
Test name
Test status
Simulation time 32220420 ps
CPU time 0.99 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:25 PM UTC 24
Peak memory 214520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872527302 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.872527302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.4268066058
Short name T1782
Test name
Test status
Simulation time 83120155 ps
CPU time 1.06 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:25 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268066058 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.4268066058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2221236772
Short name T1783
Test name
Test status
Simulation time 142631439 ps
CPU time 1.2 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:25 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221236772 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.2221236772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.2822044592
Short name T1786
Test name
Test status
Simulation time 31219871 ps
CPU time 2.04 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:26 PM UTC 24
Peak memory 215368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822044592 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2822044592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.2364803410
Short name T1784
Test name
Test status
Simulation time 49585812 ps
CPU time 1.55 seconds
Started Aug 28 10:49:23 PM UTC 24
Finished Aug 28 10:49:26 PM UTC 24
Peak memory 214608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364803410 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2364803410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1362506718
Short name T1790
Test name
Test status
Simulation time 35454614 ps
CPU time 1.46 seconds
Started Aug 28 10:49:25 PM UTC 24
Finished Aug 28 10:49:27 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1362506718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1362506718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.3365910079
Short name T245
Test name
Test status
Simulation time 29634388 ps
CPU time 1.12 seconds
Started Aug 28 10:49:24 PM UTC 24
Finished Aug 28 10:49:27 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365910079 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3365910079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.2297626072
Short name T1787
Test name
Test status
Simulation time 15673715 ps
CPU time 0.86 seconds
Started Aug 28 10:49:24 PM UTC 24
Finished Aug 28 10:49:26 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297626072 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2297626072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2145911762
Short name T1789
Test name
Test status
Simulation time 39681863 ps
CPU time 1.39 seconds
Started Aug 28 10:49:25 PM UTC 24
Finished Aug 28 10:49:27 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145911762 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.2145911762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.999149740
Short name T1793
Test name
Test status
Simulation time 265305182 ps
CPU time 2.78 seconds
Started Aug 28 10:49:24 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 215160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999149740 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.999149740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.406042440
Short name T1795
Test name
Test status
Simulation time 111703063 ps
CPU time 1.34 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 214632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=406042440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.406042440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.785009033
Short name T1791
Test name
Test status
Simulation time 55406530 ps
CPU time 1.07 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 214520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785009033 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.785009033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.382762277
Short name T1799
Test name
Test status
Simulation time 209679795 ps
CPU time 3.89 seconds
Started Aug 28 10:49:25 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 215376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382762277 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.382762277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.2323586751
Short name T221
Test name
Test status
Simulation time 90585315 ps
CPU time 2.33 seconds
Started Aug 28 10:49:25 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323586751 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2323586751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.425708112
Short name T1797
Test name
Test status
Simulation time 31405926 ps
CPU time 1.1 seconds
Started Aug 28 10:49:27 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=425708112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.425708112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.916110215
Short name T1794
Test name
Test status
Simulation time 65378069 ps
CPU time 1.09 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 214520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916110215 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.916110215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.3610384650
Short name T1792
Test name
Test status
Simulation time 49637807 ps
CPU time 0.99 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610384650 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3610384650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2363065053
Short name T1798
Test name
Test status
Simulation time 32661311 ps
CPU time 1.19 seconds
Started Aug 28 10:49:27 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363065053 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.2363065053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.665628654
Short name T1800
Test name
Test status
Simulation time 83965157 ps
CPU time 2.76 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 215376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665628654 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.665628654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.2688299034
Short name T1796
Test name
Test status
Simulation time 176509572 ps
CPU time 1.69 seconds
Started Aug 28 10:49:26 PM UTC 24
Finished Aug 28 10:49:29 PM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688299034 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2688299034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1424008082
Short name T1805
Test name
Test status
Simulation time 229240166 ps
CPU time 1.3 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:31 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1424008082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1424008082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.2688369780
Short name T1801
Test name
Test status
Simulation time 82918781 ps
CPU time 1.06 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:31 PM UTC 24
Peak memory 214696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688369780 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2688369780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.697580479
Short name T297
Test name
Test status
Simulation time 31690120 ps
CPU time 1.05 seconds
Started Aug 28 10:49:27 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697580479 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.697580479
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4113247612
Short name T1804
Test name
Test status
Simulation time 26975638 ps
CPU time 1.42 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:31 PM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113247612 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.4113247612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.1789474789
Short name T1802
Test name
Test status
Simulation time 328143548 ps
CPU time 2.15 seconds
Started Aug 28 10:49:27 PM UTC 24
Finished Aug 28 10:49:31 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789474789 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1789474789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.4208944914
Short name T226
Test name
Test status
Simulation time 82023675 ps
CPU time 1.88 seconds
Started Aug 28 10:49:27 PM UTC 24
Finished Aug 28 10:49:30 PM UTC 24
Peak memory 214700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208944914 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.4208944914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2186753915
Short name T1811
Test name
Test status
Simulation time 33365848 ps
CPU time 1.28 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2186753915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2186753915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.294591142
Short name T1807
Test name
Test status
Simulation time 17213323 ps
CPU time 1.06 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294591142 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.294591142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1991784529
Short name T1803
Test name
Test status
Simulation time 26960208 ps
CPU time 0.97 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:31 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991784529 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1991784529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3406104034
Short name T1810
Test name
Test status
Simulation time 22003265 ps
CPU time 1.14 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406104034 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.3406104034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.3954663448
Short name T1806
Test name
Test status
Simulation time 137884272 ps
CPU time 2.26 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954663448 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3954663448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.4271924361
Short name T1813
Test name
Test status
Simulation time 1541968554 ps
CPU time 2.83 seconds
Started Aug 28 10:49:29 PM UTC 24
Finished Aug 28 10:49:33 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271924361 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4271924361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.348895410
Short name T1744
Test name
Test status
Simulation time 1173021800 ps
CPU time 5.89 seconds
Started Aug 28 10:49:03 PM UTC 24
Finished Aug 28 10:49:09 PM UTC 24
Peak memory 215276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348895410 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.348895410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.466541303
Short name T110
Test name
Test status
Simulation time 20395290 ps
CPU time 1.16 seconds
Started Aug 28 10:49:02 PM UTC 24
Finished Aug 28 10:49:05 PM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466541303 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.466541303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1681661933
Short name T111
Test name
Test status
Simulation time 77599450 ps
CPU time 1.19 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1681661933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1681661933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.4179256138
Short name T248
Test name
Test status
Simulation time 131462105 ps
CPU time 1 seconds
Started Aug 28 10:49:03 PM UTC 24
Finished Aug 28 10:49:04 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179256138 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.4179256138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1837439866
Short name T139
Test name
Test status
Simulation time 139614519 ps
CPU time 1 seconds
Started Aug 28 10:49:01 PM UTC 24
Finished Aug 28 10:49:03 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837439866 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1837439866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.4008624952
Short name T113
Test name
Test status
Simulation time 668582379 ps
CPU time 1.49 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008624952 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.4008624952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.78874274
Short name T1808
Test name
Test status
Simulation time 20928767 ps
CPU time 1.04 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78874274 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.78874274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.3268805297
Short name T1809
Test name
Test status
Simulation time 20477091 ps
CPU time 1.03 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268805297 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.3268805297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.1204352544
Short name T1812
Test name
Test status
Simulation time 20087352 ps
CPU time 1.1 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:32 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204352544 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1204352544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.3007982301
Short name T298
Test name
Test status
Simulation time 18061924 ps
CPU time 1.12 seconds
Started Aug 28 10:49:30 PM UTC 24
Finished Aug 28 10:49:33 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007982301 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3007982301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.87712116
Short name T1817
Test name
Test status
Simulation time 18380671 ps
CPU time 1 seconds
Started Aug 28 10:49:31 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87712116 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.87712116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.3480941099
Short name T1814
Test name
Test status
Simulation time 18974509 ps
CPU time 0.97 seconds
Started Aug 28 10:49:31 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480941099 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3480941099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.1275168991
Short name T1815
Test name
Test status
Simulation time 46515307 ps
CPU time 0.94 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275168991 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1275168991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.1642510857
Short name T1818
Test name
Test status
Simulation time 17483238 ps
CPU time 1.05 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642510857 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1642510857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.3301410593
Short name T1819
Test name
Test status
Simulation time 52250374 ps
CPU time 0.99 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301410593 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3301410593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.4222570753
Short name T1820
Test name
Test status
Simulation time 39955887 ps
CPU time 0.98 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222570753 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4222570753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.549978948
Short name T116
Test name
Test status
Simulation time 128518795 ps
CPU time 3.27 seconds
Started Aug 28 10:49:06 PM UTC 24
Finished Aug 28 10:49:11 PM UTC 24
Peak memory 215032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549978948 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.549978948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.3291953445
Short name T1747
Test name
Test status
Simulation time 138805066 ps
CPU time 6.26 seconds
Started Aug 28 10:49:06 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 215252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291953445 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3291953445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1312543530
Short name T1743
Test name
Test status
Simulation time 134040584 ps
CPU time 1.13 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312543530 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1312543530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1389813916
Short name T216
Test name
Test status
Simulation time 178832900 ps
CPU time 1.66 seconds
Started Aug 28 10:49:07 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 224684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1389813916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1389813916
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3407820208
Short name T236
Test name
Test status
Simulation time 46594741 ps
CPU time 0.98 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407820208 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3407820208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.810975387
Short name T299
Test name
Test status
Simulation time 18667971 ps
CPU time 1.06 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810975387 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.810975387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4100187375
Short name T114
Test name
Test status
Simulation time 64124859 ps
CPU time 1.66 seconds
Started Aug 28 10:49:06 PM UTC 24
Finished Aug 28 10:49:09 PM UTC 24
Peak memory 214600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100187375 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.4100187375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1155082539
Short name T215
Test name
Test status
Simulation time 169983744 ps
CPU time 3.69 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155082539 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1155082539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3543811824
Short name T213
Test name
Test status
Simulation time 47744508 ps
CPU time 1.9 seconds
Started Aug 28 10:49:05 PM UTC 24
Finished Aug 28 10:49:08 PM UTC 24
Peak memory 214732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543811824 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3543811824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.2031130137
Short name T1816
Test name
Test status
Simulation time 40832677 ps
CPU time 0.82 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031130137 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2031130137
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.1107119971
Short name T1822
Test name
Test status
Simulation time 21643412 ps
CPU time 1.01 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107119971 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.1107119971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.1547692823
Short name T1823
Test name
Test status
Simulation time 18448373 ps
CPU time 0.98 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547692823 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1547692823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.3484147090
Short name T1821
Test name
Test status
Simulation time 23892502 ps
CPU time 0.92 seconds
Started Aug 28 10:49:32 PM UTC 24
Finished Aug 28 10:49:34 PM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484147090 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3484147090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2482518548
Short name T1824
Test name
Test status
Simulation time 19736918 ps
CPU time 0.94 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482518548 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2482518548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.456789759
Short name T1825
Test name
Test status
Simulation time 43143049 ps
CPU time 0.94 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456789759 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.456789759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.189664140
Short name T1826
Test name
Test status
Simulation time 44069877 ps
CPU time 0.95 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189664140 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.189664140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.1304031837
Short name T1828
Test name
Test status
Simulation time 21746784 ps
CPU time 1.01 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304031837 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1304031837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1123751249
Short name T1827
Test name
Test status
Simulation time 19266373 ps
CPU time 0.95 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123751249 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1123751249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3650830428
Short name T1829
Test name
Test status
Simulation time 31322396 ps
CPU time 0.98 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650830428 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3650830428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.69351981
Short name T238
Test name
Test status
Simulation time 183006572 ps
CPU time 1.84 seconds
Started Aug 28 10:49:09 PM UTC 24
Finished Aug 28 10:49:13 PM UTC 24
Peak memory 214640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69351981 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.69351981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.4260882679
Short name T1750
Test name
Test status
Simulation time 706182894 ps
CPU time 3.95 seconds
Started Aug 28 10:49:09 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260882679 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.4260882679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.540702245
Short name T135
Test name
Test status
Simulation time 92583627 ps
CPU time 1.13 seconds
Started Aug 28 10:49:08 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 214628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540702245 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.540702245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1631678909
Short name T1746
Test name
Test status
Simulation time 27644486 ps
CPU time 1.26 seconds
Started Aug 28 10:49:10 PM UTC 24
Finished Aug 28 10:49:12 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1631678909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1631678909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2141074171
Short name T115
Test name
Test status
Simulation time 384205606 ps
CPU time 1.06 seconds
Started Aug 28 10:49:08 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141074171 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2141074171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.72545030
Short name T294
Test name
Test status
Simulation time 46785995 ps
CPU time 1.02 seconds
Started Aug 28 10:49:08 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72545030 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.72545030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2824483777
Short name T1745
Test name
Test status
Simulation time 36130158 ps
CPU time 1.25 seconds
Started Aug 28 10:49:09 PM UTC 24
Finished Aug 28 10:49:11 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824483777 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.2824483777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.540413993
Short name T231
Test name
Test status
Simulation time 117645847 ps
CPU time 2.53 seconds
Started Aug 28 10:49:08 PM UTC 24
Finished Aug 28 10:49:11 PM UTC 24
Peak memory 215284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540413993 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.540413993
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.658938700
Short name T117
Test name
Test status
Simulation time 185186114 ps
CPU time 2.4 seconds
Started Aug 28 10:49:08 PM UTC 24
Finished Aug 28 10:49:11 PM UTC 24
Peak memory 215188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658938700 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.658938700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.3243438532
Short name T1830
Test name
Test status
Simulation time 38810755 ps
CPU time 1.03 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243438532 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3243438532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.827541626
Short name T1832
Test name
Test status
Simulation time 32471008 ps
CPU time 1.11 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:36 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827541626 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.827541626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3482979611
Short name T1831
Test name
Test status
Simulation time 21811288 ps
CPU time 0.92 seconds
Started Aug 28 10:49:33 PM UTC 24
Finished Aug 28 10:49:35 PM UTC 24
Peak memory 214560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482979611 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3482979611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.766108518
Short name T1833
Test name
Test status
Simulation time 77638148 ps
CPU time 1.02 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766108518 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.766108518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.717681286
Short name T1835
Test name
Test status
Simulation time 29277200 ps
CPU time 1.1 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717681286 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.717681286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1307479476
Short name T1836
Test name
Test status
Simulation time 19826460 ps
CPU time 1.06 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307479476 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1307479476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.2629455473
Short name T1834
Test name
Test status
Simulation time 16349461 ps
CPU time 0.89 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629455473 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2629455473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3359751087
Short name T1838
Test name
Test status
Simulation time 38580662 ps
CPU time 1.04 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359751087 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3359751087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.225443799
Short name T1837
Test name
Test status
Simulation time 27209511 ps
CPU time 0.97 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225443799 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.225443799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.4243143512
Short name T1839
Test name
Test status
Simulation time 52125868 ps
CPU time 1.02 seconds
Started Aug 28 10:49:35 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243143512 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.4243143512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.439674817
Short name T1748
Test name
Test status
Simulation time 29015017 ps
CPU time 1.16 seconds
Started Aug 28 10:49:11 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=439674817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.439674817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.2802817125
Short name T237
Test name
Test status
Simulation time 55299746 ps
CPU time 1.14 seconds
Started Aug 28 10:49:10 PM UTC 24
Finished Aug 28 10:49:13 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802817125 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2802817125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1072269849
Short name T1749
Test name
Test status
Simulation time 32680434 ps
CPU time 1.29 seconds
Started Aug 28 10:49:11 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 214208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072269849 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.1072269849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3070676905
Short name T222
Test name
Test status
Simulation time 75357928 ps
CPU time 2.5 seconds
Started Aug 28 10:49:10 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 215432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070676905 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3070676905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.4013213704
Short name T217
Test name
Test status
Simulation time 79090673 ps
CPU time 2.14 seconds
Started Aug 28 10:49:10 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 215184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013213704 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4013213704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4017404749
Short name T1752
Test name
Test status
Simulation time 86713600 ps
CPU time 1.17 seconds
Started Aug 28 10:49:13 PM UTC 24
Finished Aug 28 10:49:15 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4017404749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4017404749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.739339610
Short name T239
Test name
Test status
Simulation time 28223334 ps
CPU time 1.09 seconds
Started Aug 28 10:49:12 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 214752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739339610 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.739339610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.2548039103
Short name T301
Test name
Test status
Simulation time 160533089 ps
CPU time 1.08 seconds
Started Aug 28 10:49:12 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 214548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548039103 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2548039103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3435533278
Short name T1751
Test name
Test status
Simulation time 71663596 ps
CPU time 1.23 seconds
Started Aug 28 10:49:12 PM UTC 24
Finished Aug 28 10:49:14 PM UTC 24
Peak memory 214652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435533278 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.3435533278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.3779672197
Short name T1753
Test name
Test status
Simulation time 1112693647 ps
CPU time 3.42 seconds
Started Aug 28 10:49:12 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779672197 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3779672197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1929428467
Short name T225
Test name
Test status
Simulation time 146786115 ps
CPU time 3.17 seconds
Started Aug 28 10:49:12 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 215312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929428467 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1929428467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4052949555
Short name T1754
Test name
Test status
Simulation time 101747393 ps
CPU time 1.04 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4052949555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4052949555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1784060068
Short name T1755
Test name
Test status
Simulation time 20422510 ps
CPU time 1.15 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784060068 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1784060068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2258985596
Short name T302
Test name
Test status
Simulation time 50407477 ps
CPU time 1.03 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258985596 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2258985596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.939925834
Short name T1757
Test name
Test status
Simulation time 34293169 ps
CPU time 1.24 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 214816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939925834 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.939925834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3825338649
Short name T1756
Test name
Test status
Simulation time 30470804 ps
CPU time 2.48 seconds
Started Aug 28 10:49:13 PM UTC 24
Finished Aug 28 10:49:16 PM UTC 24
Peak memory 215156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825338649 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3825338649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.4092378806
Short name T224
Test name
Test status
Simulation time 97501261 ps
CPU time 3.36 seconds
Started Aug 28 10:49:13 PM UTC 24
Finished Aug 28 10:49:17 PM UTC 24
Peak memory 215344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092378806 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.4092378806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.376505390
Short name T1760
Test name
Test status
Simulation time 33860601 ps
CPU time 2.22 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 215280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=376505390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.376505390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.3610544110
Short name T240
Test name
Test status
Simulation time 26793820 ps
CPU time 1.01 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:18 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610544110 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3610544110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.1629180858
Short name T1759
Test name
Test status
Simulation time 56892506 ps
CPU time 1.03 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:18 PM UTC 24
Peak memory 214564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629180858 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1629180858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.4257191302
Short name T1761
Test name
Test status
Simulation time 223131905 ps
CPU time 3.61 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 225480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257191302 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.4257191302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1998886234
Short name T1758
Test name
Test status
Simulation time 259025192 ps
CPU time 1.71 seconds
Started Aug 28 10:49:14 PM UTC 24
Finished Aug 28 10:49:17 PM UTC 24
Peak memory 214764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998886234 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1998886234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.646127019
Short name T1763
Test name
Test status
Simulation time 56384449 ps
CPU time 1.37 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:20 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=646127019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.646127019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3693275610
Short name T242
Test name
Test status
Simulation time 46250314 ps
CPU time 1.04 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 214692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693275610 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3693275610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.279406611
Short name T304
Test name
Test status
Simulation time 58018077 ps
CPU time 1.13 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:18 PM UTC 24
Peak memory 214568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279406611 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.279406611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1273416848
Short name T1764
Test name
Test status
Simulation time 29322136 ps
CPU time 1.79 seconds
Started Aug 28 10:49:17 PM UTC 24
Finished Aug 28 10:49:20 PM UTC 24
Peak memory 214660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273416848 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.1273416848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.3258641962
Short name T1762
Test name
Test status
Simulation time 121514134 ps
CPU time 2.22 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:19 PM UTC 24
Peak memory 215192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258641962 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3258641962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2925022252
Short name T219
Test name
Test status
Simulation time 302442066 ps
CPU time 2.68 seconds
Started Aug 28 10:49:16 PM UTC 24
Finished Aug 28 10:49:20 PM UTC 24
Peak memory 215180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925022252 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2925022252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.2031568990
Short name T3
Test name
Test status
Simulation time 283712177 ps
CPU time 3.32 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:30 PM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031568990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2031568990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.3722188677
Short name T28
Test name
Test status
Simulation time 351696801 ps
CPU time 17.75 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:21:42 PM UTC 24
Peak memory 288916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722188677 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.3722188677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.2586649124
Short name T10
Test name
Test status
Simulation time 565633576 ps
CPU time 10.33 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:21:35 PM UTC 24
Peak memory 243816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586649124 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.2586649124
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.3287005878
Short name T87
Test name
Test status
Simulation time 7546617113 ps
CPU time 88.87 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:22:54 PM UTC 24
Peak memory 1161368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287005878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3287005878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.2033788613
Short name T7
Test name
Test status
Simulation time 449037788 ps
CPU time 7.74 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:34 PM UTC 24
Peak memory 233440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033788613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.2033788613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.1228086449
Short name T41
Test name
Test status
Simulation time 1150982735 ps
CPU time 25.01 seconds
Started Aug 28 10:21:23 PM UTC 24
Finished Aug 28 10:21:49 PM UTC 24
Peak memory 381088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228086449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1228086449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.2261553403
Short name T168
Test name
Test status
Simulation time 1378280791 ps
CPU time 29.37 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:56 PM UTC 24
Peak memory 243848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261553403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2261553403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.750757504
Short name T6
Test name
Test status
Simulation time 400927144 ps
CPU time 1.76 seconds
Started Aug 28 10:21:28 PM UTC 24
Finished Aug 28 10:21:31 PM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7507575
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.750757504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.4133016676
Short name T9
Test name
Test status
Simulation time 1384728509 ps
CPU time 1.75 seconds
Started Aug 28 10:21:32 PM UTC 24
Finished Aug 28 10:21:35 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133016
676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark
s_acq.4133016676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2531660183
Short name T8
Test name
Test status
Simulation time 293843876 ps
CPU time 1.61 seconds
Started Aug 28 10:21:32 PM UTC 24
Finished Aug 28 10:21:35 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531660
183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_tx.2531660183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.3838992027
Short name T55
Test name
Test status
Simulation time 1955357875 ps
CPU time 12.09 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:39 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838992027 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3838992027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.4006813135
Short name T78
Test name
Test status
Simulation time 479361585 ps
CPU time 3.22 seconds
Started Aug 28 10:21:32 PM UTC 24
Finished Aug 28 10:21:36 PM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006813
135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.4006813135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.2729322068
Short name T167
Test name
Test status
Simulation time 5627181192 ps
CPU time 10.78 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 245932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272932
2068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.2729322068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.2729467878
Short name T321
Test name
Test status
Simulation time 3914608005 ps
CPU time 32.21 seconds
Started Aug 28 10:21:27 PM UTC 24
Finished Aug 28 10:22:01 PM UTC 24
Peak memory 1099992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2729467878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress
_wr.2729467878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.3888649509
Short name T69
Test name
Test status
Simulation time 441764854 ps
CPU time 3.97 seconds
Started Aug 28 10:21:33 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 226636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888649
509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.3888649509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_perf.1427346102
Short name T49
Test name
Test status
Simulation time 712002385 ps
CPU time 4.94 seconds
Started Aug 28 10:21:30 PM UTC 24
Finished Aug 28 10:21:36 PM UTC 24
Peak memory 230956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427346
102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.1427346102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.645124443
Short name T210
Test name
Test status
Simulation time 1945399026 ps
CPU time 3.65 seconds
Started Aug 28 10:21:33 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6451244
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.645124443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.1410265944
Short name T79
Test name
Test status
Simulation time 5597767737 ps
CPU time 44.33 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:22:12 PM UTC 24
Peak memory 231028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410265944 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.1410265944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.3124425806
Short name T290
Test name
Test status
Simulation time 43872794805 ps
CPU time 217.35 seconds
Started Aug 28 10:21:30 PM UTC 24
Finished Aug 28 10:25:10 PM UTC 24
Peak memory 2236836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312442
5806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.3124425806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3049975658
Short name T50
Test name
Test status
Simulation time 843376597 ps
CPU time 8.83 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:36 PM UTC 24
Peak memory 216880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049975658 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.3049975658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.3953080823
Short name T626
Test name
Test status
Simulation time 39346118654 ps
CPU time 393.67 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:28:04 PM UTC 24
Peak memory 4993180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953080823 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.3953080823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.3261837707
Short name T80
Test name
Test status
Simulation time 2558895771 ps
CPU time 9.92 seconds
Started Aug 28 10:21:26 PM UTC 24
Finished Aug 28 10:21:37 PM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261837707 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.3261837707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.522404145
Short name T81
Test name
Test status
Simulation time 1059978715 ps
CPU time 10.11 seconds
Started Aug 28 10:21:28 PM UTC 24
Finished Aug 28 10:21:40 PM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5224041
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.522404145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_alert_test.2357982994
Short name T103
Test name
Test status
Simulation time 23316616 ps
CPU time 0.88 seconds
Started Aug 28 10:21:47 PM UTC 24
Finished Aug 28 10:21:49 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357982994 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2357982994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.3022800989
Short name T17
Test name
Test status
Simulation time 84129740 ps
CPU time 1.33 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:21:41 PM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022800989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3022800989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.67832411
Short name T48
Test name
Test status
Simulation time 210618857 ps
CPU time 5.19 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:21:43 PM UTC 24
Peak memory 258140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67832411 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.67832411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.2870332105
Short name T35
Test name
Test status
Simulation time 3592070698 ps
CPU time 53.42 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:22:32 PM UTC 24
Peak memory 561612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870332105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2870332105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.3092183742
Short name T189
Test name
Test status
Simulation time 2006205356 ps
CPU time 122.88 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:23:42 PM UTC 24
Peak memory 651612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092183742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3092183742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.1253891904
Short name T30
Test name
Test status
Simulation time 902213089 ps
CPU time 1.47 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:21:39 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253891904 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.1253891904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.3444216419
Short name T481
Test name
Test status
Simulation time 4520707748 ps
CPU time 251.08 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:25:52 PM UTC 24
Peak memory 1161656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444216419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3444216419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_override.2856262095
Short name T105
Test name
Test status
Simulation time 51350526 ps
CPU time 1 seconds
Started Aug 28 10:21:36 PM UTC 24
Finished Aug 28 10:21:38 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856262095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2856262095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_perf.2126924735
Short name T27
Test name
Test status
Simulation time 5368658083 ps
CPU time 23.6 seconds
Started Aug 28 10:21:37 PM UTC 24
Finished Aug 28 10:22:02 PM UTC 24
Peak memory 512412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126924735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2126924735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.3343298509
Short name T192
Test name
Test status
Simulation time 264855292 ps
CPU time 4.67 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:21:44 PM UTC 24
Peak memory 226808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343298509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3343298509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.1239538501
Short name T43
Test name
Test status
Simulation time 1569437359 ps
CPU time 76.41 seconds
Started Aug 28 10:21:36 PM UTC 24
Finished Aug 28 10:22:54 PM UTC 24
Peak memory 364820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239538501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1239538501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.1396051505
Short name T174
Test name
Test status
Simulation time 751776328 ps
CPU time 33.05 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:22:13 PM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396051505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1396051505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3859993169
Short name T208
Test name
Test status
Simulation time 147139565 ps
CPU time 1.11 seconds
Started Aug 28 10:21:45 PM UTC 24
Finished Aug 28 10:21:47 PM UTC 24
Peak memory 246856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859993169 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3859993169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.2158340154
Short name T72
Test name
Test status
Simulation time 1032551270 ps
CPU time 7.77 seconds
Started Aug 28 10:21:41 PM UTC 24
Finished Aug 28 10:21:50 PM UTC 24
Peak memory 228876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2158340154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2158340154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.2983913696
Short name T254
Test name
Test status
Simulation time 651982768 ps
CPU time 2.25 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:21:43 PM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983913
696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.2983913696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.488496297
Short name T195
Test name
Test status
Simulation time 210334530 ps
CPU time 2.29 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:21:43 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4884962
97 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.488496297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.3140587871
Short name T293
Test name
Test status
Simulation time 3714603519 ps
CPU time 3.28 seconds
Started Aug 28 10:21:43 PM UTC 24
Finished Aug 28 10:21:48 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140587
871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermark
s_acq.3140587871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.3948113687
Short name T314
Test name
Test status
Simulation time 127586519 ps
CPU time 1.58 seconds
Started Aug 28 10:21:43 PM UTC 24
Finished Aug 28 10:21:46 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948113
687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_tx.3948113687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.3223304112
Short name T158
Test name
Test status
Simulation time 5214327142 ps
CPU time 9.86 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:21:50 PM UTC 24
Peak memory 233620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322330
4112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.3223304112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.1233566477
Short name T460
Test name
Test status
Simulation time 15188538367 ps
CPU time 218.46 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:25:21 PM UTC 24
Peak memory 3518680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1233566477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress
_wr.1233566477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.132506476
Short name T70
Test name
Test status
Simulation time 897250039 ps
CPU time 3.62 seconds
Started Aug 28 10:21:45 PM UTC 24
Finished Aug 28 10:21:49 PM UTC 24
Peak memory 226968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325064
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.132506476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.3558819378
Short name T73
Test name
Test status
Simulation time 426387989 ps
CPU time 4.4 seconds
Started Aug 28 10:21:45 PM UTC 24
Finished Aug 28 10:21:50 PM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558819
378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.3558819378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_perf.2400606500
Short name T281
Test name
Test status
Simulation time 4249849744 ps
CPU time 10.18 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:21:51 PM UTC 24
Peak memory 233696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400606
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.2400606500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.3064685542
Short name T315
Test name
Test status
Simulation time 1002746216 ps
CPU time 3.73 seconds
Started Aug 28 10:21:44 PM UTC 24
Finished Aug 28 10:21:48 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064685
542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.3064685542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1891055912
Short name T95
Test name
Test status
Simulation time 1647088776 ps
CPU time 39.22 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:22:19 PM UTC 24
Peak memory 231116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891055912 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.1891055912
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.2374029904
Short name T316
Test name
Test status
Simulation time 708547198 ps
CPU time 13.81 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:21:53 PM UTC 24
Peak memory 230952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374029904 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.2374029904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.2849050971
Short name T56
Test name
Test status
Simulation time 32539039285 ps
CPU time 23.12 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:22:03 PM UTC 24
Peak memory 512136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849050971 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.2849050971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.3896187277
Short name T317
Test name
Test status
Simulation time 2009837595 ps
CPU time 32.08 seconds
Started Aug 28 10:21:38 PM UTC 24
Finished Aug 28 10:22:12 PM UTC 24
Peak memory 643092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896187277 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.3896187277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.501546530
Short name T82
Test name
Test status
Simulation time 17007820509 ps
CPU time 9.78 seconds
Started Aug 28 10:21:40 PM UTC 24
Finished Aug 28 10:21:50 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5015465
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.501546530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.1794126114
Short name T76
Test name
Test status
Simulation time 264114370 ps
CPU time 5.53 seconds
Started Aug 28 10:21:44 PM UTC 24
Finished Aug 28 10:21:50 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794126
114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1794126114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_alert_test.1858497888
Short name T468
Test name
Test status
Simulation time 44408495 ps
CPU time 0.91 seconds
Started Aug 28 10:25:32 PM UTC 24
Finished Aug 28 10:25:34 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858497888 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1858497888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.3840750037
Short name T456
Test name
Test status
Simulation time 1017028523 ps
CPU time 6.33 seconds
Started Aug 28 10:25:11 PM UTC 24
Finished Aug 28 10:25:19 PM UTC 24
Peak memory 264372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840750037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3840750037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.3656548196
Short name T459
Test name
Test status
Simulation time 391937329 ps
CPU time 11.1 seconds
Started Aug 28 10:25:09 PM UTC 24
Finished Aug 28 10:25:21 PM UTC 24
Peak memory 303184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656548196 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.3656548196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.949681855
Short name T571
Test name
Test status
Simulation time 8846469785 ps
CPU time 116.24 seconds
Started Aug 28 10:25:10 PM UTC 24
Finished Aug 28 10:27:08 PM UTC 24
Peak memory 317180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949681855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.949681855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2855734098
Short name T556
Test name
Test status
Simulation time 3283771390 ps
CPU time 111.88 seconds
Started Aug 28 10:25:08 PM UTC 24
Finished Aug 28 10:27:03 PM UTC 24
Peak memory 616660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855734098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2855734098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.2062551212
Short name T451
Test name
Test status
Simulation time 109201447 ps
CPU time 1.6 seconds
Started Aug 28 10:25:09 PM UTC 24
Finished Aug 28 10:25:11 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062551212 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.2062551212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.1343088764
Short name T457
Test name
Test status
Simulation time 125467086 ps
CPU time 8.13 seconds
Started Aug 28 10:25:10 PM UTC 24
Finished Aug 28 10:25:19 PM UTC 24
Peak memory 216420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343088764 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.1343088764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.2431003925
Short name T118
Test name
Test status
Simulation time 3270138875 ps
CPU time 64.98 seconds
Started Aug 28 10:25:06 PM UTC 24
Finished Aug 28 10:26:13 PM UTC 24
Peak memory 977172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431003925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2431003925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_override.2635347207
Short name T444
Test name
Test status
Simulation time 161977767 ps
CPU time 0.99 seconds
Started Aug 28 10:25:05 PM UTC 24
Finished Aug 28 10:25:07 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635347207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2635347207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_perf.2015292996
Short name T580
Test name
Test status
Simulation time 12525098817 ps
CPU time 155.22 seconds
Started Aug 28 10:25:10 PM UTC 24
Finished Aug 28 10:27:48 PM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015292996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2015292996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.2290123570
Short name T453
Test name
Test status
Simulation time 580343621 ps
CPU time 3.97 seconds
Started Aug 28 10:25:10 PM UTC 24
Finished Aug 28 10:25:15 PM UTC 24
Peak memory 228884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290123570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.2290123570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.2559849298
Short name T467
Test name
Test status
Simulation time 4132014139 ps
CPU time 25.9 seconds
Started Aug 28 10:25:05 PM UTC 24
Finished Aug 28 10:25:32 PM UTC 24
Peak memory 348456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559849298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2559849298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.3210310721
Short name T504
Test name
Test status
Simulation time 1030591102 ps
CPU time 58.13 seconds
Started Aug 28 10:25:10 PM UTC 24
Finished Aug 28 10:26:10 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210310721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3210310721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.2876968571
Short name T417
Test name
Test status
Simulation time 2892156812 ps
CPU time 5.23 seconds
Started Aug 28 10:25:23 PM UTC 24
Finished Aug 28 10:25:29 PM UTC 24
Peak memory 231056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2876968571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.2876968571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.2888578645
Short name T462
Test name
Test status
Simulation time 597011514 ps
CPU time 1.32 seconds
Started Aug 28 10:25:21 PM UTC 24
Finished Aug 28 10:25:23 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888578
645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.2888578645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.3405472333
Short name T463
Test name
Test status
Simulation time 2020222342 ps
CPU time 1.76 seconds
Started Aug 28 10:25:22 PM UTC 24
Finished Aug 28 10:25:24 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405472
333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.3405472333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.3938249835
Short name T470
Test name
Test status
Simulation time 1676666714 ps
CPU time 4.83 seconds
Started Aug 28 10:25:29 PM UTC 24
Finished Aug 28 10:25:35 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938249
835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermar
ks_acq.3938249835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.206885324
Short name T465
Test name
Test status
Simulation time 179560571 ps
CPU time 1.74 seconds
Started Aug 28 10:25:29 PM UTC 24
Finished Aug 28 10:25:32 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068853
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermarks
_tx.206885324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.1747040522
Short name T464
Test name
Test status
Simulation time 1310043104 ps
CPU time 10.33 seconds
Started Aug 28 10:25:16 PM UTC 24
Finished Aug 28 10:25:28 PM UTC 24
Peak memory 226920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174704
0522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.1747040522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.3731139621
Short name T483
Test name
Test status
Simulation time 10720548076 ps
CPU time 34.99 seconds
Started Aug 28 10:25:16 PM UTC 24
Finished Aug 28 10:25:53 PM UTC 24
Peak memory 735512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3731139621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres
s_wr.3731139621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.2075266363
Short name T471
Test name
Test status
Simulation time 559293576 ps
CPU time 4.78 seconds
Started Aug 28 10:25:30 PM UTC 24
Finished Aug 28 10:25:36 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075266
363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.2075266363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.2793798961
Short name T472
Test name
Test status
Simulation time 797625364 ps
CPU time 3.91 seconds
Started Aug 28 10:25:32 PM UTC 24
Finished Aug 28 10:25:37 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793798
961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad
dr.2793798961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.589311462
Short name T182
Test name
Test status
Simulation time 142431482 ps
CPU time 1.87 seconds
Started Aug 28 10:25:32 PM UTC 24
Finished Aug 28 10:25:34 PM UTC 24
Peak memory 232576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5893114
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.589311462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_perf.2169987246
Short name T454
Test name
Test status
Simulation time 521055349 ps
CPU time 6.35 seconds
Started Aug 28 10:25:22 PM UTC 24
Finished Aug 28 10:25:29 PM UTC 24
Peak memory 233300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169987
246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.2169987246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.3585519055
Short name T469
Test name
Test status
Simulation time 1751846312 ps
CPU time 2.48 seconds
Started Aug 28 10:25:30 PM UTC 24
Finished Aug 28 10:25:34 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585519
055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.3585519055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.180512096
Short name T437
Test name
Test status
Simulation time 3833343796 ps
CPU time 15.74 seconds
Started Aug 28 10:25:11 PM UTC 24
Finished Aug 28 10:25:28 PM UTC 24
Peak memory 231032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180512096 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.180512096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.2854820872
Short name T1516
Test name
Test status
Simulation time 49685038744 ps
CPU time 1198.38 seconds
Started Aug 28 10:25:23 PM UTC 24
Finished Aug 28 10:45:34 PM UTC 24
Peak memory 7069852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285482
0872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.2854820872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.63999966
Short name T617
Test name
Test status
Simulation time 27542796363 ps
CPU time 163.16 seconds
Started Aug 28 10:25:12 PM UTC 24
Finished Aug 28 10:27:58 PM UTC 24
Peak memory 2013600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63999966 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.63999966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.1394187627
Short name T533
Test name
Test status
Simulation time 1694847538 ps
CPU time 75.51 seconds
Started Aug 28 10:25:15 PM UTC 24
Finished Aug 28 10:26:33 PM UTC 24
Peak memory 585812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394187627 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.1394187627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.252928166
Short name T466
Test name
Test status
Simulation time 1490510518 ps
CPU time 11.7 seconds
Started Aug 28 10:25:20 PM UTC 24
Finished Aug 28 10:25:32 PM UTC 24
Peak memory 233064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529281
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.252928166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.2212657200
Short name T480
Test name
Test status
Simulation time 836753664 ps
CPU time 17.63 seconds
Started Aug 28 10:25:30 PM UTC 24
Finished Aug 28 10:25:49 PM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212657
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.2212657200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_alert_test.3328486174
Short name T501
Test name
Test status
Simulation time 16549942 ps
CPU time 1.01 seconds
Started Aug 28 10:26:07 PM UTC 24
Finished Aug 28 10:26:09 PM UTC 24
Peak memory 215260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328486174 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3328486174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.2112306919
Short name T479
Test name
Test status
Simulation time 297163715 ps
CPU time 6.88 seconds
Started Aug 28 10:25:39 PM UTC 24
Finished Aug 28 10:25:47 PM UTC 24
Peak memory 264340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112306919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2112306919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.76201022
Short name T477
Test name
Test status
Simulation time 1593457652 ps
CPU time 9.04 seconds
Started Aug 28 10:25:35 PM UTC 24
Finished Aug 28 10:25:45 PM UTC 24
Peak memory 301048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76201022 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.76201022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.2259125735
Short name T577
Test name
Test status
Simulation time 3309324914 ps
CPU time 98.59 seconds
Started Aug 28 10:25:36 PM UTC 24
Finished Aug 28 10:27:17 PM UTC 24
Peak memory 864468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259125735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2259125735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.1562171070
Short name T514
Test name
Test status
Simulation time 5665282290 ps
CPU time 40.91 seconds
Started Aug 28 10:25:35 PM UTC 24
Finished Aug 28 10:26:18 PM UTC 24
Peak memory 420312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562171070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1562171070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.10271729
Short name T473
Test name
Test status
Simulation time 685127636 ps
CPU time 1.66 seconds
Started Aug 28 10:25:35 PM UTC 24
Finished Aug 28 10:25:38 PM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10271729 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.10271729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.3327861473
Short name T476
Test name
Test status
Simulation time 1589397335 ps
CPU time 6.53 seconds
Started Aug 28 10:25:36 PM UTC 24
Finished Aug 28 10:25:44 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327861473 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.3327861473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.1545427025
Short name T574
Test name
Test status
Simulation time 15238536151 ps
CPU time 95.57 seconds
Started Aug 28 10:25:34 PM UTC 24
Finished Aug 28 10:27:11 PM UTC 24
Peak memory 1081568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545427025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1545427025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.3894920505
Short name T497
Test name
Test status
Simulation time 503312881 ps
CPU time 3.69 seconds
Started Aug 28 10:26:02 PM UTC 24
Finished Aug 28 10:26:06 PM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894920505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3894920505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_perf.2583861067
Short name T927
Test name
Test status
Simulation time 27904517762 ps
CPU time 488.3 seconds
Started Aug 28 10:25:37 PM UTC 24
Finished Aug 28 10:33:52 PM UTC 24
Peak memory 254284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583861067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2583861067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.2998522818
Short name T475
Test name
Test status
Simulation time 99153173 ps
CPU time 1.39 seconds
Started Aug 28 10:25:37 PM UTC 24
Finished Aug 28 10:25:40 PM UTC 24
Peak memory 234552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998522818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.2998522818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.10119699
Short name T552
Test name
Test status
Simulation time 2114402225 ps
CPU time 84.65 seconds
Started Aug 28 10:25:33 PM UTC 24
Finished Aug 28 10:26:59 PM UTC 24
Peak memory 342092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10119699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.10119699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.4027079266
Short name T511
Test name
Test status
Simulation time 775542933 ps
CPU time 35.68 seconds
Started Aug 28 10:25:38 PM UTC 24
Finished Aug 28 10:26:15 PM UTC 24
Peak memory 226676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027079266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4027079266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.3476826051
Short name T493
Test name
Test status
Simulation time 1489094800 ps
CPU time 6.7 seconds
Started Aug 28 10:25:56 PM UTC 24
Finished Aug 28 10:26:04 PM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3476826051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_ad
dr.3476826051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.4274959524
Short name T485
Test name
Test status
Simulation time 169044737 ps
CPU time 1.82 seconds
Started Aug 28 10:25:52 PM UTC 24
Finished Aug 28 10:25:55 PM UTC 24
Peak memory 214308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274959
524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.4274959524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.2081936540
Short name T486
Test name
Test status
Simulation time 346496764 ps
CPU time 1.82 seconds
Started Aug 28 10:25:53 PM UTC 24
Finished Aug 28 10:25:56 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081936
540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.2081936540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.1043737575
Short name T500
Test name
Test status
Simulation time 1505031836 ps
CPU time 3.56 seconds
Started Aug 28 10:26:04 PM UTC 24
Finished Aug 28 10:26:08 PM UTC 24
Peak memory 215564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043737
575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.1043737575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.671764732
Short name T498
Test name
Test status
Simulation time 282583707 ps
CPU time 2.07 seconds
Started Aug 28 10:26:04 PM UTC 24
Finished Aug 28 10:26:07 PM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6717647
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermarks
_tx.671764732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_hrst.4067758075
Short name T492
Test name
Test status
Simulation time 1528033310 ps
CPU time 2.87 seconds
Started Aug 28 10:25:59 PM UTC 24
Finished Aug 28 10:26:03 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067758
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.4067758075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.2865380895
Short name T490
Test name
Test status
Simulation time 1831280381 ps
CPU time 14.69 seconds
Started Aug 28 10:25:47 PM UTC 24
Finished Aug 28 10:26:03 PM UTC 24
Peak memory 227116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286538
0895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.2865380895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.661887925
Short name T605
Test name
Test status
Simulation time 19501862965 ps
CPU time 113.25 seconds
Started Aug 28 10:25:48 PM UTC 24
Finished Aug 28 10:27:43 PM UTC 24
Peak memory 1763480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=661887925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stress
_wr.661887925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.575764068
Short name T506
Test name
Test status
Simulation time 2153191775 ps
CPU time 4.68 seconds
Started Aug 28 10:26:05 PM UTC 24
Finished Aug 28 10:26:11 PM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5757640
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.575764068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.3035653359
Short name T507
Test name
Test status
Simulation time 1860223211 ps
CPU time 4.27 seconds
Started Aug 28 10:26:06 PM UTC 24
Finished Aug 28 10:26:11 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035653
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.3035653359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_perf.2259048645
Short name T496
Test name
Test status
Simulation time 849090204 ps
CPU time 9.3 seconds
Started Aug 28 10:25:55 PM UTC 24
Finished Aug 28 10:26:06 PM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259048
645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.2259048645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.1828088838
Short name T505
Test name
Test status
Simulation time 661593844 ps
CPU time 4.51 seconds
Started Aug 28 10:26:05 PM UTC 24
Finished Aug 28 10:26:10 PM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828088
838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.1828088838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.2775327552
Short name T515
Test name
Test status
Simulation time 4720759206 ps
CPU time 36.37 seconds
Started Aug 28 10:25:41 PM UTC 24
Finished Aug 28 10:26:18 PM UTC 24
Peak memory 226980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775327552 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.2775327552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.3230857146
Short name T767
Test name
Test status
Simulation time 31613721801 ps
CPU time 273.85 seconds
Started Aug 28 10:25:55 PM UTC 24
Finished Aug 28 10:30:33 PM UTC 24
Peak memory 2695328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323085
7146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.3230857146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.291818503
Short name T487
Test name
Test status
Simulation time 252069911 ps
CPU time 11.83 seconds
Started Aug 28 10:25:46 PM UTC 24
Finished Aug 28 10:25:59 PM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291818503 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.291818503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.3445433847
Short name T524
Test name
Test status
Simulation time 45881418727 ps
CPU time 41.45 seconds
Started Aug 28 10:25:45 PM UTC 24
Finished Aug 28 10:26:28 PM UTC 24
Peak memory 784780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445433847 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.3445433847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.600394183
Short name T489
Test name
Test status
Simulation time 1240114403 ps
CPU time 13.3 seconds
Started Aug 28 10:25:47 PM UTC 24
Finished Aug 28 10:26:01 PM UTC 24
Peak memory 321544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600394183 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.600394183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.2367694632
Short name T495
Test name
Test status
Simulation time 2755061426 ps
CPU time 13.67 seconds
Started Aug 28 10:25:50 PM UTC 24
Finished Aug 28 10:26:05 PM UTC 24
Peak memory 227188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367694
632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.2367694632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.2722438588
Short name T499
Test name
Test status
Simulation time 80103302 ps
CPU time 2.72 seconds
Started Aug 28 10:26:04 PM UTC 24
Finished Aug 28 10:26:08 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722438
588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.2722438588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_alert_test.2193588506
Short name T502
Test name
Test status
Simulation time 22984968 ps
CPU time 1 seconds
Started Aug 28 10:26:31 PM UTC 24
Finished Aug 28 10:26:33 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193588506 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2193588506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.504585881
Short name T38
Test name
Test status
Simulation time 915333131 ps
CPU time 11.7 seconds
Started Aug 28 10:26:13 PM UTC 24
Finished Aug 28 10:26:26 PM UTC 24
Peak memory 243488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504585881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.504585881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.231373971
Short name T518
Test name
Test status
Simulation time 340425762 ps
CPU time 8.77 seconds
Started Aug 28 10:26:11 PM UTC 24
Finished Aug 28 10:26:21 PM UTC 24
Peak memory 280640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231373971 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.231373971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.2919389619
Short name T623
Test name
Test status
Simulation time 2294610241 ps
CPU time 107.7 seconds
Started Aug 28 10:26:12 PM UTC 24
Finished Aug 28 10:28:02 PM UTC 24
Peak memory 362828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919389619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2919389619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.4158414039
Short name T666
Test name
Test status
Simulation time 2883542094 ps
CPU time 146.87 seconds
Started Aug 28 10:26:10 PM UTC 24
Finished Aug 28 10:28:41 PM UTC 24
Peak memory 721068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158414039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4158414039
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.3901986576
Short name T510
Test name
Test status
Simulation time 145877422 ps
CPU time 1.71 seconds
Started Aug 28 10:26:10 PM UTC 24
Finished Aug 28 10:26:14 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901986576 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.3901986576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.2559246743
Short name T516
Test name
Test status
Simulation time 165198337 ps
CPU time 6.66 seconds
Started Aug 28 10:26:11 PM UTC 24
Finished Aug 28 10:26:19 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559246743 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.2559246743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.3209959685
Short name T603
Test name
Test status
Simulation time 13115577583 ps
CPU time 91.24 seconds
Started Aug 28 10:26:09 PM UTC 24
Finished Aug 28 10:27:43 PM UTC 24
Peak memory 997620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209959685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3209959685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.2767894348
Short name T542
Test name
Test status
Simulation time 384104811 ps
CPU time 17.7 seconds
Started Aug 28 10:26:25 PM UTC 24
Finished Aug 28 10:26:44 PM UTC 24
Peak memory 216612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767894348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2767894348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_perf.3080810414
Short name T639
Test name
Test status
Simulation time 2728422138 ps
CPU time 127.16 seconds
Started Aug 28 10:26:12 PM UTC 24
Finished Aug 28 10:28:21 PM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080810414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3080810414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.853990286
Short name T736
Test name
Test status
Simulation time 24266552127 ps
CPU time 325.85 seconds
Started Aug 28 10:26:12 PM UTC 24
Finished Aug 28 10:31:42 PM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853990286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.853990286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.4167370386
Short name T531
Test name
Test status
Simulation time 5214351023 ps
CPU time 23.44 seconds
Started Aug 28 10:26:07 PM UTC 24
Finished Aug 28 10:26:32 PM UTC 24
Peak memory 333792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167370386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4167370386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.164306374
Short name T519
Test name
Test status
Simulation time 2524131372 ps
CPU time 9.63 seconds
Started Aug 28 10:26:12 PM UTC 24
Finished Aug 28 10:26:23 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164306374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.164306374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.1584787047
Short name T527
Test name
Test status
Simulation time 4722214656 ps
CPU time 4.91 seconds
Started Aug 28 10:26:24 PM UTC 24
Finished Aug 28 10:26:30 PM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1584787047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.1584787047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.3040570827
Short name T522
Test name
Test status
Simulation time 217925617 ps
CPU time 1.84 seconds
Started Aug 28 10:26:22 PM UTC 24
Finished Aug 28 10:26:24 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040570
827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.3040570827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.1504244163
Short name T523
Test name
Test status
Simulation time 736457656 ps
CPU time 2.34 seconds
Started Aug 28 10:26:22 PM UTC 24
Finished Aug 28 10:26:25 PM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504244
163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.1504244163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.870852052
Short name T532
Test name
Test status
Simulation time 583331613 ps
CPU time 4.7 seconds
Started Aug 28 10:26:26 PM UTC 24
Finished Aug 28 10:26:32 PM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8708520
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_acq.870852052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.1424473038
Short name T529
Test name
Test status
Simulation time 428347217 ps
CPU time 1.66 seconds
Started Aug 28 10:26:27 PM UTC 24
Finished Aug 28 10:26:30 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424473
038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_tx.1424473038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.28880352
Short name T525
Test name
Test status
Simulation time 1000518777 ps
CPU time 3.16 seconds
Started Aug 28 10:26:24 PM UTC 24
Finished Aug 28 10:26:28 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888035
2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.28880352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.1986180385
Short name T526
Test name
Test status
Simulation time 4857739464 ps
CPU time 10.07 seconds
Started Aug 28 10:26:17 PM UTC 24
Finished Aug 28 10:26:28 PM UTC 24
Peak memory 233628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198618
0385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.1986180385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.4070525925
Short name T521
Test name
Test status
Simulation time 1512609113 ps
CPU time 4.19 seconds
Started Aug 28 10:26:18 PM UTC 24
Finished Aug 28 10:26:24 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4070525925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.4070525925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.1011148051
Short name T538
Test name
Test status
Simulation time 604924335 ps
CPU time 5.63 seconds
Started Aug 28 10:26:29 PM UTC 24
Finished Aug 28 10:26:36 PM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011148
051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.1011148051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.3246811131
Short name T53
Test name
Test status
Simulation time 3642457788 ps
CPU time 5.23 seconds
Started Aug 28 10:26:30 PM UTC 24
Finished Aug 28 10:26:37 PM UTC 24
Peak memory 216724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246811
131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad
dr.3246811131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_nack_txstretch.1837678346
Short name T536
Test name
Test status
Simulation time 164381752 ps
CPU time 2.51 seconds
Started Aug 28 10:26:31 PM UTC 24
Finished Aug 28 10:26:34 PM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837678
346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_txstretch.1837678346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_perf.3037994044
Short name T530
Test name
Test status
Simulation time 1066722823 ps
CPU time 6.47 seconds
Started Aug 28 10:26:23 PM UTC 24
Finished Aug 28 10:26:30 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037994
044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.3037994044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.4010965681
Short name T537
Test name
Test status
Simulation time 4543942547 ps
CPU time 3.92 seconds
Started Aug 28 10:26:29 PM UTC 24
Finished Aug 28 10:26:34 PM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010965
681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.4010965681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.2167206742
Short name T534
Test name
Test status
Simulation time 1874549972 ps
CPU time 17.2 seconds
Started Aug 28 10:26:14 PM UTC 24
Finished Aug 28 10:26:33 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167206742 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.2167206742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.2204958956
Short name T543
Test name
Test status
Simulation time 10433061958 ps
CPU time 30.35 seconds
Started Aug 28 10:26:16 PM UTC 24
Finished Aug 28 10:26:48 PM UTC 24
Peak memory 244184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204958956 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.2204958956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.830308533
Short name T1683
Test name
Test status
Simulation time 60429692292 ps
CPU time 1324.45 seconds
Started Aug 28 10:26:15 PM UTC 24
Finished Aug 28 10:48:33 PM UTC 24
Peak memory 10567896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830308533 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.830308533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3970149927
Short name T528
Test name
Test status
Simulation time 3176601841 ps
CPU time 9.19 seconds
Started Aug 28 10:26:19 PM UTC 24
Finished Aug 28 10:26:30 PM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970149
927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.3970149927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.3050605070
Short name T540
Test name
Test status
Simulation time 514669879 ps
CPU time 8.04 seconds
Started Aug 28 10:26:28 PM UTC 24
Finished Aug 28 10:26:38 PM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050605
070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3050605070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_alert_test.3509631744
Short name T565
Test name
Test status
Simulation time 18829109 ps
CPU time 0.91 seconds
Started Aug 28 10:27:04 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509631744 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3509631744
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.1559070351
Short name T520
Test name
Test status
Simulation time 174010833 ps
CPU time 2.14 seconds
Started Aug 28 10:26:37 PM UTC 24
Finished Aug 28 10:26:40 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559070351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.1559070351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.2169151382
Short name T549
Test name
Test status
Simulation time 967810751 ps
CPU time 21.99 seconds
Started Aug 28 10:26:34 PM UTC 24
Finished Aug 28 10:26:57 PM UTC 24
Peak memory 290880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169151382 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.2169151382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.1848892889
Short name T632
Test name
Test status
Simulation time 4536202916 ps
CPU time 95.35 seconds
Started Aug 28 10:26:35 PM UTC 24
Finished Aug 28 10:28:13 PM UTC 24
Peak memory 598216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848892889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1848892889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.4278788587
Short name T630
Test name
Test status
Simulation time 33250645265 ps
CPU time 95.65 seconds
Started Aug 28 10:26:33 PM UTC 24
Finished Aug 28 10:28:11 PM UTC 24
Peak memory 639236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278788587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.4278788587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.2069429408
Short name T539
Test name
Test status
Simulation time 163470424 ps
CPU time 1.46 seconds
Started Aug 28 10:26:34 PM UTC 24
Finished Aug 28 10:26:37 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069429408 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.2069429408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.2185770395
Short name T541
Test name
Test status
Simulation time 676734855 ps
CPU time 8.11 seconds
Started Aug 28 10:26:34 PM UTC 24
Finished Aug 28 10:26:43 PM UTC 24
Peak memory 258380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185770395 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.2185770395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.820600709
Short name T120
Test name
Test status
Simulation time 5673086013 ps
CPU time 148.94 seconds
Started Aug 28 10:26:33 PM UTC 24
Finished Aug 28 10:29:05 PM UTC 24
Peak memory 1681752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820600709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.820600709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.153781652
Short name T274
Test name
Test status
Simulation time 1060764448 ps
CPU time 5.03 seconds
Started Aug 28 10:27:00 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153781652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.153781652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_override.488673774
Short name T535
Test name
Test status
Simulation time 87689579 ps
CPU time 0.96 seconds
Started Aug 28 10:26:32 PM UTC 24
Finished Aug 28 10:26:34 PM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488673774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.488673774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_perf.867877757
Short name T551
Test name
Test status
Simulation time 5574024177 ps
CPU time 21.95 seconds
Started Aug 28 10:26:35 PM UTC 24
Finished Aug 28 10:26:58 PM UTC 24
Peak memory 242120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867877757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.867877757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.888877021
Short name T484
Test name
Test status
Simulation time 88658741 ps
CPU time 3 seconds
Started Aug 28 10:26:35 PM UTC 24
Finished Aug 28 10:26:39 PM UTC 24
Peak memory 226636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888877021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.888877021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3040212544
Short name T564
Test name
Test status
Simulation time 1839418336 ps
CPU time 33.68 seconds
Started Aug 28 10:26:31 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 377040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040212544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3040212544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.3034703873
Short name T554
Test name
Test status
Simulation time 1075824483 ps
CPU time 21.63 seconds
Started Aug 28 10:26:37 PM UTC 24
Finished Aug 28 10:27:00 PM UTC 24
Peak memory 233600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034703873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3034703873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.1274433093
Short name T559
Test name
Test status
Simulation time 2484987418 ps
CPU time 6.34 seconds
Started Aug 28 10:26:56 PM UTC 24
Finished Aug 28 10:27:04 PM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1274433093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_ad
dr.1274433093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.1032021481
Short name T546
Test name
Test status
Simulation time 670625981 ps
CPU time 1.91 seconds
Started Aug 28 10:26:51 PM UTC 24
Finished Aug 28 10:26:54 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032021
481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.1032021481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.567160979
Short name T548
Test name
Test status
Simulation time 264612483 ps
CPU time 1.85 seconds
Started Aug 28 10:26:53 PM UTC 24
Finished Aug 28 10:26:56 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5671609
79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.567160979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.4260945057
Short name T563
Test name
Test status
Simulation time 473168763 ps
CPU time 5.07 seconds
Started Aug 28 10:27:00 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260945
057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermar
ks_acq.4260945057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.745473155
Short name T557
Test name
Test status
Simulation time 291422030 ps
CPU time 1.78 seconds
Started Aug 28 10:27:01 PM UTC 24
Finished Aug 28 10:27:04 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7454731
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermarks
_tx.745473155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.2586061714
Short name T553
Test name
Test status
Simulation time 311434896 ps
CPU time 2.23 seconds
Started Aug 28 10:26:56 PM UTC 24
Finished Aug 28 10:27:00 PM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586061
714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.2586061714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.3864519136
Short name T544
Test name
Test status
Simulation time 7327145164 ps
CPU time 7.06 seconds
Started Aug 28 10:26:42 PM UTC 24
Finished Aug 28 10:26:50 PM UTC 24
Peak memory 229192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386451
9136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.3864519136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.991618751
Short name T638
Test name
Test status
Simulation time 13434839000 ps
CPU time 95.37 seconds
Started Aug 28 10:26:44 PM UTC 24
Finished Aug 28 10:28:21 PM UTC 24
Peak memory 1738840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=991618751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stress
_wr.991618751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.2888183021
Short name T570
Test name
Test status
Simulation time 2220118043 ps
CPU time 5.18 seconds
Started Aug 28 10:27:01 PM UTC 24
Finished Aug 28 10:27:07 PM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888183
021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.2888183021
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.3690630318
Short name T566
Test name
Test status
Simulation time 1572291380 ps
CPU time 3.27 seconds
Started Aug 28 10:27:02 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690630
318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.3690630318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.3450588760
Short name T568
Test name
Test status
Simulation time 493521812 ps
CPU time 2.42 seconds
Started Aug 28 10:27:03 PM UTC 24
Finished Aug 28 10:27:07 PM UTC 24
Peak memory 233424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450588
760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.3450588760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_perf.2180109074
Short name T560
Test name
Test status
Simulation time 14237629589 ps
CPU time 9.1 seconds
Started Aug 28 10:26:54 PM UTC 24
Finished Aug 28 10:27:04 PM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180109
074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.2180109074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.4251438942
Short name T561
Test name
Test status
Simulation time 1830243827 ps
CPU time 3.28 seconds
Started Aug 28 10:27:01 PM UTC 24
Finished Aug 28 10:27:05 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251438
942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.4251438942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.1574922960
Short name T558
Test name
Test status
Simulation time 674795291 ps
CPU time 24.82 seconds
Started Aug 28 10:26:37 PM UTC 24
Finished Aug 28 10:27:04 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574922960 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.1574922960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.2693642389
Short name T599
Test name
Test status
Simulation time 20481621964 ps
CPU time 40.33 seconds
Started Aug 28 10:26:55 PM UTC 24
Finished Aug 28 10:27:37 PM UTC 24
Peak memory 283056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269364
2389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.2693642389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.2148405639
Short name T562
Test name
Test status
Simulation time 4441461170 ps
CPU time 24.32 seconds
Started Aug 28 10:26:40 PM UTC 24
Finished Aug 28 10:27:05 PM UTC 24
Peak memory 233212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148405639 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.2148405639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.781514131
Short name T555
Test name
Test status
Simulation time 8268657239 ps
CPU time 20.47 seconds
Started Aug 28 10:26:39 PM UTC 24
Finished Aug 28 10:27:00 PM UTC 24
Peak memory 217012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781514131 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.781514131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.4236001621
Short name T608
Test name
Test status
Simulation time 2828316114 ps
CPU time 65.03 seconds
Started Aug 28 10:26:41 PM UTC 24
Finished Aug 28 10:27:47 PM UTC 24
Peak memory 520468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236001621 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.4236001621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.3805609725
Short name T545
Test name
Test status
Simulation time 1193022868 ps
CPU time 7.81 seconds
Started Aug 28 10:26:45 PM UTC 24
Finished Aug 28 10:26:54 PM UTC 24
Peak memory 226920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805609
725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.3805609725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.940375957
Short name T569
Test name
Test status
Simulation time 202444748 ps
CPU time 4.99 seconds
Started Aug 28 10:27:01 PM UTC 24
Finished Aug 28 10:27:07 PM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9403759
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.940375957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_alert_test.1988938300
Short name T601
Test name
Test status
Simulation time 78035449 ps
CPU time 0.9 seconds
Started Aug 28 10:27:39 PM UTC 24
Finished Aug 28 10:27:41 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988938300 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1988938300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1277367109
Short name T39
Test name
Test status
Simulation time 504871082 ps
CPU time 3.45 seconds
Started Aug 28 10:27:08 PM UTC 24
Finished Aug 28 10:27:12 PM UTC 24
Peak memory 233220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277367109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1277367109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.2273940285
Short name T587
Test name
Test status
Simulation time 391596890 ps
CPU time 20.49 seconds
Started Aug 28 10:27:07 PM UTC 24
Finished Aug 28 10:27:28 PM UTC 24
Peak memory 303132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273940285 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.2273940285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.2059291683
Short name T629
Test name
Test status
Simulation time 3836927371 ps
CPU time 62.25 seconds
Started Aug 28 10:27:07 PM UTC 24
Finished Aug 28 10:28:11 PM UTC 24
Peak memory 571600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059291683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2059291683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.3882738857
Short name T144
Test name
Test status
Simulation time 1931960954 ps
CPU time 59.13 seconds
Started Aug 28 10:27:06 PM UTC 24
Finished Aug 28 10:28:07 PM UTC 24
Peak memory 686232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882738857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3882738857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.565419505
Short name T572
Test name
Test status
Simulation time 149036873 ps
CPU time 1.42 seconds
Started Aug 28 10:27:06 PM UTC 24
Finished Aug 28 10:27:09 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565419505 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.565419505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.1112805716
Short name T578
Test name
Test status
Simulation time 125711209 ps
CPU time 9.89 seconds
Started Aug 28 10:27:07 PM UTC 24
Finished Aug 28 10:27:18 PM UTC 24
Peak memory 237704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112805716 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.1112805716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.2873209372
Short name T770
Test name
Test status
Simulation time 8184018905 ps
CPU time 207.48 seconds
Started Aug 28 10:27:05 PM UTC 24
Finished Aug 28 10:30:36 PM UTC 24
Peak memory 1091840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873209372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2873209372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.431135167
Short name T264
Test name
Test status
Simulation time 1654623578 ps
CPU time 7.62 seconds
Started Aug 28 10:27:24 PM UTC 24
Finished Aug 28 10:27:33 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431135167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.431135167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_override.1832153143
Short name T567
Test name
Test status
Simulation time 86128332 ps
CPU time 1 seconds
Started Aug 28 10:27:04 PM UTC 24
Finished Aug 28 10:27:06 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832153143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1832153143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_perf.2767281571
Short name T594
Test name
Test status
Simulation time 2235388070 ps
CPU time 24.35 seconds
Started Aug 28 10:27:07 PM UTC 24
Finished Aug 28 10:27:32 PM UTC 24
Peak memory 299220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767281571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2767281571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.1042131160
Short name T573
Test name
Test status
Simulation time 99501465 ps
CPU time 1.7 seconds
Started Aug 28 10:27:08 PM UTC 24
Finished Aug 28 10:27:11 PM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042131160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1042131160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.675645454
Short name T610
Test name
Test status
Simulation time 928551493 ps
CPU time 45.58 seconds
Started Aug 28 10:27:04 PM UTC 24
Finished Aug 28 10:27:51 PM UTC 24
Peak memory 297060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675645454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.675645454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_stress_all.1226727234
Short name T880
Test name
Test status
Simulation time 62992549889 ps
CPU time 345.22 seconds
Started Aug 28 10:27:08 PM UTC 24
Finished Aug 28 10:32:58 PM UTC 24
Peak memory 1708440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226727234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1226727234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.1970417760
Short name T575
Test name
Test status
Simulation time 1073010228 ps
CPU time 7.36 seconds
Started Aug 28 10:27:08 PM UTC 24
Finished Aug 28 10:27:16 PM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970417760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1970417760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.1371483057
Short name T590
Test name
Test status
Simulation time 4192160058 ps
CPU time 6.62 seconds
Started Aug 28 10:27:22 PM UTC 24
Finished Aug 28 10:27:30 PM UTC 24
Peak memory 233392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1371483057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad
dr.1371483057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.2179346019
Short name T579
Test name
Test status
Simulation time 242639937 ps
CPU time 1.1 seconds
Started Aug 28 10:27:18 PM UTC 24
Finished Aug 28 10:27:20 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179346
019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.2179346019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.1732268766
Short name T582
Test name
Test status
Simulation time 360365597 ps
CPU time 2.3 seconds
Started Aug 28 10:27:19 PM UTC 24
Finished Aug 28 10:27:22 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732268
766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.1732268766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.4257877132
Short name T591
Test name
Test status
Simulation time 1798976958 ps
CPU time 4.02 seconds
Started Aug 28 10:27:25 PM UTC 24
Finished Aug 28 10:27:30 PM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257877
132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.4257877132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.357044323
Short name T589
Test name
Test status
Simulation time 516918971 ps
CPU time 2.25 seconds
Started Aug 28 10:27:26 PM UTC 24
Finished Aug 28 10:27:29 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570443
23 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks
_tx.357044323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.1124814689
Short name T583
Test name
Test status
Simulation time 1092839274 ps
CPU time 9.98 seconds
Started Aug 28 10:27:12 PM UTC 24
Finished Aug 28 10:27:23 PM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112481
4689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.1124814689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.2221149213
Short name T581
Test name
Test status
Simulation time 2660279155 ps
CPU time 5.91 seconds
Started Aug 28 10:27:13 PM UTC 24
Finished Aug 28 10:27:20 PM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2221149213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.2221149213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.282182029
Short name T598
Test name
Test status
Simulation time 2189902669 ps
CPU time 4.84 seconds
Started Aug 28 10:27:29 PM UTC 24
Finished Aug 28 10:27:35 PM UTC 24
Peak memory 226696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821820
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.282182029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.1861113125
Short name T54
Test name
Test status
Simulation time 876111326 ps
CPU time 4 seconds
Started Aug 28 10:27:31 PM UTC 24
Finished Aug 28 10:27:36 PM UTC 24
Peak memory 216400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861113
125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_ad
dr.1861113125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.3236624772
Short name T596
Test name
Test status
Simulation time 138033845 ps
CPU time 2.19 seconds
Started Aug 28 10:27:31 PM UTC 24
Finished Aug 28 10:27:34 PM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236624
772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.3236624772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_perf.515691043
Short name T592
Test name
Test status
Simulation time 10017863123 ps
CPU time 8.84 seconds
Started Aug 28 10:27:21 PM UTC 24
Finished Aug 28 10:27:31 PM UTC 24
Peak memory 229048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5156910
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.515691043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.1395291388
Short name T597
Test name
Test status
Simulation time 376345623 ps
CPU time 3.46 seconds
Started Aug 28 10:27:29 PM UTC 24
Finished Aug 28 10:27:34 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395291
388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.1395291388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.2825358739
Short name T595
Test name
Test status
Simulation time 4058650557 ps
CPU time 23.24 seconds
Started Aug 28 10:27:08 PM UTC 24
Finished Aug 28 10:27:33 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825358739 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.2825358739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.3049366639
Short name T622
Test name
Test status
Simulation time 79342940323 ps
CPU time 38.39 seconds
Started Aug 28 10:27:21 PM UTC 24
Finished Aug 28 10:28:01 PM UTC 24
Peak memory 282928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304936
6639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.3049366639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.1347277170
Short name T606
Test name
Test status
Simulation time 3844761223 ps
CPU time 33.03 seconds
Started Aug 28 10:27:10 PM UTC 24
Finished Aug 28 10:27:45 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347277170 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.1347277170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.1467132702
Short name T585
Test name
Test status
Simulation time 9083280295 ps
CPU time 13.52 seconds
Started Aug 28 10:27:09 PM UTC 24
Finished Aug 28 10:27:24 PM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467132702 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.1467132702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.3193397457
Short name T576
Test name
Test status
Simulation time 2663608485 ps
CPU time 4.37 seconds
Started Aug 28 10:27:11 PM UTC 24
Finished Aug 28 10:27:17 PM UTC 24
Peak memory 260244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193397457 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.3193397457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.3478545342
Short name T588
Test name
Test status
Simulation time 2916213388 ps
CPU time 9.84 seconds
Started Aug 28 10:27:18 PM UTC 24
Finished Aug 28 10:27:28 PM UTC 24
Peak memory 244180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478545
342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.3478545342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.1953380745
Short name T593
Test name
Test status
Simulation time 74272438 ps
CPU time 3.11 seconds
Started Aug 28 10:27:27 PM UTC 24
Finished Aug 28 10:27:31 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953380
745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1953380745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_alert_test.1380924467
Short name T627
Test name
Test status
Simulation time 51671883 ps
CPU time 0.96 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:04 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380924467 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1380924467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.3348776640
Short name T607
Test name
Test status
Simulation time 802675051 ps
CPU time 2.86 seconds
Started Aug 28 10:27:42 PM UTC 24
Finished Aug 28 10:27:46 PM UTC 24
Peak memory 229144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348776640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3348776640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.3368914688
Short name T615
Test name
Test status
Simulation time 1004893401 ps
CPU time 15.19 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:27:57 PM UTC 24
Peak memory 258332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368914688 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.3368914688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.3051159495
Short name T688
Test name
Test status
Simulation time 2979532474 ps
CPU time 81.13 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:29:04 PM UTC 24
Peak memory 602388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051159495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3051159495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.3350310699
Short name T737
Test name
Test status
Simulation time 10822056278 ps
CPU time 134.14 seconds
Started Aug 28 10:27:40 PM UTC 24
Finished Aug 28 10:29:57 PM UTC 24
Peak memory 741264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350310699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3350310699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.2319446344
Short name T258
Test name
Test status
Simulation time 263363904 ps
CPU time 1.57 seconds
Started Aug 28 10:27:40 PM UTC 24
Finished Aug 28 10:27:43 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319446344 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.2319446344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.1494937866
Short name T619
Test name
Test status
Simulation time 912766932 ps
CPU time 17.06 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:27:59 PM UTC 24
Peak memory 264264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494937866 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.1494937866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.4015707613
Short name T121
Test name
Test status
Simulation time 9458543069 ps
CPU time 98.71 seconds
Started Aug 28 10:27:40 PM UTC 24
Finished Aug 28 10:29:21 PM UTC 24
Peak memory 1308712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015707613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.4015707613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.1600713333
Short name T275
Test name
Test status
Simulation time 7695091255 ps
CPU time 26.68 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:30 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600713333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1600713333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_mode_toggle.2102944013
Short name T616
Test name
Test status
Simulation time 293154787 ps
CPU time 1.63 seconds
Started Aug 28 10:27:54 PM UTC 24
Finished Aug 28 10:27:57 PM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102944013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2102944013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_override.1699817464
Short name T602
Test name
Test status
Simulation time 46917203 ps
CPU time 1.04 seconds
Started Aug 28 10:27:39 PM UTC 24
Finished Aug 28 10:27:41 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699817464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1699817464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_perf.275770765
Short name T690
Test name
Test status
Simulation time 5301665975 ps
CPU time 85.66 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:29:08 PM UTC 24
Peak memory 711064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275770765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.275770765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.751427819
Short name T604
Test name
Test status
Simulation time 121462338 ps
CPU time 1.28 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:27:43 PM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751427819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.751427819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.3425352313
Short name T655
Test name
Test status
Simulation time 2675682046 ps
CPU time 49.46 seconds
Started Aug 28 10:27:39 PM UTC 24
Finished Aug 28 10:28:30 PM UTC 24
Peak memory 481552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425352313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3425352313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.1801803834
Short name T621
Test name
Test status
Simulation time 936059970 ps
CPU time 18.37 seconds
Started Aug 28 10:27:41 PM UTC 24
Finished Aug 28 10:28:01 PM UTC 24
Peak memory 228788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801803834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1801803834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.1407886286
Short name T624
Test name
Test status
Simulation time 3610728092 ps
CPU time 7.66 seconds
Started Aug 28 10:27:53 PM UTC 24
Finished Aug 28 10:28:02 PM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1407886286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.1407886286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.1426394741
Short name T611
Test name
Test status
Simulation time 211015753 ps
CPU time 2.47 seconds
Started Aug 28 10:27:49 PM UTC 24
Finished Aug 28 10:27:52 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426394
741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.1426394741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.3235956177
Short name T612
Test name
Test status
Simulation time 181276787 ps
CPU time 1.2 seconds
Started Aug 28 10:27:51 PM UTC 24
Finished Aug 28 10:27:53 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235956
177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.3235956177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2821174528
Short name T143
Test name
Test status
Simulation time 542748254 ps
CPU time 3.57 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:07 PM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821174
528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar
ks_acq.2821174528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.2810179146
Short name T628
Test name
Test status
Simulation time 526085304 ps
CPU time 1.99 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:05 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810179
146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_tx.2810179146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.1565022563
Short name T613
Test name
Test status
Simulation time 3954270389 ps
CPU time 9.6 seconds
Started Aug 28 10:27:44 PM UTC 24
Finished Aug 28 10:27:55 PM UTC 24
Peak memory 233940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156502
2563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.1565022563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.2271288885
Short name T609
Test name
Test status
Simulation time 447785708 ps
CPU time 3.44 seconds
Started Aug 28 10:27:45 PM UTC 24
Finished Aug 28 10:27:50 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2271288885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stres
s_wr.2271288885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.3198931938
Short name T147
Test name
Test status
Simulation time 612840172 ps
CPU time 3.98 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:07 PM UTC 24
Peak memory 226180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198931
938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.3198931938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.35928362
Short name T148
Test name
Test status
Simulation time 1044418111 ps
CPU time 4.18 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:08 PM UTC 24
Peak memory 216724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592836
2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_addr.35928362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_perf.1255170856
Short name T620
Test name
Test status
Simulation time 748616491 ps
CPU time 6.81 seconds
Started Aug 28 10:27:52 PM UTC 24
Finished Aug 28 10:28:00 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255170
856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.1255170856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.1923571604
Short name T142
Test name
Test status
Simulation time 1093540533 ps
CPU time 2.98 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:06 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923571
604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.1923571604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.2264266911
Short name T618
Test name
Test status
Simulation time 2782635306 ps
CPU time 15.5 seconds
Started Aug 28 10:27:42 PM UTC 24
Finished Aug 28 10:27:59 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264266911 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.2264266911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.3351932804
Short name T793
Test name
Test status
Simulation time 19985464782 ps
CPU time 187.07 seconds
Started Aug 28 10:27:52 PM UTC 24
Finished Aug 28 10:31:02 PM UTC 24
Peak memory 2114060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335193
2804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.3351932804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.3823988807
Short name T682
Test name
Test status
Simulation time 26925395423 ps
CPU time 70.95 seconds
Started Aug 28 10:27:44 PM UTC 24
Finished Aug 28 10:28:57 PM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823988807 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.3823988807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.1618560387
Short name T730
Test name
Test status
Simulation time 27754251208 ps
CPU time 128.5 seconds
Started Aug 28 10:27:43 PM UTC 24
Finished Aug 28 10:29:54 PM UTC 24
Peak memory 2191768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618560387 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.1618560387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.4065243760
Short name T635
Test name
Test status
Simulation time 1628647717 ps
CPU time 30.86 seconds
Started Aug 28 10:27:44 PM UTC 24
Finished Aug 28 10:28:16 PM UTC 24
Peak memory 561152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065243760 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.4065243760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.3125479026
Short name T614
Test name
Test status
Simulation time 1168166155 ps
CPU time 8.33 seconds
Started Aug 28 10:27:46 PM UTC 24
Finished Aug 28 10:27:56 PM UTC 24
Peak memory 243792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125479
026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.3125479026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.2560076863
Short name T141
Test name
Test status
Simulation time 77860957 ps
CPU time 2.99 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:06 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560076
863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2560076863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_alert_test.2058733052
Short name T650
Test name
Test status
Simulation time 17338921 ps
CPU time 1 seconds
Started Aug 28 10:28:25 PM UTC 24
Finished Aug 28 10:28:27 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058733052 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2058733052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.1914889820
Short name T29
Test name
Test status
Simulation time 687374481 ps
CPU time 6.74 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:28:16 PM UTC 24
Peak memory 243920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914889820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1914889820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.560026721
Short name T634
Test name
Test status
Simulation time 410658934 ps
CPU time 7.01 seconds
Started Aug 28 10:28:06 PM UTC 24
Finished Aug 28 10:28:14 PM UTC 24
Peak memory 303236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560026721 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.560026721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.222435222
Short name T746
Test name
Test status
Simulation time 3225508953 ps
CPU time 117.38 seconds
Started Aug 28 10:28:07 PM UTC 24
Finished Aug 28 10:30:07 PM UTC 24
Peak memory 764108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222435222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.222435222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.1192691822
Short name T684
Test name
Test status
Simulation time 1953662304 ps
CPU time 54.48 seconds
Started Aug 28 10:28:04 PM UTC 24
Finished Aug 28 10:29:00 PM UTC 24
Peak memory 667724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192691822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1192691822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.2361257263
Short name T146
Test name
Test status
Simulation time 468011031 ps
CPU time 1.56 seconds
Started Aug 28 10:28:05 PM UTC 24
Finished Aug 28 10:28:07 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361257263 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.2361257263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.497961096
Short name T631
Test name
Test status
Simulation time 553326021 ps
CPU time 4.89 seconds
Started Aug 28 10:28:06 PM UTC 24
Finished Aug 28 10:28:12 PM UTC 24
Peak memory 237716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497961096 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.497961096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.2279885819
Short name T840
Test name
Test status
Simulation time 10896848589 ps
CPU time 236.93 seconds
Started Aug 28 10:28:03 PM UTC 24
Finished Aug 28 10:32:04 PM UTC 24
Peak memory 1267912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279885819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2279885819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.44194001
Short name T269
Test name
Test status
Simulation time 660255503 ps
CPU time 5.52 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:27 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44194001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.44194001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_override.111153887
Short name T153
Test name
Test status
Simulation time 92759903 ps
CPU time 1.05 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:05 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111153887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.111153887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_perf.2687586866
Short name T633
Test name
Test status
Simulation time 254410648 ps
CPU time 5.73 seconds
Started Aug 28 10:28:07 PM UTC 24
Finished Aug 28 10:28:14 PM UTC 24
Peak memory 250000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687586866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2687586866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.4040789901
Short name T1238
Test name
Test status
Simulation time 24235257923 ps
CPU time 698.59 seconds
Started Aug 28 10:28:07 PM UTC 24
Finished Aug 28 10:39:53 PM UTC 24
Peak memory 2605248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040789901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.4040789901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.2484249113
Short name T674
Test name
Test status
Simulation time 8058152440 ps
CPU time 47.28 seconds
Started Aug 28 10:28:02 PM UTC 24
Finished Aug 28 10:28:51 PM UTC 24
Peak memory 401564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484249113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2484249113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.2202552822
Short name T879
Test name
Test status
Simulation time 44160963255 ps
CPU time 285.51 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:32:58 PM UTC 24
Peak memory 1526024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202552822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2202552822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.2547791105
Short name T663
Test name
Test status
Simulation time 478478341 ps
CPU time 28.7 seconds
Started Aug 28 10:28:07 PM UTC 24
Finished Aug 28 10:28:37 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547791105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2547791105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.690421596
Short name T653
Test name
Test status
Simulation time 871064420 ps
CPU time 7.38 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:29 PM UTC 24
Peak memory 231032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=690421596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.690421596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.3648031097
Short name T641
Test name
Test status
Simulation time 756275014 ps
CPU time 1.64 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:23 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648031
097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.3648031097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.1305668955
Short name T642
Test name
Test status
Simulation time 192187676 ps
CPU time 2 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:23 PM UTC 24
Peak memory 226444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305668
955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.1305668955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.2253365605
Short name T649
Test name
Test status
Simulation time 512494686 ps
CPU time 3.84 seconds
Started Aug 28 10:28:21 PM UTC 24
Finished Aug 28 10:28:27 PM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253365
605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.2253365605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.177048629
Short name T645
Test name
Test status
Simulation time 431288577 ps
CPU time 2.05 seconds
Started Aug 28 10:28:21 PM UTC 24
Finished Aug 28 10:28:25 PM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770486
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermarks
_tx.177048629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_hrst.2688814827
Short name T644
Test name
Test status
Simulation time 942772097 ps
CPU time 2.91 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:24 PM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688814
827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.2688814827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.3437135029
Short name T646
Test name
Test status
Simulation time 1146625398 ps
CPU time 12.6 seconds
Started Aug 28 10:28:11 PM UTC 24
Finished Aug 28 10:28:25 PM UTC 24
Peak memory 233052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343713
5029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.3437135029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.3464227992
Short name T700
Test name
Test status
Simulation time 22641137282 ps
CPU time 69.86 seconds
Started Aug 28 10:28:11 PM UTC 24
Finished Aug 28 10:29:23 PM UTC 24
Peak memory 993724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3464227992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stres
s_wr.3464227992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.3095573573
Short name T656
Test name
Test status
Simulation time 2171829855 ps
CPU time 5.28 seconds
Started Aug 28 10:28:24 PM UTC 24
Finished Aug 28 10:28:30 PM UTC 24
Peak memory 227032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095573
573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.3095573573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.2916794020
Short name T654
Test name
Test status
Simulation time 565036518 ps
CPU time 4.79 seconds
Started Aug 28 10:28:24 PM UTC 24
Finished Aug 28 10:28:30 PM UTC 24
Peak memory 216548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916794
020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.2916794020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_perf.2914273157
Short name T658
Test name
Test status
Simulation time 975740605 ps
CPU time 11.4 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:28:33 PM UTC 24
Peak memory 243788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914273
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.2914273157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.2148015157
Short name T652
Test name
Test status
Simulation time 368042402 ps
CPU time 3.3 seconds
Started Aug 28 10:28:23 PM UTC 24
Finished Aug 28 10:28:27 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148015
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.2148015157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.313717287
Short name T637
Test name
Test status
Simulation time 10602452517 ps
CPU time 11.37 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:28:21 PM UTC 24
Peak memory 233932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313717287 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.313717287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.3161219735
Short name T1072
Test name
Test status
Simulation time 32144280077 ps
CPU time 483.9 seconds
Started Aug 28 10:28:20 PM UTC 24
Finished Aug 28 10:36:30 PM UTC 24
Peak memory 6111360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316121
9735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.3161219735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.2520824997
Short name T662
Test name
Test status
Simulation time 2259368027 ps
CPU time 26.99 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:28:37 PM UTC 24
Peak memory 233540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520824997 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.2520824997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.2809501396
Short name T881
Test name
Test status
Simulation time 33693715145 ps
CPU time 286.47 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:32:59 PM UTC 24
Peak memory 3397760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809501396 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.2809501396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2340038234
Short name T636
Test name
Test status
Simulation time 589003139 ps
CPU time 8.48 seconds
Started Aug 28 10:28:08 PM UTC 24
Finished Aug 28 10:28:18 PM UTC 24
Peak memory 299032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340038234 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.2340038234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.1716833374
Short name T647
Test name
Test status
Simulation time 2520258819 ps
CPU time 12.39 seconds
Started Aug 28 10:28:13 PM UTC 24
Finished Aug 28 10:28:26 PM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716833
374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.1716833374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.3949825386
Short name T648
Test name
Test status
Simulation time 106562121 ps
CPU time 2.56 seconds
Started Aug 28 10:28:23 PM UTC 24
Finished Aug 28 10:28:26 PM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949825
386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.3949825386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_alert_test.633578417
Short name T675
Test name
Test status
Simulation time 36969537 ps
CPU time 0.91 seconds
Started Aug 28 10:28:51 PM UTC 24
Finished Aug 28 10:28:53 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633578417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.633578417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.469557476
Short name T659
Test name
Test status
Simulation time 90634793 ps
CPU time 2.23 seconds
Started Aug 28 10:28:30 PM UTC 24
Finished Aug 28 10:28:33 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469557476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.469557476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.2511823312
Short name T678
Test name
Test status
Simulation time 392350265 ps
CPU time 25.67 seconds
Started Aug 28 10:28:27 PM UTC 24
Finished Aug 28 10:28:54 PM UTC 24
Peak memory 301188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511823312 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.2511823312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.2191048449
Short name T753
Test name
Test status
Simulation time 12011464799 ps
CPU time 110.27 seconds
Started Aug 28 10:28:28 PM UTC 24
Finished Aug 28 10:30:21 PM UTC 24
Peak memory 868632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191048449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2191048449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.1469813065
Short name T695
Test name
Test status
Simulation time 27498019671 ps
CPU time 50.06 seconds
Started Aug 28 10:28:27 PM UTC 24
Finished Aug 28 10:29:19 PM UTC 24
Peak memory 463312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469813065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1469813065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.296014633
Short name T657
Test name
Test status
Simulation time 1175160922 ps
CPU time 1.97 seconds
Started Aug 28 10:28:27 PM UTC 24
Finished Aug 28 10:28:30 PM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296014633 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.296014633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.3474772381
Short name T661
Test name
Test status
Simulation time 749500223 ps
CPU time 5.48 seconds
Started Aug 28 10:28:28 PM UTC 24
Finished Aug 28 10:28:35 PM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474772381 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.3474772381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.3993064152
Short name T815
Test name
Test status
Simulation time 12649804441 ps
CPU time 177.97 seconds
Started Aug 28 10:28:26 PM UTC 24
Finished Aug 28 10:31:27 PM UTC 24
Peak memory 958868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993064152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3993064152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.844629575
Short name T685
Test name
Test status
Simulation time 659301892 ps
CPU time 17.99 seconds
Started Aug 28 10:28:43 PM UTC 24
Finished Aug 28 10:29:02 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844629575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.844629575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_override.1000129915
Short name T154
Test name
Test status
Simulation time 172590762 ps
CPU time 1.06 seconds
Started Aug 28 10:28:26 PM UTC 24
Finished Aug 28 10:28:28 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000129915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1000129915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_perf.2067224418
Short name T957
Test name
Test status
Simulation time 12865057553 ps
CPU time 344.37 seconds
Started Aug 28 10:28:28 PM UTC 24
Finished Aug 28 10:34:18 PM UTC 24
Peak memory 1102096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067224418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2067224418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.2197026003
Short name T660
Test name
Test status
Simulation time 220775685 ps
CPU time 5.25 seconds
Started Aug 28 10:28:29 PM UTC 24
Finished Aug 28 10:28:35 PM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197026003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2197026003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.3666006651
Short name T724
Test name
Test status
Simulation time 1648198802 ps
CPU time 75.51 seconds
Started Aug 28 10:28:25 PM UTC 24
Finished Aug 28 10:29:42 PM UTC 24
Peak memory 315408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666006651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3666006651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.2383400240
Short name T669
Test name
Test status
Simulation time 2193667238 ps
CPU time 14.03 seconds
Started Aug 28 10:28:30 PM UTC 24
Finished Aug 28 10:28:45 PM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383400240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2383400240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.1825622245
Short name T651
Test name
Test status
Simulation time 775329445 ps
CPU time 5.81 seconds
Started Aug 28 10:28:42 PM UTC 24
Finished Aug 28 10:28:48 PM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1825622245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.1825622245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.557735178
Short name T664
Test name
Test status
Simulation time 418499012 ps
CPU time 1.69 seconds
Started Aug 28 10:28:37 PM UTC 24
Finished Aug 28 10:28:40 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5577351
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.557735178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.2336191278
Short name T665
Test name
Test status
Simulation time 537633847 ps
CPU time 1.97 seconds
Started Aug 28 10:28:37 PM UTC 24
Finished Aug 28 10:28:40 PM UTC 24
Peak memory 216444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336191
278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.2336191278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.2335497350
Short name T670
Test name
Test status
Simulation time 1157916924 ps
CPU time 3.18 seconds
Started Aug 28 10:28:46 PM UTC 24
Finished Aug 28 10:28:50 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335497
350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermar
ks_acq.2335497350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.614570645
Short name T671
Test name
Test status
Simulation time 177560997 ps
CPU time 2.39 seconds
Started Aug 28 10:28:47 PM UTC 24
Finished Aug 28 10:28:50 PM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6145706
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermarks
_tx.614570645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.2627846805
Short name T668
Test name
Test status
Simulation time 2700228340 ps
CPU time 6.88 seconds
Started Aug 28 10:28:34 PM UTC 24
Finished Aug 28 10:28:42 PM UTC 24
Peak memory 228932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262784
6805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.2627846805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.1715803090
Short name T834
Test name
Test status
Simulation time 14643578256 ps
CPU time 204.85 seconds
Started Aug 28 10:28:34 PM UTC 24
Finished Aug 28 10:32:02 PM UTC 24
Peak memory 3602652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1715803090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.1715803090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.3339196255
Short name T681
Test name
Test status
Simulation time 1139159647 ps
CPU time 5.67 seconds
Started Aug 28 10:28:48 PM UTC 24
Finished Aug 28 10:28:55 PM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339196
255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.3339196255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.1213171407
Short name T680
Test name
Test status
Simulation time 2079505699 ps
CPU time 4.51 seconds
Started Aug 28 10:28:49 PM UTC 24
Finished Aug 28 10:28:55 PM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213171
407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.1213171407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_perf.308021713
Short name T145
Test name
Test status
Simulation time 597446308 ps
CPU time 6.73 seconds
Started Aug 28 10:28:39 PM UTC 24
Finished Aug 28 10:28:47 PM UTC 24
Peak memory 226880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080217
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.308021713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.1761449414
Short name T677
Test name
Test status
Simulation time 1167588629 ps
CPU time 4.88 seconds
Started Aug 28 10:28:48 PM UTC 24
Finished Aug 28 10:28:54 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761449
414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.1761449414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.3580818751
Short name T672
Test name
Test status
Simulation time 4185070579 ps
CPU time 18.67 seconds
Started Aug 28 10:28:31 PM UTC 24
Finished Aug 28 10:28:51 PM UTC 24
Peak memory 226568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580818751 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.3580818751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.3315029071
Short name T722
Test name
Test status
Simulation time 33406072036 ps
CPU time 60.04 seconds
Started Aug 28 10:28:41 PM UTC 24
Finished Aug 28 10:29:42 PM UTC 24
Peak memory 606344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331502
9071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.3315029071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.399086777
Short name T140
Test name
Test status
Simulation time 1449620501 ps
CPU time 14.37 seconds
Started Aug 28 10:28:31 PM UTC 24
Finished Aug 28 10:28:47 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399086777 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.399086777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.2665176315
Short name T694
Test name
Test status
Simulation time 13926535415 ps
CPU time 45.93 seconds
Started Aug 28 10:28:31 PM UTC 24
Finished Aug 28 10:29:18 PM UTC 24
Peak memory 216260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665176315 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.2665176315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.854770909
Short name T667
Test name
Test status
Simulation time 5615994787 ps
CPU time 9.49 seconds
Started Aug 28 10:28:31 PM UTC 24
Finished Aug 28 10:28:42 PM UTC 24
Peak memory 283072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854770909 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.854770909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.3774974756
Short name T625
Test name
Test status
Simulation time 2481267258 ps
CPU time 9.77 seconds
Started Aug 28 10:28:36 PM UTC 24
Finished Aug 28 10:28:47 PM UTC 24
Peak memory 233052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774974
756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.3774974756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.456477795
Short name T673
Test name
Test status
Simulation time 52978916 ps
CPU time 2 seconds
Started Aug 28 10:28:48 PM UTC 24
Finished Aug 28 10:28:51 PM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4564777
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.456477795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_alert_test.1062577601
Short name T709
Test name
Test status
Simulation time 22785419 ps
CPU time 0.94 seconds
Started Aug 28 10:29:26 PM UTC 24
Finished Aug 28 10:29:28 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062577601 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1062577601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.2222909140
Short name T689
Test name
Test status
Simulation time 2586023917 ps
CPU time 10.71 seconds
Started Aug 28 10:28:55 PM UTC 24
Finished Aug 28 10:29:07 PM UTC 24
Peak memory 313560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222909140 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.2222909140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.4054711096
Short name T810
Test name
Test status
Simulation time 4614816377 ps
CPU time 138.8 seconds
Started Aug 28 10:28:56 PM UTC 24
Finished Aug 28 10:31:17 PM UTC 24
Peak memory 536776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054711096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.4054711096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.2119328856
Short name T816
Test name
Test status
Simulation time 8783162625 ps
CPU time 152.13 seconds
Started Aug 28 10:28:54 PM UTC 24
Finished Aug 28 10:31:28 PM UTC 24
Peak memory 755980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119328856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2119328856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.582064256
Short name T683
Test name
Test status
Simulation time 1266129663 ps
CPU time 1.74 seconds
Started Aug 28 10:28:55 PM UTC 24
Finished Aug 28 10:28:57 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582064256 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.582064256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.652670413
Short name T686
Test name
Test status
Simulation time 195332447 ps
CPU time 7.03 seconds
Started Aug 28 10:28:55 PM UTC 24
Finished Aug 28 10:29:03 PM UTC 24
Peak memory 254028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652670413 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.652670413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.1634090119
Short name T945
Test name
Test status
Simulation time 20727125625 ps
CPU time 304.5 seconds
Started Aug 28 10:28:53 PM UTC 24
Finished Aug 28 10:34:01 PM UTC 24
Peak memory 1517636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634090119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1634090119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.615067224
Short name T734
Test name
Test status
Simulation time 5174214928 ps
CPU time 33.71 seconds
Started Aug 28 10:29:20 PM UTC 24
Finished Aug 28 10:29:56 PM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615067224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.615067224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_mode_toggle.3621394838
Short name T706
Test name
Test status
Simulation time 142134054 ps
CPU time 6.81 seconds
Started Aug 28 10:29:19 PM UTC 24
Finished Aug 28 10:29:27 PM UTC 24
Peak memory 233108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621394838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3621394838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_override.4054408657
Short name T676
Test name
Test status
Simulation time 40641951 ps
CPU time 0.96 seconds
Started Aug 28 10:28:52 PM UTC 24
Finished Aug 28 10:28:54 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054408657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.4054408657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_perf.1915635306
Short name T705
Test name
Test status
Simulation time 1636063800 ps
CPU time 27.99 seconds
Started Aug 28 10:28:56 PM UTC 24
Finished Aug 28 10:29:25 PM UTC 24
Peak memory 356360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915635306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1915635306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.2874016423
Short name T687
Test name
Test status
Simulation time 402712066 ps
CPU time 6.5 seconds
Started Aug 28 10:28:56 PM UTC 24
Finished Aug 28 10:29:04 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874016423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2874016423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.2235581906
Short name T701
Test name
Test status
Simulation time 1442894538 ps
CPU time 69.83 seconds
Started Aug 28 10:28:51 PM UTC 24
Finished Aug 28 10:30:03 PM UTC 24
Peak memory 366756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235581906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2235581906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.1878447536
Short name T698
Test name
Test status
Simulation time 966405115 ps
CPU time 22.36 seconds
Started Aug 28 10:28:58 PM UTC 24
Finished Aug 28 10:29:22 PM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878447536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1878447536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.927905455
Short name T699
Test name
Test status
Simulation time 1004165512 ps
CPU time 3.71 seconds
Started Aug 28 10:29:17 PM UTC 24
Finished Aug 28 10:29:22 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=927905455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.927905455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.3567580153
Short name T692
Test name
Test status
Simulation time 173378136 ps
CPU time 1.9 seconds
Started Aug 28 10:29:11 PM UTC 24
Finished Aug 28 10:29:14 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567580
153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.3567580153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.919459820
Short name T693
Test name
Test status
Simulation time 952327130 ps
CPU time 2.68 seconds
Started Aug 28 10:29:13 PM UTC 24
Finished Aug 28 10:29:17 PM UTC 24
Peak memory 218676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9194598
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.919459820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.1230600014
Short name T707
Test name
Test status
Simulation time 2069347070 ps
CPU time 4.7 seconds
Started Aug 28 10:29:22 PM UTC 24
Finished Aug 28 10:29:27 PM UTC 24
Peak memory 216508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230600
014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar
ks_acq.1230600014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.186890251
Short name T703
Test name
Test status
Simulation time 556244043 ps
CPU time 2.45 seconds
Started Aug 28 10:29:22 PM UTC 24
Finished Aug 28 10:29:25 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868902
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermarks
_tx.186890251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.1825949813
Short name T702
Test name
Test status
Simulation time 430367305 ps
CPU time 4.21 seconds
Started Aug 28 10:29:19 PM UTC 24
Finished Aug 28 10:29:25 PM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825949
813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.1825949813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.2223169604
Short name T691
Test name
Test status
Simulation time 2900301897 ps
CPU time 7.41 seconds
Started Aug 28 10:29:05 PM UTC 24
Finished Aug 28 10:29:13 PM UTC 24
Peak memory 228944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222316
9604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.2223169604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.4237865542
Short name T760
Test name
Test status
Simulation time 7626232768 ps
CPU time 78.63 seconds
Started Aug 28 10:29:06 PM UTC 24
Finished Aug 28 10:30:26 PM UTC 24
Peak memory 2056340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4237865542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stres
s_wr.4237865542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.3827853162
Short name T713
Test name
Test status
Simulation time 2075749807 ps
CPU time 4.65 seconds
Started Aug 28 10:29:24 PM UTC 24
Finished Aug 28 10:29:30 PM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827853
162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.3827853162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.3961755416
Short name T714
Test name
Test status
Simulation time 2548139053 ps
CPU time 3.94 seconds
Started Aug 28 10:29:25 PM UTC 24
Finished Aug 28 10:29:30 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961755
416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.3961755416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_perf.3483862854
Short name T697
Test name
Test status
Simulation time 2560884428 ps
CPU time 5.53 seconds
Started Aug 28 10:29:14 PM UTC 24
Finished Aug 28 10:29:21 PM UTC 24
Peak memory 233592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483862
854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.3483862854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.1015818180
Short name T711
Test name
Test status
Simulation time 1942167239 ps
CPU time 4.32 seconds
Started Aug 28 10:29:23 PM UTC 24
Finished Aug 28 10:29:28 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015818
180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.1015818180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.602819510
Short name T723
Test name
Test status
Simulation time 1143762031 ps
CPU time 37.66 seconds
Started Aug 28 10:29:03 PM UTC 24
Finished Aug 28 10:29:42 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602819510 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.602819510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.1612219606
Short name T732
Test name
Test status
Simulation time 7058060303 ps
CPU time 38.82 seconds
Started Aug 28 10:29:15 PM UTC 24
Finished Aug 28 10:29:55 PM UTC 24
Peak memory 299092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161221
9606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.1612219606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.3642923170
Short name T704
Test name
Test status
Simulation time 10652840389 ps
CPU time 20.54 seconds
Started Aug 28 10:29:04 PM UTC 24
Finished Aug 28 10:29:25 PM UTC 24
Peak memory 233396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642923170 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.3642923170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.573853179
Short name T1520
Test name
Test status
Simulation time 53233614806 ps
CPU time 988.24 seconds
Started Aug 28 10:29:03 PM UTC 24
Finished Aug 28 10:45:42 PM UTC 24
Peak memory 8310936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573853179 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.573853179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3005754501
Short name T696
Test name
Test status
Simulation time 4514858042 ps
CPU time 10.19 seconds
Started Aug 28 10:29:08 PM UTC 24
Finished Aug 28 10:29:19 PM UTC 24
Peak memory 233892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005754
501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3005754501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.1605974431
Short name T716
Test name
Test status
Simulation time 301614386 ps
CPU time 7.67 seconds
Started Aug 28 10:29:23 PM UTC 24
Finished Aug 28 10:29:31 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605974
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.1605974431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_alert_test.1454746609
Short name T741
Test name
Test status
Simulation time 18564894 ps
CPU time 1 seconds
Started Aug 28 10:29:58 PM UTC 24
Finished Aug 28 10:30:01 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454746609 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1454746609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.4251907665
Short name T720
Test name
Test status
Simulation time 113308497 ps
CPU time 5.32 seconds
Started Aug 28 10:29:31 PM UTC 24
Finished Aug 28 10:29:37 PM UTC 24
Peak memory 235940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251907665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4251907665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.2681188950
Short name T721
Test name
Test status
Simulation time 1475582244 ps
CPU time 9.63 seconds
Started Aug 28 10:29:28 PM UTC 24
Finished Aug 28 10:29:39 PM UTC 24
Peak memory 295004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681188950 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.2681188950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.4228627420
Short name T818
Test name
Test status
Simulation time 4793688493 ps
CPU time 120 seconds
Started Aug 28 10:29:29 PM UTC 24
Finished Aug 28 10:31:31 PM UTC 24
Peak memory 327948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228627420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4228627420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.4287413547
Short name T777
Test name
Test status
Simulation time 2446453204 ps
CPU time 69 seconds
Started Aug 28 10:29:28 PM UTC 24
Finished Aug 28 10:30:39 PM UTC 24
Peak memory 774504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287413547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.4287413547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.120941687
Short name T715
Test name
Test status
Simulation time 438288228 ps
CPU time 1.37 seconds
Started Aug 28 10:29:28 PM UTC 24
Finished Aug 28 10:29:31 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120941687 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.120941687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.262039358
Short name T719
Test name
Test status
Simulation time 108045130 ps
CPU time 7.04 seconds
Started Aug 28 10:29:28 PM UTC 24
Finished Aug 28 10:29:37 PM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262039358 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.262039358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.1406624052
Short name T914
Test name
Test status
Simulation time 8815162191 ps
CPU time 247.84 seconds
Started Aug 28 10:29:26 PM UTC 24
Finished Aug 28 10:33:38 PM UTC 24
Peak memory 1259936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406624052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1406624052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.4261476863
Short name T747
Test name
Test status
Simulation time 1172870537 ps
CPU time 13.41 seconds
Started Aug 28 10:29:55 PM UTC 24
Finished Aug 28 10:30:10 PM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261476863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.4261476863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_override.380869204
Short name T710
Test name
Test status
Simulation time 34358261 ps
CPU time 0.87 seconds
Started Aug 28 10:29:26 PM UTC 24
Finished Aug 28 10:29:28 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380869204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.380869204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_perf.1654345446
Short name T1739
Test name
Test status
Simulation time 52151599245 ps
CPU time 2336.31 seconds
Started Aug 28 10:29:30 PM UTC 24
Finished Aug 28 11:08:52 PM UTC 24
Peak memory 1083644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654345446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1654345446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.64945792
Short name T718
Test name
Test status
Simulation time 162120940 ps
CPU time 1.74 seconds
Started Aug 28 10:29:30 PM UTC 24
Finished Aug 28 10:29:32 PM UTC 24
Peak memory 236472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64945792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.64945792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.317044231
Short name T782
Test name
Test status
Simulation time 5190422034 ps
CPU time 75.47 seconds
Started Aug 28 10:29:26 PM UTC 24
Finished Aug 28 10:30:43 PM UTC 24
Peak memory 311780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317044231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.317044231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.3152916034
Short name T731
Test name
Test status
Simulation time 2728901928 ps
CPU time 23.23 seconds
Started Aug 28 10:29:31 PM UTC 24
Finished Aug 28 10:29:55 PM UTC 24
Peak memory 233964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152916034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3152916034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.1587502041
Short name T735
Test name
Test status
Simulation time 3857587056 ps
CPU time 5.35 seconds
Started Aug 28 10:29:50 PM UTC 24
Finished Aug 28 10:29:56 PM UTC 24
Peak memory 230984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1587502041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad
dr.1587502041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.2621687809
Short name T160
Test name
Test status
Simulation time 158708534 ps
CPU time 1.75 seconds
Started Aug 28 10:29:43 PM UTC 24
Finished Aug 28 10:29:46 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621687
809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.2621687809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.2835120726
Short name T727
Test name
Test status
Simulation time 681177305 ps
CPU time 2.22 seconds
Started Aug 28 10:29:46 PM UTC 24
Finished Aug 28 10:29:49 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835120
726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.2835120726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.727632990
Short name T743
Test name
Test status
Simulation time 890787006 ps
CPU time 3.89 seconds
Started Aug 28 10:29:56 PM UTC 24
Finished Aug 28 10:30:01 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7276329
90 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark
s_acq.727632990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.122881897
Short name T740
Test name
Test status
Simulation time 447867517 ps
CPU time 1.32 seconds
Started Aug 28 10:29:56 PM UTC 24
Finished Aug 28 10:29:59 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228818
97 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermarks
_tx.122881897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.3663988988
Short name T733
Test name
Test status
Simulation time 334789399 ps
CPU time 3.55 seconds
Started Aug 28 10:29:51 PM UTC 24
Finished Aug 28 10:29:55 PM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663988
988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.3663988988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.3072970068
Short name T728
Test name
Test status
Simulation time 2713151972 ps
CPU time 11.11 seconds
Started Aug 28 10:29:38 PM UTC 24
Finished Aug 28 10:29:50 PM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307297
0068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.3072970068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.2185484489
Short name T759
Test name
Test status
Simulation time 15373165974 ps
CPU time 44.15 seconds
Started Aug 28 10:29:40 PM UTC 24
Finished Aug 28 10:30:26 PM UTC 24
Peak memory 964692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2185484489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.2185484489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.2560017593
Short name T708
Test name
Test status
Simulation time 1523864528 ps
CPU time 3.95 seconds
Started Aug 28 10:29:57 PM UTC 24
Finished Aug 28 10:30:03 PM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560017
593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.2560017593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.2460544871
Short name T679
Test name
Test status
Simulation time 2400245943 ps
CPU time 4.28 seconds
Started Aug 28 10:29:57 PM UTC 24
Finished Aug 28 10:30:03 PM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460544
871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_ad
dr.2460544871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_perf.601066755
Short name T739
Test name
Test status
Simulation time 813611352 ps
CPU time 10.77 seconds
Started Aug 28 10:29:47 PM UTC 24
Finished Aug 28 10:29:58 PM UTC 24
Peak memory 233668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6010667
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.601066755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.3845116288
Short name T742
Test name
Test status
Simulation time 2133950262 ps
CPU time 3.83 seconds
Started Aug 28 10:29:56 PM UTC 24
Finished Aug 28 10:30:01 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845116
288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.3845116288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.1069381443
Short name T725
Test name
Test status
Simulation time 900539238 ps
CPU time 11.26 seconds
Started Aug 28 10:29:32 PM UTC 24
Finished Aug 28 10:29:44 PM UTC 24
Peak memory 233604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069381443 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.1069381443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.3842949664
Short name T755
Test name
Test status
Simulation time 11066692857 ps
CPU time 35.65 seconds
Started Aug 28 10:29:47 PM UTC 24
Finished Aug 28 10:30:24 PM UTC 24
Peak memory 248032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384294
9664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.3842949664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.2520815895
Short name T738
Test name
Test status
Simulation time 1015441600 ps
CPU time 23.15 seconds
Started Aug 28 10:29:33 PM UTC 24
Finished Aug 28 10:29:57 PM UTC 24
Peak memory 233016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520815895 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.2520815895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.4181745469
Short name T781
Test name
Test status
Simulation time 37130662793 ps
CPU time 68.37 seconds
Started Aug 28 10:29:33 PM UTC 24
Finished Aug 28 10:30:43 PM UTC 24
Peak memory 1204504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181745469 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.4181745469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.2515397764
Short name T750
Test name
Test status
Simulation time 4210154199 ps
CPU time 32.31 seconds
Started Aug 28 10:29:37 PM UTC 24
Finished Aug 28 10:30:11 PM UTC 24
Peak memory 616644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515397764 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.2515397764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.2393746420
Short name T729
Test name
Test status
Simulation time 1604157657 ps
CPU time 8.16 seconds
Started Aug 28 10:29:43 PM UTC 24
Finished Aug 28 10:29:53 PM UTC 24
Peak memory 233076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393746
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.2393746420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.2810773306
Short name T744
Test name
Test status
Simulation time 168564209 ps
CPU time 6.35 seconds
Started Aug 28 10:29:56 PM UTC 24
Finished Aug 28 10:30:04 PM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810773
306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2810773306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_alert_test.256945404
Short name T104
Test name
Test status
Simulation time 27981892 ps
CPU time 0.9 seconds
Started Aug 28 10:22:04 PM UTC 24
Finished Aug 28 10:22:06 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256945404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.256945404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.2226922896
Short name T37
Test name
Test status
Simulation time 252343673 ps
CPU time 1.97 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:21:54 PM UTC 24
Peak memory 226436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226922896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2226922896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.933496556
Short name T173
Test name
Test status
Simulation time 2856203441 ps
CPU time 23.31 seconds
Started Aug 28 10:21:48 PM UTC 24
Finished Aug 28 10:22:13 PM UTC 24
Peak memory 309596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933496556 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.933496556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.720346575
Short name T47
Test name
Test status
Simulation time 35064862942 ps
CPU time 94.3 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:23:27 PM UTC 24
Peak memory 489944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720346575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.720346575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.4134552908
Short name T107
Test name
Test status
Simulation time 2772930388 ps
CPU time 88.98 seconds
Started Aug 28 10:21:48 PM UTC 24
Finished Aug 28 10:23:20 PM UTC 24
Peak memory 569548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134552908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.4134552908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.603091750
Short name T44
Test name
Test status
Simulation time 113420103 ps
CPU time 1.16 seconds
Started Aug 28 10:21:48 PM UTC 24
Finished Aug 28 10:21:51 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603091750 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.603091750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.1041288778
Short name T161
Test name
Test status
Simulation time 209128483 ps
CPU time 10.54 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:22:03 PM UTC 24
Peak memory 256084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041288778 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.1041288778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.1236718002
Short name T262
Test name
Test status
Simulation time 2804464509 ps
CPU time 31.25 seconds
Started Aug 28 10:21:59 PM UTC 24
Finished Aug 28 10:22:32 PM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236718002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1236718002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_override.3841519475
Short name T85
Test name
Test status
Simulation time 260779353 ps
CPU time 1.06 seconds
Started Aug 28 10:21:47 PM UTC 24
Finished Aug 28 10:21:49 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841519475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3841519475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_perf.4091395998
Short name T878
Test name
Test status
Simulation time 48371267306 ps
CPU time 657.89 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:32:57 PM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091395998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.4091395998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.867306048
Short name T194
Test name
Test status
Simulation time 144577387 ps
CPU time 1.69 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:21:54 PM UTC 24
Peak memory 226444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867306048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.867306048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.4221893430
Short name T282
Test name
Test status
Simulation time 1790148601 ps
CPU time 33.59 seconds
Started Aug 28 10:21:47 PM UTC 24
Finished Aug 28 10:22:22 PM UTC 24
Peak memory 430284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221893430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4221893430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.3493693154
Short name T339
Test name
Test status
Simulation time 1098151508 ps
CPU time 48.02 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:22:41 PM UTC 24
Peak memory 233168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493693154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3493693154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.3638572694
Short name T169
Test name
Test status
Simulation time 81042411 ps
CPU time 1.39 seconds
Started Aug 28 10:22:04 PM UTC 24
Finished Aug 28 10:22:06 PM UTC 24
Peak memory 246616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638572694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3638572694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3911833568
Short name T71
Test name
Test status
Simulation time 642790072 ps
CPU time 6.96 seconds
Started Aug 28 10:21:56 PM UTC 24
Finished Aug 28 10:22:04 PM UTC 24
Peak memory 230924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3911833568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3911833568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.2000234628
Short name T318
Test name
Test status
Simulation time 509745773 ps
CPU time 1.8 seconds
Started Aug 28 10:21:53 PM UTC 24
Finished Aug 28 10:21:56 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000234
628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.2000234628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.4147720144
Short name T320
Test name
Test status
Simulation time 221450840 ps
CPU time 2.2 seconds
Started Aug 28 10:21:55 PM UTC 24
Finished Aug 28 10:21:59 PM UTC 24
Peak memory 216048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147720
144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.4147720144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.1962547578
Short name T232
Test name
Test status
Simulation time 5005428490 ps
CPU time 4.59 seconds
Started Aug 28 10:21:59 PM UTC 24
Finished Aug 28 10:22:05 PM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962547
578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermark
s_acq.1962547578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.379250909
Short name T319
Test name
Test status
Simulation time 10618729552 ps
CPU time 5.68 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:21:58 PM UTC 24
Peak memory 227256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379250
909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.379250909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.2215474093
Short name T349
Test name
Test status
Simulation time 6133346375 ps
CPU time 59.7 seconds
Started Aug 28 10:21:53 PM UTC 24
Finished Aug 28 10:22:55 PM UTC 24
Peak memory 1618324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2215474093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress
_wr.2215474093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.953699875
Short name T162
Test name
Test status
Simulation time 2066072732 ps
CPU time 5.47 seconds
Started Aug 28 10:22:02 PM UTC 24
Finished Aug 28 10:22:09 PM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9536998
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.953699875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.3999224127
Short name T74
Test name
Test status
Simulation time 580240824 ps
CPU time 3.5 seconds
Started Aug 28 10:22:02 PM UTC 24
Finished Aug 28 10:22:07 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999224
127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.3999224127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_perf.447150494
Short name T288
Test name
Test status
Simulation time 592125390 ps
CPU time 7.8 seconds
Started Aug 28 10:21:56 PM UTC 24
Finished Aug 28 10:22:04 PM UTC 24
Peak memory 226608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4471504
94 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.447150494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.3200543641
Short name T171
Test name
Test status
Simulation time 564821283 ps
CPU time 4.98 seconds
Started Aug 28 10:22:01 PM UTC 24
Finished Aug 28 10:22:07 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200543
641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.3200543641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.2539542079
Short name T197
Test name
Test status
Simulation time 95157884693 ps
CPU time 45.48 seconds
Started Aug 28 10:21:56 PM UTC 24
Finished Aug 28 10:22:42 PM UTC 24
Peak memory 299152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253954
2079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.2539542079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2237746332
Short name T185
Test name
Test status
Simulation time 1861900799 ps
CPU time 36.25 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:22:29 PM UTC 24
Peak memory 226532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237746332 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.2237746332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.760894835
Short name T63
Test name
Test status
Simulation time 55707783536 ps
CPU time 151.51 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:24:25 PM UTC 24
Peak memory 2195868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760894835 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.760894835
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2158537704
Short name T331
Test name
Test status
Simulation time 4688326639 ps
CPU time 38.5 seconds
Started Aug 28 10:21:51 PM UTC 24
Finished Aug 28 10:22:31 PM UTC 24
Peak memory 604376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158537704 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.2158537704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.1926071434
Short name T322
Test name
Test status
Simulation time 2700659723 ps
CPU time 10.81 seconds
Started Aug 28 10:21:53 PM UTC 24
Finished Aug 28 10:22:05 PM UTC 24
Peak memory 233148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926071
434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.1926071434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.1263210573
Short name T77
Test name
Test status
Simulation time 484287501 ps
CPU time 7.96 seconds
Started Aug 28 10:22:01 PM UTC 24
Finished Aug 28 10:22:10 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263210
573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.1263210573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_alert_test.4232561547
Short name T771
Test name
Test status
Simulation time 16571070 ps
CPU time 1 seconds
Started Aug 28 10:30:35 PM UTC 24
Finished Aug 28 10:30:37 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232561547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.4232561547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.3658057496
Short name T748
Test name
Test status
Simulation time 284237442 ps
CPU time 4.71 seconds
Started Aug 28 10:30:04 PM UTC 24
Finished Aug 28 10:30:10 PM UTC 24
Peak memory 226840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658057496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3658057496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.1661452476
Short name T751
Test name
Test status
Simulation time 276545183 ps
CPU time 8.33 seconds
Started Aug 28 10:30:02 PM UTC 24
Finished Aug 28 10:30:11 PM UTC 24
Peak memory 272720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661452476 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.1661452476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.3962004736
Short name T843
Test name
Test status
Simulation time 12509420941 ps
CPU time 122.18 seconds
Started Aug 28 10:30:03 PM UTC 24
Finished Aug 28 10:32:08 PM UTC 24
Peak memory 887044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962004736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3962004736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.1186111899
Short name T847
Test name
Test status
Simulation time 2084059380 ps
CPU time 134.02 seconds
Started Aug 28 10:30:02 PM UTC 24
Finished Aug 28 10:32:18 PM UTC 24
Peak memory 696352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186111899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1186111899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.2498701607
Short name T745
Test name
Test status
Simulation time 298279719 ps
CPU time 2.21 seconds
Started Aug 28 10:30:02 PM UTC 24
Finished Aug 28 10:30:05 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498701607 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.2498701607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.4016068917
Short name T749
Test name
Test status
Simulation time 402763193 ps
CPU time 6.37 seconds
Started Aug 28 10:30:03 PM UTC 24
Finished Aug 28 10:30:11 PM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016068917 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.4016068917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.78307169
Short name T794
Test name
Test status
Simulation time 19563757509 ps
CPU time 62.01 seconds
Started Aug 28 10:30:01 PM UTC 24
Finished Aug 28 10:31:05 PM UTC 24
Peak memory 835872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78307169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.78307169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.3512627461
Short name T266
Test name
Test status
Simulation time 2023508537 ps
CPU time 9.51 seconds
Started Aug 28 10:30:27 PM UTC 24
Finished Aug 28 10:30:38 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512627461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3512627461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_override.296898302
Short name T155
Test name
Test status
Simulation time 47524499 ps
CPU time 1.06 seconds
Started Aug 28 10:30:00 PM UTC 24
Finished Aug 28 10:30:02 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296898302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.296898302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_perf.2025788690
Short name T764
Test name
Test status
Simulation time 3369275489 ps
CPU time 26.51 seconds
Started Aug 28 10:30:03 PM UTC 24
Finished Aug 28 10:30:31 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025788690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2025788690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.3959193111
Short name T812
Test name
Test status
Simulation time 2021930778 ps
CPU time 77 seconds
Started Aug 28 10:30:04 PM UTC 24
Finished Aug 28 10:31:23 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959193111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3959193111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.3798933780
Short name T779
Test name
Test status
Simulation time 3553200415 ps
CPU time 39.57 seconds
Started Aug 28 10:30:00 PM UTC 24
Finished Aug 28 10:30:41 PM UTC 24
Peak memory 315832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798933780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3798933780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.3903308659
Short name T762
Test name
Test status
Simulation time 3940702595 ps
CPU time 22.12 seconds
Started Aug 28 10:30:04 PM UTC 24
Finished Aug 28 10:30:28 PM UTC 24
Peak memory 233336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903308659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3903308659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.2962125372
Short name T769
Test name
Test status
Simulation time 2588337890 ps
CPU time 6.6 seconds
Started Aug 28 10:30:26 PM UTC 24
Finished Aug 28 10:30:34 PM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2962125372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.2962125372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.358203251
Short name T757
Test name
Test status
Simulation time 215691851 ps
CPU time 1.73 seconds
Started Aug 28 10:30:22 PM UTC 24
Finished Aug 28 10:30:25 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582032
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.358203251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.2380634906
Short name T763
Test name
Test status
Simulation time 712832840 ps
CPU time 2.15 seconds
Started Aug 28 10:30:25 PM UTC 24
Finished Aug 28 10:30:28 PM UTC 24
Peak memory 220620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380634
906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.2380634906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.108020726
Short name T766
Test name
Test status
Simulation time 793913041 ps
CPU time 1.78 seconds
Started Aug 28 10:30:29 PM UTC 24
Finished Aug 28 10:30:31 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080207
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_acq.108020726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.2160529892
Short name T765
Test name
Test status
Simulation time 768675456 ps
CPU time 1.61 seconds
Started Aug 28 10:30:29 PM UTC 24
Finished Aug 28 10:30:31 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160529
892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_tx.2160529892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.2540895279
Short name T754
Test name
Test status
Simulation time 3856897258 ps
CPU time 8.5 seconds
Started Aug 28 10:30:12 PM UTC 24
Finished Aug 28 10:30:21 PM UTC 24
Peak memory 233100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254089
5279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.2540895279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.70131355
Short name T913
Test name
Test status
Simulation time 18184627621 ps
CPU time 202.17 seconds
Started Aug 28 10:30:13 PM UTC 24
Finished Aug 28 10:33:38 PM UTC 24
Peak memory 2857108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=70131355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.70131355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.418733500
Short name T774
Test name
Test status
Simulation time 1670490906 ps
CPU time 3.66 seconds
Started Aug 28 10:30:33 PM UTC 24
Finished Aug 28 10:30:38 PM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187335
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.418733500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.79313301
Short name T775
Test name
Test status
Simulation time 1773520203 ps
CPU time 3.8 seconds
Started Aug 28 10:30:34 PM UTC 24
Finished Aug 28 10:30:39 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7931330
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_addr.79313301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.2803025518
Short name T772
Test name
Test status
Simulation time 482934496 ps
CPU time 2.23 seconds
Started Aug 28 10:30:34 PM UTC 24
Finished Aug 28 10:30:37 PM UTC 24
Peak memory 233424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803025
518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.2803025518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_perf.3985375325
Short name T768
Test name
Test status
Simulation time 1357529401 ps
CPU time 6.75 seconds
Started Aug 28 10:30:25 PM UTC 24
Finished Aug 28 10:30:33 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985375
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.3985375325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.2638054631
Short name T773
Test name
Test status
Simulation time 501741070 ps
CPU time 4.64 seconds
Started Aug 28 10:30:32 PM UTC 24
Finished Aug 28 10:30:38 PM UTC 24
Peak memory 216240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638054
631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.2638054631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.1472124010
Short name T758
Test name
Test status
Simulation time 5243349941 ps
CPU time 16.89 seconds
Started Aug 28 10:30:07 PM UTC 24
Finished Aug 28 10:30:26 PM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472124010 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.1472124010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.1521098405
Short name T894
Test name
Test status
Simulation time 58666652127 ps
CPU time 174.08 seconds
Started Aug 28 10:30:25 PM UTC 24
Finished Aug 28 10:33:22 PM UTC 24
Peak memory 2369776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152109
8405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.1521098405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.210388104
Short name T776
Test name
Test status
Simulation time 4417519692 ps
CPU time 26.56 seconds
Started Aug 28 10:30:11 PM UTC 24
Finished Aug 28 10:30:39 PM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210388104 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.210388104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2932815641
Short name T1126
Test name
Test status
Simulation time 58167010217 ps
CPU time 436.07 seconds
Started Aug 28 10:30:10 PM UTC 24
Finished Aug 28 10:37:33 PM UTC 24
Peak memory 4776092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932815641 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.2932815641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.2791285404
Short name T752
Test name
Test status
Simulation time 269085229 ps
CPU time 1.93 seconds
Started Aug 28 10:30:12 PM UTC 24
Finished Aug 28 10:30:15 PM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791285404 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.2791285404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.1895969852
Short name T761
Test name
Test status
Simulation time 2095516288 ps
CPU time 9.53 seconds
Started Aug 28 10:30:16 PM UTC 24
Finished Aug 28 10:30:26 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895969
852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.1895969852
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_alert_test.3904187058
Short name T804
Test name
Test status
Simulation time 23812262 ps
CPU time 0.96 seconds
Started Aug 28 10:31:14 PM UTC 24
Finished Aug 28 10:31:15 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904187058 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3904187058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.414772097
Short name T784
Test name
Test status
Simulation time 654662056 ps
CPU time 3.43 seconds
Started Aug 28 10:30:41 PM UTC 24
Finished Aug 28 10:30:45 PM UTC 24
Peak memory 229184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414772097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.414772097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.2893285504
Short name T786
Test name
Test status
Simulation time 2767360615 ps
CPU time 13.48 seconds
Started Aug 28 10:30:38 PM UTC 24
Finished Aug 28 10:30:53 PM UTC 24
Peak memory 348376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893285504 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.2893285504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3908352224
Short name T883
Test name
Test status
Simulation time 2698640821 ps
CPU time 141.09 seconds
Started Aug 28 10:30:40 PM UTC 24
Finished Aug 28 10:33:03 PM UTC 24
Peak memory 432356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908352224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3908352224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.3216269378
Short name T846
Test name
Test status
Simulation time 1434257868 ps
CPU time 96.21 seconds
Started Aug 28 10:30:38 PM UTC 24
Finished Aug 28 10:32:17 PM UTC 24
Peak memory 467012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216269378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3216269378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.1944812484
Short name T780
Test name
Test status
Simulation time 169069118 ps
CPU time 1.57 seconds
Started Aug 28 10:30:38 PM UTC 24
Finished Aug 28 10:30:41 PM UTC 24
Peak memory 214288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944812484 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.1944812484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.2257451889
Short name T785
Test name
Test status
Simulation time 173328003 ps
CPU time 6.98 seconds
Started Aug 28 10:30:38 PM UTC 24
Finished Aug 28 10:30:46 PM UTC 24
Peak memory 246096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257451889 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.2257451889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.824453867
Short name T122
Test name
Test status
Simulation time 3903574369 ps
CPU time 84.95 seconds
Started Aug 28 10:30:37 PM UTC 24
Finished Aug 28 10:32:04 PM UTC 24
Peak memory 1181888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824453867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.824453867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_mode_toggle.2145170699
Short name T796
Test name
Test status
Simulation time 222202491 ps
CPU time 2.6 seconds
Started Aug 28 10:31:03 PM UTC 24
Finished Aug 28 10:31:07 PM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145170699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2145170699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_override.3700351100
Short name T778
Test name
Test status
Simulation time 89719113 ps
CPU time 1.1 seconds
Started Aug 28 10:30:37 PM UTC 24
Finished Aug 28 10:30:39 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700351100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3700351100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.214827704
Short name T783
Test name
Test status
Simulation time 280227936 ps
CPU time 3.59 seconds
Started Aug 28 10:30:40 PM UTC 24
Finished Aug 28 10:30:44 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214827704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.214827704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.4112941218
Short name T849
Test name
Test status
Simulation time 1793973472 ps
CPU time 102.38 seconds
Started Aug 28 10:30:36 PM UTC 24
Finished Aug 28 10:32:21 PM UTC 24
Peak memory 360544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112941218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.4112941218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.1870397405
Short name T788
Test name
Test status
Simulation time 2767679382 ps
CPU time 13.84 seconds
Started Aug 28 10:30:40 PM UTC 24
Finished Aug 28 10:30:55 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870397405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1870397405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.1747518247
Short name T799
Test name
Test status
Simulation time 9062579693 ps
CPU time 9.68 seconds
Started Aug 28 10:31:00 PM UTC 24
Finished Aug 28 10:31:11 PM UTC 24
Peak memory 226960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1747518247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_ad
dr.1747518247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.951460960
Short name T791
Test name
Test status
Simulation time 232444407 ps
CPU time 1.69 seconds
Started Aug 28 10:30:55 PM UTC 24
Finished Aug 28 10:30:58 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9514609
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.951460960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.1930642085
Short name T792
Test name
Test status
Simulation time 217691717 ps
CPU time 1.38 seconds
Started Aug 28 10:30:58 PM UTC 24
Finished Aug 28 10:31:00 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930642
085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.1930642085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.690338791
Short name T800
Test name
Test status
Simulation time 3295110553 ps
CPU time 5.61 seconds
Started Aug 28 10:31:05 PM UTC 24
Finished Aug 28 10:31:12 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6903387
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_acq.690338791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.3205753233
Short name T798
Test name
Test status
Simulation time 141075489 ps
CPU time 1.91 seconds
Started Aug 28 10:31:07 PM UTC 24
Finished Aug 28 10:31:10 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205753
233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.3205753233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.1711093782
Short name T790
Test name
Test status
Simulation time 1053784198 ps
CPU time 9.74 seconds
Started Aug 28 10:30:46 PM UTC 24
Finished Aug 28 10:30:57 PM UTC 24
Peak memory 233260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171109
3782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.1711093782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.1181725653
Short name T806
Test name
Test status
Simulation time 6041497919 ps
CPU time 27.88 seconds
Started Aug 28 10:30:47 PM UTC 24
Finished Aug 28 10:31:16 PM UTC 24
Peak memory 833956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1181725653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.1181725653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.3224531090
Short name T809
Test name
Test status
Simulation time 7509647319 ps
CPU time 4.85 seconds
Started Aug 28 10:31:11 PM UTC 24
Finished Aug 28 10:31:17 PM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224531
090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.3224531090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.2303831413
Short name T808
Test name
Test status
Simulation time 464224643 ps
CPU time 4.53 seconds
Started Aug 28 10:31:11 PM UTC 24
Finished Aug 28 10:31:17 PM UTC 24
Peak memory 216660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303831
413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_ad
dr.2303831413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.3792682811
Short name T805
Test name
Test status
Simulation time 1126385704 ps
CPU time 2.28 seconds
Started Aug 28 10:31:12 PM UTC 24
Finished Aug 28 10:31:16 PM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792682
811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.3792682811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_perf.3604533317
Short name T797
Test name
Test status
Simulation time 5503441875 ps
CPU time 9.46 seconds
Started Aug 28 10:30:58 PM UTC 24
Finished Aug 28 10:31:08 PM UTC 24
Peak memory 233616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604533
317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.3604533317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.4275981565
Short name T803
Test name
Test status
Simulation time 956228642 ps
CPU time 3.63 seconds
Started Aug 28 10:31:09 PM UTC 24
Finished Aug 28 10:31:14 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275981
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.4275981565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.68530059
Short name T789
Test name
Test status
Simulation time 3417223783 ps
CPU time 13.48 seconds
Started Aug 28 10:30:42 PM UTC 24
Finished Aug 28 10:30:56 PM UTC 24
Peak memory 227208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68530059 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.68530059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.967067380
Short name T756
Test name
Test status
Simulation time 7635573715 ps
CPU time 37.88 seconds
Started Aug 28 10:30:59 PM UTC 24
Finished Aug 28 10:31:38 PM UTC 24
Peak memory 381336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967067
380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.967067380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.1763317532
Short name T802
Test name
Test status
Simulation time 3555150282 ps
CPU time 28.15 seconds
Started Aug 28 10:30:44 PM UTC 24
Finished Aug 28 10:31:14 PM UTC 24
Peak memory 216680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763317532 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.1763317532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.3461441550
Short name T1461
Test name
Test status
Simulation time 50514683732 ps
CPU time 813.8 seconds
Started Aug 28 10:30:44 PM UTC 24
Finished Aug 28 10:44:26 PM UTC 24
Peak memory 7186588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461441550 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.3461441550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.1039457584
Short name T787
Test name
Test status
Simulation time 2316277534 ps
CPU time 8.04 seconds
Started Aug 28 10:30:45 PM UTC 24
Finished Aug 28 10:30:54 PM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039457584 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.1039457584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.2822570887
Short name T795
Test name
Test status
Simulation time 3873907895 ps
CPU time 11.37 seconds
Started Aug 28 10:30:53 PM UTC 24
Finished Aug 28 10:31:06 PM UTC 24
Peak memory 227000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822570
887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.2822570887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2073338567
Short name T801
Test name
Test status
Simulation time 151925724 ps
CPU time 4.6 seconds
Started Aug 28 10:31:07 PM UTC 24
Finished Aug 28 10:31:13 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073338
567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2073338567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_alert_test.3159823749
Short name T836
Test name
Test status
Simulation time 33396469 ps
CPU time 0.78 seconds
Started Aug 28 10:32:01 PM UTC 24
Finished Aug 28 10:32:03 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159823749 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3159823749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.785139736
Short name T814
Test name
Test status
Simulation time 227058978 ps
CPU time 6.87 seconds
Started Aug 28 10:31:18 PM UTC 24
Finished Aug 28 10:31:26 PM UTC 24
Peak memory 260116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785139736 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.785139736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.1997401979
Short name T890
Test name
Test status
Simulation time 23947425482 ps
CPU time 115.59 seconds
Started Aug 28 10:31:18 PM UTC 24
Finished Aug 28 10:33:16 PM UTC 24
Peak memory 432540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997401979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1997401979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.2610938056
Short name T873
Test name
Test status
Simulation time 2389974950 ps
CPU time 84.94 seconds
Started Aug 28 10:31:17 PM UTC 24
Finished Aug 28 10:32:44 PM UTC 24
Peak memory 800736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610938056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2610938056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.3298114066
Short name T811
Test name
Test status
Simulation time 92497667 ps
CPU time 1.53 seconds
Started Aug 28 10:31:17 PM UTC 24
Finished Aug 28 10:31:19 PM UTC 24
Peak memory 213992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298114066 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.3298114066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.3644160413
Short name T817
Test name
Test status
Simulation time 526337486 ps
CPU time 9.55 seconds
Started Aug 28 10:31:18 PM UTC 24
Finished Aug 28 10:31:29 PM UTC 24
Peak memory 239944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644160413 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.3644160413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.2378355710
Short name T1103
Test name
Test status
Simulation time 33747311279 ps
CPU time 345.14 seconds
Started Aug 28 10:31:16 PM UTC 24
Finished Aug 28 10:37:06 PM UTC 24
Peak memory 1511608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378355710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2378355710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.492241475
Short name T830
Test name
Test status
Simulation time 829319467 ps
CPU time 9.2 seconds
Started Aug 28 10:31:50 PM UTC 24
Finished Aug 28 10:32:00 PM UTC 24
Peak memory 216784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492241475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.492241475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_override.3421977257
Short name T807
Test name
Test status
Simulation time 47880153 ps
CPU time 1 seconds
Started Aug 28 10:31:15 PM UTC 24
Finished Aug 28 10:31:17 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421977257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3421977257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_perf.2357828517
Short name T917
Test name
Test status
Simulation time 12857469120 ps
CPU time 142.43 seconds
Started Aug 28 10:31:18 PM UTC 24
Finished Aug 28 10:33:43 PM UTC 24
Peak memory 216952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357828517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2357828517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.3886035684
Short name T813
Test name
Test status
Simulation time 74857243 ps
CPU time 2.31 seconds
Started Aug 28 10:31:20 PM UTC 24
Finished Aug 28 10:31:23 PM UTC 24
Peak memory 226704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886035684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3886035684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.676530108
Short name T839
Test name
Test status
Simulation time 4139607345 ps
CPU time 47.63 seconds
Started Aug 28 10:31:15 PM UTC 24
Finished Aug 28 10:32:04 PM UTC 24
Peak memory 448740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676530108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.676530108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_stress_all.225530294
Short name T1222
Test name
Test status
Simulation time 12789201949 ps
CPU time 481.74 seconds
Started Aug 28 10:31:26 PM UTC 24
Finished Aug 28 10:39:34 PM UTC 24
Peak memory 2695700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225530294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.225530294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.2553082899
Short name T831
Test name
Test status
Simulation time 814718156 ps
CPU time 35.04 seconds
Started Aug 28 10:31:24 PM UTC 24
Finished Aug 28 10:32:01 PM UTC 24
Peak memory 233584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553082899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2553082899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.1562254260
Short name T828
Test name
Test status
Simulation time 7763180675 ps
CPU time 10.64 seconds
Started Aug 28 10:31:45 PM UTC 24
Finished Aug 28 10:31:57 PM UTC 24
Peak memory 233808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1562254260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_ad
dr.1562254260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.2031901105
Short name T821
Test name
Test status
Simulation time 224730490 ps
CPU time 2.5 seconds
Started Aug 28 10:31:42 PM UTC 24
Finished Aug 28 10:31:46 PM UTC 24
Peak memory 217900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031901
105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.2031901105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.1071571159
Short name T820
Test name
Test status
Simulation time 1462850360 ps
CPU time 1.18 seconds
Started Aug 28 10:31:42 PM UTC 24
Finished Aug 28 10:31:44 PM UTC 24
Peak memory 215172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071571
159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.1071571159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.3501559044
Short name T829
Test name
Test status
Simulation time 2304771929 ps
CPU time 6.05 seconds
Started Aug 28 10:31:53 PM UTC 24
Finished Aug 28 10:32:00 PM UTC 24
Peak memory 216976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501559
044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermar
ks_acq.3501559044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.2532435304
Short name T827
Test name
Test status
Simulation time 371779980 ps
CPU time 2.8 seconds
Started Aug 28 10:31:53 PM UTC 24
Finished Aug 28 10:31:56 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532435
304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_tx.2532435304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_hrst.3236595620
Short name T823
Test name
Test status
Simulation time 598807447 ps
CPU time 3.9 seconds
Started Aug 28 10:31:46 PM UTC 24
Finished Aug 28 10:31:51 PM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236595
620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.3236595620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.2117138771
Short name T825
Test name
Test status
Simulation time 1316308809 ps
CPU time 10.17 seconds
Started Aug 28 10:31:41 PM UTC 24
Finished Aug 28 10:31:52 PM UTC 24
Peak memory 227068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211713
8771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.2117138771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.2993768029
Short name T959
Test name
Test status
Simulation time 10472875413 ps
CPU time 154.22 seconds
Started Aug 28 10:31:42 PM UTC 24
Finished Aug 28 10:34:19 PM UTC 24
Peak memory 2744540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2993768029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.2993768029
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.8285416
Short name T833
Test name
Test status
Simulation time 1841616310 ps
CPU time 4.2 seconds
Started Aug 28 10:31:57 PM UTC 24
Finished Aug 28 10:32:02 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8285416
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.8285416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.3326428689
Short name T838
Test name
Test status
Simulation time 1648750924 ps
CPU time 4.7 seconds
Started Aug 28 10:31:58 PM UTC 24
Finished Aug 28 10:32:04 PM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326428
689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_ad
dr.3326428689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.69846668
Short name T837
Test name
Test status
Simulation time 525310636 ps
CPU time 2.45 seconds
Started Aug 28 10:32:00 PM UTC 24
Finished Aug 28 10:32:03 PM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6984666
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.69846668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_perf.2559076115
Short name T822
Test name
Test status
Simulation time 1371253124 ps
CPU time 4.94 seconds
Started Aug 28 10:31:42 PM UTC 24
Finished Aug 28 10:31:48 PM UTC 24
Peak memory 233668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559076
115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.2559076115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.650799785
Short name T832
Test name
Test status
Simulation time 604137073 ps
CPU time 3.92 seconds
Started Aug 28 10:31:57 PM UTC 24
Finished Aug 28 10:32:02 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6507997
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.650799785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.4258889061
Short name T842
Test name
Test status
Simulation time 4186983387 ps
CPU time 36.53 seconds
Started Aug 28 10:31:28 PM UTC 24
Finished Aug 28 10:32:07 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258889061 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.4258889061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.4041062505
Short name T922
Test name
Test status
Simulation time 14696377043 ps
CPU time 123.43 seconds
Started Aug 28 10:31:43 PM UTC 24
Finished Aug 28 10:33:49 PM UTC 24
Peak memory 1445996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404106
2505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.4041062505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.937662715
Short name T726
Test name
Test status
Simulation time 590434879 ps
CPU time 7.54 seconds
Started Aug 28 10:31:30 PM UTC 24
Finished Aug 28 10:31:39 PM UTC 24
Peak memory 216876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937662715 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.937662715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.3748754094
Short name T1001
Test name
Test status
Simulation time 30733574280 ps
CPU time 212.15 seconds
Started Aug 28 10:31:30 PM UTC 24
Finished Aug 28 10:35:06 PM UTC 24
Peak memory 2730208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748754094 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.3748754094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.2528415018
Short name T819
Test name
Test status
Simulation time 2822328934 ps
CPU time 6.2 seconds
Started Aug 28 10:31:30 PM UTC 24
Finished Aug 28 10:31:38 PM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528415018 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.2528415018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.3424019951
Short name T826
Test name
Test status
Simulation time 2902348501 ps
CPU time 13.03 seconds
Started Aug 28 10:31:42 PM UTC 24
Finished Aug 28 10:31:56 PM UTC 24
Peak memory 227104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424019
951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.3424019951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1259736484
Short name T835
Test name
Test status
Simulation time 330319189 ps
CPU time 7.86 seconds
Started Aug 28 10:31:54 PM UTC 24
Finished Aug 28 10:32:03 PM UTC 24
Peak memory 218828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259736
484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1259736484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_alert_test.2609759292
Short name T870
Test name
Test status
Simulation time 30314937 ps
CPU time 0.97 seconds
Started Aug 28 10:32:39 PM UTC 24
Finished Aug 28 10:32:41 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609759292 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2609759292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.2737407801
Short name T844
Test name
Test status
Simulation time 590872446 ps
CPU time 4.95 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:32:11 PM UTC 24
Peak memory 250204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737407801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2737407801
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.2531649772
Short name T848
Test name
Test status
Simulation time 251908645 ps
CPU time 15.4 seconds
Started Aug 28 10:32:03 PM UTC 24
Finished Aug 28 10:32:20 PM UTC 24
Peak memory 266316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531649772 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.2531649772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.3413489786
Short name T1010
Test name
Test status
Simulation time 6793333985 ps
CPU time 191.64 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:35:19 PM UTC 24
Peak memory 391364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413489786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.3413489786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.181789232
Short name T891
Test name
Test status
Simulation time 9651914635 ps
CPU time 71.65 seconds
Started Aug 28 10:32:03 PM UTC 24
Finished Aug 28 10:33:17 PM UTC 24
Peak memory 669912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181789232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.181789232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.871566346
Short name T841
Test name
Test status
Simulation time 99730729 ps
CPU time 1.41 seconds
Started Aug 28 10:32:03 PM UTC 24
Finished Aug 28 10:32:06 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871566346 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.871566346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.3689433775
Short name T845
Test name
Test status
Simulation time 207351278 ps
CPU time 6.19 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:32:12 PM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689433775 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.3689433775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.2782714618
Short name T920
Test name
Test status
Simulation time 3407326715 ps
CPU time 99.86 seconds
Started Aug 28 10:32:03 PM UTC 24
Finished Aug 28 10:33:45 PM UTC 24
Peak memory 1059224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782714618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2782714618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.333552983
Short name T263
Test name
Test status
Simulation time 1485249335 ps
CPU time 18.88 seconds
Started Aug 28 10:32:30 PM UTC 24
Finished Aug 28 10:32:50 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333552983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.333552983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_override.2329513068
Short name T156
Test name
Test status
Simulation time 48240174 ps
CPU time 1.04 seconds
Started Aug 28 10:32:02 PM UTC 24
Finished Aug 28 10:32:04 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329513068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2329513068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_perf.3549379447
Short name T851
Test name
Test status
Simulation time 1329984853 ps
CPU time 18.44 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:32:24 PM UTC 24
Peak memory 262540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549379447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3549379447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.1100172595
Short name T947
Test name
Test status
Simulation time 24778107621 ps
CPU time 115.02 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:34:02 PM UTC 24
Peak memory 774280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100172595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1100172595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.775686043
Short name T884
Test name
Test status
Simulation time 5276582151 ps
CPU time 61.37 seconds
Started Aug 28 10:32:02 PM UTC 24
Finished Aug 28 10:33:05 PM UTC 24
Peak memory 379456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775686043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.775686043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.898976719
Short name T858
Test name
Test status
Simulation time 2290320455 ps
CPU time 25.25 seconds
Started Aug 28 10:32:05 PM UTC 24
Finished Aug 28 10:32:31 PM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898976719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.898976719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.1167415303
Short name T866
Test name
Test status
Simulation time 4851743168 ps
CPU time 10.53 seconds
Started Aug 28 10:32:27 PM UTC 24
Finished Aug 28 10:32:38 PM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1167415303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_ad
dr.1167415303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.3949299420
Short name T854
Test name
Test status
Simulation time 188723361 ps
CPU time 1.74 seconds
Started Aug 28 10:32:24 PM UTC 24
Finished Aug 28 10:32:26 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949299
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.3949299420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.2400730716
Short name T857
Test name
Test status
Simulation time 280886037 ps
CPU time 2.95 seconds
Started Aug 28 10:32:26 PM UTC 24
Finished Aug 28 10:32:30 PM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400730
716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.2400730716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.3198327247
Short name T864
Test name
Test status
Simulation time 332886455 ps
CPU time 3.25 seconds
Started Aug 28 10:32:32 PM UTC 24
Finished Aug 28 10:32:36 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198327
247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermar
ks_acq.3198327247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1198208326
Short name T863
Test name
Test status
Simulation time 172090431 ps
CPU time 1.94 seconds
Started Aug 28 10:32:33 PM UTC 24
Finished Aug 28 10:32:36 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198208
326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.1198208326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1008539500
Short name T855
Test name
Test status
Simulation time 4490992078 ps
CPU time 8.43 seconds
Started Aug 28 10:32:17 PM UTC 24
Finished Aug 28 10:32:27 PM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100853
9500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.1008539500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.1562133549
Short name T988
Test name
Test status
Simulation time 24594030573 ps
CPU time 157.33 seconds
Started Aug 28 10:32:19 PM UTC 24
Finished Aug 28 10:34:59 PM UTC 24
Peak memory 2883972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1562133549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stres
s_wr.1562133549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.1220530828
Short name T868
Test name
Test status
Simulation time 1223779531 ps
CPU time 4.84 seconds
Started Aug 28 10:32:34 PM UTC 24
Finished Aug 28 10:32:40 PM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220530
828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.1220530828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.3237843199
Short name T872
Test name
Test status
Simulation time 621462719 ps
CPU time 4.98 seconds
Started Aug 28 10:32:38 PM UTC 24
Finished Aug 28 10:32:44 PM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237843
199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_ad
dr.3237843199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_nack_txstretch.1882953724
Short name T869
Test name
Test status
Simulation time 130746321 ps
CPU time 2.04 seconds
Started Aug 28 10:32:38 PM UTC 24
Finished Aug 28 10:32:41 PM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882953
724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_txstretch.1882953724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_perf.4203808170
Short name T859
Test name
Test status
Simulation time 2425240279 ps
CPU time 5.78 seconds
Started Aug 28 10:32:26 PM UTC 24
Finished Aug 28 10:32:33 PM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203808
170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.4203808170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.2059740793
Short name T867
Test name
Test status
Simulation time 503350033 ps
CPU time 3.94 seconds
Started Aug 28 10:32:34 PM UTC 24
Finished Aug 28 10:32:39 PM UTC 24
Peak memory 216556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059740
793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.2059740793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.50549527
Short name T850
Test name
Test status
Simulation time 869636390 ps
CPU time 13.9 seconds
Started Aug 28 10:32:08 PM UTC 24
Finished Aug 28 10:32:23 PM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50549527 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.50549527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.2723264959
Short name T925
Test name
Test status
Simulation time 75284281336 ps
CPU time 83.87 seconds
Started Aug 28 10:32:26 PM UTC 24
Finished Aug 28 10:33:52 PM UTC 24
Peak memory 287152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272326
4959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.2723264959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.485858432
Short name T860
Test name
Test status
Simulation time 1771599707 ps
CPU time 19.47 seconds
Started Aug 28 10:32:12 PM UTC 24
Finished Aug 28 10:32:33 PM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485858432 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.485858432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.973933186
Short name T1314
Test name
Test status
Simulation time 42643440614 ps
CPU time 552.8 seconds
Started Aug 28 10:32:08 PM UTC 24
Finished Aug 28 10:41:27 PM UTC 24
Peak memory 5843164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973933186 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.973933186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.58998222
Short name T856
Test name
Test status
Simulation time 3300726217 ps
CPU time 15.07 seconds
Started Aug 28 10:32:12 PM UTC 24
Finished Aug 28 10:32:28 PM UTC 24
Peak memory 313548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58998222 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.58998222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.1419982936
Short name T862
Test name
Test status
Simulation time 5848119905 ps
CPU time 12.18 seconds
Started Aug 28 10:32:20 PM UTC 24
Finished Aug 28 10:32:34 PM UTC 24
Peak memory 244128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419982
936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.1419982936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.1659372947
Short name T865
Test name
Test status
Simulation time 107159778 ps
CPU time 3.58 seconds
Started Aug 28 10:32:33 PM UTC 24
Finished Aug 28 10:32:38 PM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659372
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1659372947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_alert_test.4280550416
Short name T900
Test name
Test status
Simulation time 42433295 ps
CPU time 0.99 seconds
Started Aug 28 10:33:26 PM UTC 24
Finished Aug 28 10:33:28 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280550416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.4280550416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.119518070
Short name T882
Test name
Test status
Simulation time 144927170 ps
CPU time 4.23 seconds
Started Aug 28 10:32:56 PM UTC 24
Finished Aug 28 10:33:01 PM UTC 24
Peak memory 248172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119518070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.119518070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.314805331
Short name T876
Test name
Test status
Simulation time 160704841 ps
CPU time 10.38 seconds
Started Aug 28 10:32:43 PM UTC 24
Finished Aug 28 10:32:54 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314805331 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.314805331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.331151654
Short name T1044
Test name
Test status
Simulation time 3254105566 ps
CPU time 189.88 seconds
Started Aug 28 10:32:44 PM UTC 24
Finished Aug 28 10:35:57 PM UTC 24
Peak memory 459024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331151654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.331151654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.3081001047
Short name T824
Test name
Test status
Simulation time 2853862974 ps
CPU time 41.84 seconds
Started Aug 28 10:32:42 PM UTC 24
Finished Aug 28 10:33:25 PM UTC 24
Peak memory 569484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081001047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3081001047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.69428762
Short name T874
Test name
Test status
Simulation time 230615619 ps
CPU time 1.44 seconds
Started Aug 28 10:32:42 PM UTC 24
Finished Aug 28 10:32:44 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69428762 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.69428762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.808046753
Short name T875
Test name
Test status
Simulation time 115530250 ps
CPU time 4.84 seconds
Started Aug 28 10:32:44 PM UTC 24
Finished Aug 28 10:32:50 PM UTC 24
Peak memory 231536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808046753 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.808046753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.2842490425
Short name T123
Test name
Test status
Simulation time 9948102923 ps
CPU time 117.52 seconds
Started Aug 28 10:32:41 PM UTC 24
Finished Aug 28 10:34:41 PM UTC 24
Peak memory 1407176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842490425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2842490425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.694003544
Short name T908
Test name
Test status
Simulation time 899410555 ps
CPU time 7.6 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:33 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694003544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.694003544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_override.172077355
Short name T871
Test name
Test status
Simulation time 27236336 ps
CPU time 1.06 seconds
Started Aug 28 10:32:40 PM UTC 24
Finished Aug 28 10:32:42 PM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172077355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.172077355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_perf.3559644988
Short name T897
Test name
Test status
Simulation time 7676372524 ps
CPU time 38.35 seconds
Started Aug 28 10:32:45 PM UTC 24
Finished Aug 28 10:33:25 PM UTC 24
Peak memory 512160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559644988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3559644988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.1429819656
Short name T877
Test name
Test status
Simulation time 167637469 ps
CPU time 3.93 seconds
Started Aug 28 10:32:50 PM UTC 24
Finished Aug 28 10:32:55 PM UTC 24
Peak memory 237036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429819656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1429819656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.2713495117
Short name T885
Test name
Test status
Simulation time 1778151099 ps
CPU time 28.5 seconds
Started Aug 28 10:32:40 PM UTC 24
Finished Aug 28 10:33:10 PM UTC 24
Peak memory 331976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713495117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2713495117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.2029506081
Short name T893
Test name
Test status
Simulation time 986584871 ps
CPU time 28.63 seconds
Started Aug 28 10:32:51 PM UTC 24
Finished Aug 28 10:33:21 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029506081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2029506081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.3052064641
Short name T909
Test name
Test status
Simulation time 1942419487 ps
CPU time 9.08 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:34 PM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3052064641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.3052064641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.3084331473
Short name T886
Test name
Test status
Simulation time 319127789 ps
CPU time 1.53 seconds
Started Aug 28 10:33:10 PM UTC 24
Finished Aug 28 10:33:13 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084331
473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.3084331473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.2778039448
Short name T887
Test name
Test status
Simulation time 183549591 ps
CPU time 1.08 seconds
Started Aug 28 10:33:11 PM UTC 24
Finished Aug 28 10:33:14 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778039
448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.2778039448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.137933530
Short name T902
Test name
Test status
Simulation time 1119835928 ps
CPU time 3.39 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:28 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379335
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_acq.137933530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.3424511900
Short name T898
Test name
Test status
Simulation time 130843297 ps
CPU time 1.67 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:27 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424511
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.3424511900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.3440053347
Short name T888
Test name
Test status
Simulation time 4328356350 ps
CPU time 10.56 seconds
Started Aug 28 10:33:02 PM UTC 24
Finished Aug 28 10:33:15 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344005
3347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.3440053347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.2930207858
Short name T911
Test name
Test status
Simulation time 12181594685 ps
CPU time 30.98 seconds
Started Aug 28 10:33:04 PM UTC 24
Finished Aug 28 10:33:37 PM UTC 24
Peak memory 733396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2930207858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.2930207858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.843223359
Short name T906
Test name
Test status
Simulation time 970365839 ps
CPU time 5.03 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:30 PM UTC 24
Peak memory 226820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8432233
59 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.843223359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.468985551
Short name T905
Test name
Test status
Simulation time 2180445303 ps
CPU time 4.88 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:30 PM UTC 24
Peak memory 216728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4689855
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.468985551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.600900427
Short name T901
Test name
Test status
Simulation time 169681562 ps
CPU time 2.09 seconds
Started Aug 28 10:33:25 PM UTC 24
Finished Aug 28 10:33:28 PM UTC 24
Peak memory 233532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6009004
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_txstretch.600900427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_perf.2514191842
Short name T895
Test name
Test status
Simulation time 2930158768 ps
CPU time 8.47 seconds
Started Aug 28 10:33:14 PM UTC 24
Finished Aug 28 10:33:23 PM UTC 24
Peak memory 222788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514191
842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.2514191842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.3042388953
Short name T903
Test name
Test status
Simulation time 424709742 ps
CPU time 3.34 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:29 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042388
953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.3042388953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.2266455832
Short name T889
Test name
Test status
Simulation time 6917601407 ps
CPU time 16.4 seconds
Started Aug 28 10:32:58 PM UTC 24
Finished Aug 28 10:33:15 PM UTC 24
Peak memory 233880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266455832 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.2266455832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.1047497173
Short name T1037
Test name
Test status
Simulation time 12496782533 ps
CPU time 149.13 seconds
Started Aug 28 10:33:15 PM UTC 24
Finished Aug 28 10:35:47 PM UTC 24
Peak memory 1421468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104749
7173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.1047497173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.3624200900
Short name T896
Test name
Test status
Simulation time 620061522 ps
CPU time 23.13 seconds
Started Aug 28 10:32:59 PM UTC 24
Finished Aug 28 10:33:23 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624200900 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.3624200900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.3785629265
Short name T1290
Test name
Test status
Simulation time 40253890952 ps
CPU time 482.17 seconds
Started Aug 28 10:32:59 PM UTC 24
Finished Aug 28 10:41:07 PM UTC 24
Peak memory 5345500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785629265 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.3785629265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.768372221
Short name T910
Test name
Test status
Simulation time 2876952151 ps
CPU time 34.34 seconds
Started Aug 28 10:33:00 PM UTC 24
Finished Aug 28 10:33:36 PM UTC 24
Peak memory 579712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768372221 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.768372221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.838570204
Short name T892
Test name
Test status
Simulation time 2717231804 ps
CPU time 11.74 seconds
Started Aug 28 10:33:05 PM UTC 24
Finished Aug 28 10:33:18 PM UTC 24
Peak memory 231080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8385702
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.838570204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.3437898296
Short name T899
Test name
Test status
Simulation time 78027742 ps
CPU time 3.06 seconds
Started Aug 28 10:33:24 PM UTC 24
Finished Aug 28 10:33:28 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437898
296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3437898296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_alert_test.327893590
Short name T936
Test name
Test status
Simulation time 35589051 ps
CPU time 0.97 seconds
Started Aug 28 10:33:54 PM UTC 24
Finished Aug 28 10:33:56 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327893590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.327893590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.2387028154
Short name T912
Test name
Test status
Simulation time 87860829 ps
CPU time 2.34 seconds
Started Aug 28 10:33:33 PM UTC 24
Finished Aug 28 10:33:37 PM UTC 24
Peak memory 233652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387028154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2387028154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.2635488164
Short name T916
Test name
Test status
Simulation time 1089833880 ps
CPU time 9.91 seconds
Started Aug 28 10:33:30 PM UTC 24
Finished Aug 28 10:33:41 PM UTC 24
Peak memory 297240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635488164 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.2635488164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.324316894
Short name T1012
Test name
Test status
Simulation time 11750721186 ps
CPU time 108.84 seconds
Started Aug 28 10:33:31 PM UTC 24
Finished Aug 28 10:35:22 PM UTC 24
Peak memory 727324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324316894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.324316894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.14459683
Short name T1064
Test name
Test status
Simulation time 10500844363 ps
CPU time 168.29 seconds
Started Aug 28 10:33:30 PM UTC 24
Finished Aug 28 10:36:21 PM UTC 24
Peak memory 786660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14459683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.14459683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.3976706404
Short name T907
Test name
Test status
Simulation time 103249358 ps
CPU time 1.55 seconds
Started Aug 28 10:33:30 PM UTC 24
Finished Aug 28 10:33:32 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976706404 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.3976706404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.3507747780
Short name T915
Test name
Test status
Simulation time 1524595822 ps
CPU time 7.67 seconds
Started Aug 28 10:33:31 PM UTC 24
Finished Aug 28 10:33:40 PM UTC 24
Peak memory 258184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507747780 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.3507747780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.3656919610
Short name T124
Test name
Test status
Simulation time 11433997544 ps
CPU time 122.68 seconds
Started Aug 28 10:33:30 PM UTC 24
Finished Aug 28 10:35:35 PM UTC 24
Peak memory 1620412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656919610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3656919610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.876398898
Short name T941
Test name
Test status
Simulation time 348745135 ps
CPU time 7.09 seconds
Started Aug 28 10:33:50 PM UTC 24
Finished Aug 28 10:33:58 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876398898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.876398898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_mode_toggle.4138470207
Short name T928
Test name
Test status
Simulation time 101242120 ps
CPU time 3.35 seconds
Started Aug 28 10:33:48 PM UTC 24
Finished Aug 28 10:33:53 PM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138470207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.4138470207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_override.3347884886
Short name T157
Test name
Test status
Simulation time 116722844 ps
CPU time 0.82 seconds
Started Aug 28 10:33:29 PM UTC 24
Finished Aug 28 10:33:30 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347884886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3347884886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_perf.2256052822
Short name T1096
Test name
Test status
Simulation time 12668171717 ps
CPU time 197.26 seconds
Started Aug 28 10:33:31 PM UTC 24
Finished Aug 28 10:36:51 PM UTC 24
Peak memory 1767672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256052822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2256052822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.2625214718
Short name T949
Test name
Test status
Simulation time 2663576427 ps
CPU time 34.05 seconds
Started Aug 28 10:33:31 PM UTC 24
Finished Aug 28 10:34:07 PM UTC 24
Peak memory 237332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625214718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.2625214718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.383272193
Short name T950
Test name
Test status
Simulation time 4000234946 ps
CPU time 40.12 seconds
Started Aug 28 10:33:28 PM UTC 24
Finished Aug 28 10:34:09 PM UTC 24
Peak memory 354560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383272193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.383272193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.864409095
Short name T929
Test name
Test status
Simulation time 3663811061 ps
CPU time 20.51 seconds
Started Aug 28 10:33:31 PM UTC 24
Finished Aug 28 10:33:53 PM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864409095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.864409095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.1889665878
Short name T934
Test name
Test status
Simulation time 4378331012 ps
CPU time 9.04 seconds
Started Aug 28 10:33:45 PM UTC 24
Finished Aug 28 10:33:56 PM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1889665878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.1889665878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.1981870977
Short name T919
Test name
Test status
Simulation time 166008857 ps
CPU time 1.86 seconds
Started Aug 28 10:33:42 PM UTC 24
Finished Aug 28 10:33:45 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981870
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.1981870977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.415143147
Short name T921
Test name
Test status
Simulation time 238732940 ps
CPU time 2.81 seconds
Started Aug 28 10:33:44 PM UTC 24
Finished Aug 28 10:33:48 PM UTC 24
Peak memory 216620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151431
47 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.415143147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.73951145
Short name T932
Test name
Test status
Simulation time 290014464 ps
CPU time 2.92 seconds
Started Aug 28 10:33:51 PM UTC 24
Finished Aug 28 10:33:55 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7395114
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermarks
_acq.73951145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.3530817845
Short name T930
Test name
Test status
Simulation time 292475786 ps
CPU time 2.05 seconds
Started Aug 28 10:33:51 PM UTC 24
Finished Aug 28 10:33:54 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530817
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.3530817845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.4122600234
Short name T926
Test name
Test status
Simulation time 6121391173 ps
CPU time 12.96 seconds
Started Aug 28 10:33:38 PM UTC 24
Finished Aug 28 10:33:52 PM UTC 24
Peak memory 233728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412260
0234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.4122600234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.3916133703
Short name T933
Test name
Test status
Simulation time 9630628596 ps
CPU time 14.99 seconds
Started Aug 28 10:33:39 PM UTC 24
Finished Aug 28 10:33:55 PM UTC 24
Peak memory 246176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3916133703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres
s_wr.3916133703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.3091288827
Short name T943
Test name
Test status
Simulation time 503992844 ps
CPU time 4.64 seconds
Started Aug 28 10:33:53 PM UTC 24
Finished Aug 28 10:33:59 PM UTC 24
Peak memory 227080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091288
827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.3091288827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.1763904668
Short name T938
Test name
Test status
Simulation time 2193727278 ps
CPU time 3.4 seconds
Started Aug 28 10:33:53 PM UTC 24
Finished Aug 28 10:33:57 PM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763904
668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad
dr.1763904668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.2299476603
Short name T939
Test name
Test status
Simulation time 1267265853 ps
CPU time 2.47 seconds
Started Aug 28 10:33:54 PM UTC 24
Finished Aug 28 10:33:58 PM UTC 24
Peak memory 233540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299476
603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_txstretch.2299476603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_perf.992653561
Short name T931
Test name
Test status
Simulation time 1923761900 ps
CPU time 9.01 seconds
Started Aug 28 10:33:44 PM UTC 24
Finished Aug 28 10:33:54 PM UTC 24
Peak memory 233808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9926535
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.992653561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1410706407
Short name T942
Test name
Test status
Simulation time 1853111772 ps
CPU time 3.89 seconds
Started Aug 28 10:33:53 PM UTC 24
Finished Aug 28 10:33:58 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410706
407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.1410706407
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.3552457874
Short name T923
Test name
Test status
Simulation time 1405139133 ps
CPU time 14.76 seconds
Started Aug 28 10:33:33 PM UTC 24
Finished Aug 28 10:33:50 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552457874 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.3552457874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.2506644146
Short name T1350
Test name
Test status
Simulation time 36000511881 ps
CPU time 512.98 seconds
Started Aug 28 10:33:45 PM UTC 24
Finished Aug 28 10:42:24 PM UTC 24
Peak memory 5240992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250664
4146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.2506644146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3869589086
Short name T946
Test name
Test status
Simulation time 1215819119 ps
CPU time 23.85 seconds
Started Aug 28 10:33:37 PM UTC 24
Finished Aug 28 10:34:02 PM UTC 24
Peak memory 233788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869589086 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.3869589086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.4130703178
Short name T852
Test name
Test status
Simulation time 39363745072 ps
CPU time 60.55 seconds
Started Aug 28 10:33:35 PM UTC 24
Finished Aug 28 10:34:37 PM UTC 24
Peak memory 1261792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130703178 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.4130703178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.3865042326
Short name T918
Test name
Test status
Simulation time 1103668884 ps
CPU time 5.74 seconds
Started Aug 28 10:33:38 PM UTC 24
Finished Aug 28 10:33:44 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865042326 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.3865042326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.2488983735
Short name T924
Test name
Test status
Simulation time 2420885733 ps
CPU time 10.26 seconds
Started Aug 28 10:33:39 PM UTC 24
Finished Aug 28 10:33:50 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488983
735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.2488983735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.1689685885
Short name T935
Test name
Test status
Simulation time 145307647 ps
CPU time 3.98 seconds
Started Aug 28 10:33:51 PM UTC 24
Finished Aug 28 10:33:56 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689685
885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.1689685885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_alert_test.695932804
Short name T964
Test name
Test status
Simulation time 28419353 ps
CPU time 1.02 seconds
Started Aug 28 10:34:22 PM UTC 24
Finished Aug 28 10:34:24 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695932804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.695932804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.4207584585
Short name T24
Test name
Test status
Simulation time 173596539 ps
CPU time 3.27 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:34:03 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207584585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.4207584585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2387082974
Short name T954
Test name
Test status
Simulation time 3457792637 ps
CPU time 18.43 seconds
Started Aug 28 10:33:56 PM UTC 24
Finished Aug 28 10:34:16 PM UTC 24
Peak memory 289024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387082974 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.2387082974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.3219930558
Short name T1158
Test name
Test status
Simulation time 10702262916 ps
CPU time 251.51 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:38:14 PM UTC 24
Peak memory 788660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219930558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3219930558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.3995933384
Short name T976
Test name
Test status
Simulation time 5859709906 ps
CPU time 48.66 seconds
Started Aug 28 10:33:56 PM UTC 24
Finished Aug 28 10:34:47 PM UTC 24
Peak memory 489612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995933384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3995933384
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.3619932027
Short name T944
Test name
Test status
Simulation time 155641320 ps
CPU time 1.39 seconds
Started Aug 28 10:33:56 PM UTC 24
Finished Aug 28 10:33:59 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619932027 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.3619932027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.2311812653
Short name T951
Test name
Test status
Simulation time 757014468 ps
CPU time 12.87 seconds
Started Aug 28 10:33:56 PM UTC 24
Finished Aug 28 10:34:10 PM UTC 24
Peak memory 254024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311812653 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.2311812653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.534461557
Short name T981
Test name
Test status
Simulation time 16992420454 ps
CPU time 119.67 seconds
Started Aug 28 10:33:55 PM UTC 24
Finished Aug 28 10:35:57 PM UTC 24
Peak memory 1196304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534461557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.534461557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1290115962
Short name T940
Test name
Test status
Simulation time 526412844 ps
CPU time 10.28 seconds
Started Aug 28 10:34:17 PM UTC 24
Finished Aug 28 10:34:29 PM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290115962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1290115962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_override.3682958142
Short name T937
Test name
Test status
Simulation time 50421843 ps
CPU time 1.07 seconds
Started Aug 28 10:33:55 PM UTC 24
Finished Aug 28 10:33:57 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682958142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3682958142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2277278807
Short name T1169
Test name
Test status
Simulation time 26005337172 ps
CPU time 268.44 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:38:32 PM UTC 24
Peak memory 1122332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277278807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2277278807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.49195303
Short name T948
Test name
Test status
Simulation time 115587236 ps
CPU time 2.99 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:34:03 PM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49195303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.49195303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.1438703176
Short name T973
Test name
Test status
Simulation time 2273718657 ps
CPU time 46.85 seconds
Started Aug 28 10:33:54 PM UTC 24
Finished Aug 28 10:34:42 PM UTC 24
Peak memory 446716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438703176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1438703176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_stress_all.4279808812
Short name T261
Test name
Test status
Simulation time 139825688940 ps
CPU time 258.07 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:38:21 PM UTC 24
Peak memory 1640712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279808812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.4279808812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.3520045420
Short name T962
Test name
Test status
Simulation time 931768406 ps
CPU time 21.07 seconds
Started Aug 28 10:33:59 PM UTC 24
Finished Aug 28 10:34:21 PM UTC 24
Peak memory 233184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520045420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3520045420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.3783144502
Short name T968
Test name
Test status
Simulation time 1982451171 ps
CPU time 9.9 seconds
Started Aug 28 10:34:15 PM UTC 24
Finished Aug 28 10:34:26 PM UTC 24
Peak memory 230952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3783144502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad
dr.3783144502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.1368430237
Short name T952
Test name
Test status
Simulation time 483614513 ps
CPU time 1.71 seconds
Started Aug 28 10:34:11 PM UTC 24
Finished Aug 28 10:34:14 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368430
237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.1368430237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.323502278
Short name T953
Test name
Test status
Simulation time 206615572 ps
CPU time 1.5 seconds
Started Aug 28 10:34:13 PM UTC 24
Finished Aug 28 10:34:15 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235022
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.323502278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.3511072474
Short name T967
Test name
Test status
Simulation time 651562363 ps
CPU time 5.66 seconds
Started Aug 28 10:34:19 PM UTC 24
Finished Aug 28 10:34:26 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511072
474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.3511072474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.738280774
Short name T963
Test name
Test status
Simulation time 46850437 ps
CPU time 1.31 seconds
Started Aug 28 10:34:19 PM UTC 24
Finished Aug 28 10:34:22 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7382807
74 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermarks
_tx.738280774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.174830041
Short name T958
Test name
Test status
Simulation time 12447172745 ps
CPU time 13.34 seconds
Started Aug 28 10:34:03 PM UTC 24
Finished Aug 28 10:34:18 PM UTC 24
Peak memory 230984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174830
041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.174830041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.3887753191
Short name T1011
Test name
Test status
Simulation time 20115260478 ps
CPU time 76.87 seconds
Started Aug 28 10:34:03 PM UTC 24
Finished Aug 28 10:35:22 PM UTC 24
Peak memory 1483160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3887753191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres
s_wr.3887753191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.3342132814
Short name T969
Test name
Test status
Simulation time 564518716 ps
CPU time 4.58 seconds
Started Aug 28 10:34:21 PM UTC 24
Finished Aug 28 10:34:27 PM UTC 24
Peak memory 226708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342132
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.3342132814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.389309181
Short name T904
Test name
Test status
Simulation time 2169455682 ps
CPU time 5.07 seconds
Started Aug 28 10:34:22 PM UTC 24
Finished Aug 28 10:34:28 PM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893091
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_addr.389309181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_perf.1220691355
Short name T961
Test name
Test status
Simulation time 524369757 ps
CPU time 6.76 seconds
Started Aug 28 10:34:13 PM UTC 24
Finished Aug 28 10:34:21 PM UTC 24
Peak memory 233508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220691
355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.1220691355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.4043557686
Short name T965
Test name
Test status
Simulation time 484005716 ps
CPU time 4.38 seconds
Started Aug 28 10:34:19 PM UTC 24
Finished Aug 28 10:34:25 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043557
686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.4043557686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.4267940175
Short name T90
Test name
Test status
Simulation time 4425129604 ps
CPU time 14.97 seconds
Started Aug 28 10:34:00 PM UTC 24
Finished Aug 28 10:34:16 PM UTC 24
Peak memory 231348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267940175 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.4267940175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.1544575203
Short name T1447
Test name
Test status
Simulation time 35147026662 ps
CPU time 591.84 seconds
Started Aug 28 10:34:13 PM UTC 24
Finished Aug 28 10:44:11 PM UTC 24
Peak memory 6273252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154457
5203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.1544575203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.1737870234
Short name T1023
Test name
Test status
Simulation time 3187970224 ps
CPU time 87.77 seconds
Started Aug 28 10:34:02 PM UTC 24
Finished Aug 28 10:35:32 PM UTC 24
Peak memory 231340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737870234 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.1737870234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.2039245533
Short name T1131
Test name
Test status
Simulation time 31029128567 ps
CPU time 216.11 seconds
Started Aug 28 10:34:00 PM UTC 24
Finished Aug 28 10:37:39 PM UTC 24
Peak memory 2764948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039245533 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.2039245533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.3711511686
Short name T960
Test name
Test status
Simulation time 1533269198 ps
CPU time 27.46 seconds
Started Aug 28 10:34:02 PM UTC 24
Finished Aug 28 10:34:31 PM UTC 24
Peak memory 528416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711511686 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.3711511686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.1449293828
Short name T955
Test name
Test status
Simulation time 1371960823 ps
CPU time 11.32 seconds
Started Aug 28 10:34:04 PM UTC 24
Finished Aug 28 10:34:17 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449293
828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.1449293828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.1008607667
Short name T966
Test name
Test status
Simulation time 144981040 ps
CPU time 4.7 seconds
Started Aug 28 10:34:19 PM UTC 24
Finished Aug 28 10:34:25 PM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008607
667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1008607667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_alert_test.2215285215
Short name T991
Test name
Test status
Simulation time 28951243 ps
CPU time 0.91 seconds
Started Aug 28 10:34:59 PM UTC 24
Finished Aug 28 10:35:00 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215285215 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2215285215
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.467623422
Short name T861
Test name
Test status
Simulation time 234319705 ps
CPU time 2.55 seconds
Started Aug 28 10:34:31 PM UTC 24
Finished Aug 28 10:34:35 PM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467623422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.467623422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.2570334733
Short name T971
Test name
Test status
Simulation time 1384039397 ps
CPU time 8.27 seconds
Started Aug 28 10:34:28 PM UTC 24
Finished Aug 28 10:34:38 PM UTC 24
Peak memory 295056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570334733 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.2570334733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.1260175194
Short name T1081
Test name
Test status
Simulation time 3356599020 ps
CPU time 129.2 seconds
Started Aug 28 10:34:28 PM UTC 24
Finished Aug 28 10:36:40 PM UTC 24
Peak memory 592076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260175194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1260175194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.1596712464
Short name T1036
Test name
Test status
Simulation time 1387156456 ps
CPU time 77.45 seconds
Started Aug 28 10:34:26 PM UTC 24
Finished Aug 28 10:35:45 PM UTC 24
Peak memory 491668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596712464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1596712464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.931961528
Short name T956
Test name
Test status
Simulation time 992639564 ps
CPU time 1.5 seconds
Started Aug 28 10:34:26 PM UTC 24
Finished Aug 28 10:34:29 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931961528 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.931961528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.604812046
Short name T972
Test name
Test status
Simulation time 136989984 ps
CPU time 8.79 seconds
Started Aug 28 10:34:28 PM UTC 24
Finished Aug 28 10:34:38 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604812046 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.604812046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.42923925
Short name T125
Test name
Test status
Simulation time 13522307384 ps
CPU time 96.86 seconds
Started Aug 28 10:34:26 PM UTC 24
Finished Aug 28 10:36:05 PM UTC 24
Peak memory 1046744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42923925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.42923925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.3462234200
Short name T1004
Test name
Test status
Simulation time 249048261 ps
CPU time 13.18 seconds
Started Aug 28 10:34:56 PM UTC 24
Finished Aug 28 10:35:10 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462234200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3462234200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_override.314946064
Short name T970
Test name
Test status
Simulation time 44933684 ps
CPU time 0.96 seconds
Started Aug 28 10:34:26 PM UTC 24
Finished Aug 28 10:34:28 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314946064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.314946064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_perf.3081860002
Short name T974
Test name
Test status
Simulation time 2916835175 ps
CPU time 14.87 seconds
Started Aug 28 10:34:28 PM UTC 24
Finished Aug 28 10:34:44 PM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081860002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3081860002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.2696563040
Short name T1143
Test name
Test status
Simulation time 24698930982 ps
CPU time 204.41 seconds
Started Aug 28 10:34:30 PM UTC 24
Finished Aug 28 10:37:59 PM UTC 24
Peak memory 1656280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696563040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2696563040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.3883861327
Short name T979
Test name
Test status
Simulation time 5573722332 ps
CPU time 25.7 seconds
Started Aug 28 10:34:24 PM UTC 24
Finished Aug 28 10:34:51 PM UTC 24
Peak memory 303360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883861327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3883861327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.4143135079
Short name T975
Test name
Test status
Simulation time 675184329 ps
CPU time 13.63 seconds
Started Aug 28 10:34:30 PM UTC 24
Finished Aug 28 10:34:46 PM UTC 24
Peak memory 228516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143135079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.4143135079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.1570793794
Short name T985
Test name
Test status
Simulation time 837862931 ps
CPU time 8.19 seconds
Started Aug 28 10:34:48 PM UTC 24
Finished Aug 28 10:34:57 PM UTC 24
Peak memory 230900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1570793794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_ad
dr.1570793794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.2134859924
Short name T977
Test name
Test status
Simulation time 395021052 ps
CPU time 2.04 seconds
Started Aug 28 10:34:44 PM UTC 24
Finished Aug 28 10:34:48 PM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134859
924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.2134859924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.3856568864
Short name T978
Test name
Test status
Simulation time 344161969 ps
CPU time 1.45 seconds
Started Aug 28 10:34:45 PM UTC 24
Finished Aug 28 10:34:48 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856568
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.3856568864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2225215251
Short name T992
Test name
Test status
Simulation time 1126761792 ps
CPU time 3.88 seconds
Started Aug 28 10:34:56 PM UTC 24
Finished Aug 28 10:35:01 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225215
251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar
ks_acq.2225215251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.432641693
Short name T990
Test name
Test status
Simulation time 242984478 ps
CPU time 2 seconds
Started Aug 28 10:34:57 PM UTC 24
Finished Aug 28 10:35:00 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4326416
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermarks
_tx.432641693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.661214888
Short name T983
Test name
Test status
Simulation time 2743140083 ps
CPU time 11.31 seconds
Started Aug 28 10:34:40 PM UTC 24
Finished Aug 28 10:34:53 PM UTC 24
Peak memory 226980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661214
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.661214888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.1347374090
Short name T980
Test name
Test status
Simulation time 5451072029 ps
CPU time 7.68 seconds
Started Aug 28 10:34:42 PM UTC 24
Finished Aug 28 10:34:51 PM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1347374090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres
s_wr.1347374090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.638533596
Short name T998
Test name
Test status
Simulation time 499863822 ps
CPU time 4.45 seconds
Started Aug 28 10:34:57 PM UTC 24
Finished Aug 28 10:35:03 PM UTC 24
Peak memory 226724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6385335
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.638533596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.3055979585
Short name T996
Test name
Test status
Simulation time 2807249013 ps
CPU time 3.81 seconds
Started Aug 28 10:34:57 PM UTC 24
Finished Aug 28 10:35:02 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055979
585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad
dr.3055979585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.2279946185
Short name T995
Test name
Test status
Simulation time 1073880346 ps
CPU time 2.29 seconds
Started Aug 28 10:34:58 PM UTC 24
Finished Aug 28 10:35:02 PM UTC 24
Peak memory 233428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279946
185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.2279946185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_perf.684378782
Short name T982
Test name
Test status
Simulation time 1348790726 ps
CPU time 4.13 seconds
Started Aug 28 10:34:47 PM UTC 24
Finished Aug 28 10:34:52 PM UTC 24
Peak memory 233520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6843787
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.684378782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.1598811793
Short name T997
Test name
Test status
Simulation time 4622663074 ps
CPU time 4.1 seconds
Started Aug 28 10:34:57 PM UTC 24
Finished Aug 28 10:35:02 PM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598811
793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.1598811793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.3738416552
Short name T1066
Test name
Test status
Simulation time 49059442817 ps
CPU time 94.58 seconds
Started Aug 28 10:34:47 PM UTC 24
Finished Aug 28 10:36:23 PM UTC 24
Peak memory 741548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373841
6552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.3738416552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.3219284853
Short name T989
Test name
Test status
Simulation time 428092081 ps
CPU time 18.87 seconds
Started Aug 28 10:34:40 PM UTC 24
Finished Aug 28 10:35:00 PM UTC 24
Peak memory 216824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219284853 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.3219284853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.617671113
Short name T1732
Test name
Test status
Simulation time 58928301672 ps
CPU time 1129.46 seconds
Started Aug 28 10:34:39 PM UTC 24
Finished Aug 28 10:53:40 PM UTC 24
Peak memory 9367708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617671113 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.617671113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.2576471213
Short name T986
Test name
Test status
Simulation time 3012955507 ps
CPU time 16.33 seconds
Started Aug 28 10:34:40 PM UTC 24
Finished Aug 28 10:34:58 PM UTC 24
Peak memory 268556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576471213 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.2576471213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.2234655966
Short name T984
Test name
Test status
Simulation time 1301776092 ps
CPU time 12.13 seconds
Started Aug 28 10:34:43 PM UTC 24
Finished Aug 28 10:34:57 PM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234655
966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.2234655966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.1617950732
Short name T993
Test name
Test status
Simulation time 118685755 ps
CPU time 3.4 seconds
Started Aug 28 10:34:57 PM UTC 24
Finished Aug 28 10:35:02 PM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617950
732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.1617950732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_alert_test.660791254
Short name T1024
Test name
Test status
Simulation time 34942564 ps
CPU time 0.91 seconds
Started Aug 28 10:35:30 PM UTC 24
Finished Aug 28 10:35:32 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660791254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.660791254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.3280419258
Short name T1006
Test name
Test status
Simulation time 334336653 ps
CPU time 8.92 seconds
Started Aug 28 10:35:02 PM UTC 24
Finished Aug 28 10:35:12 PM UTC 24
Peak memory 286940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280419258 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.3280419258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.3973034481
Short name T1105
Test name
Test status
Simulation time 43648528622 ps
CPU time 122.02 seconds
Started Aug 28 10:35:02 PM UTC 24
Finished Aug 28 10:37:07 PM UTC 24
Peak memory 706832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973034481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3973034481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.1063376942
Short name T1074
Test name
Test status
Simulation time 23422032794 ps
CPU time 90.38 seconds
Started Aug 28 10:35:01 PM UTC 24
Finished Aug 28 10:36:33 PM UTC 24
Peak memory 934312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063376942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1063376942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.3955012287
Short name T1000
Test name
Test status
Simulation time 752683305 ps
CPU time 1.86 seconds
Started Aug 28 10:35:01 PM UTC 24
Finished Aug 28 10:35:04 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955012287 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.3955012287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.3225470334
Short name T1005
Test name
Test status
Simulation time 218293587 ps
CPU time 8.74 seconds
Started Aug 28 10:35:02 PM UTC 24
Finished Aug 28 10:35:12 PM UTC 24
Peak memory 260172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225470334 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.3225470334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.4145054680
Short name T1063
Test name
Test status
Simulation time 33628755770 ps
CPU time 77.8 seconds
Started Aug 28 10:35:01 PM UTC 24
Finished Aug 28 10:36:20 PM UTC 24
Peak memory 954672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145054680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4145054680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.775668689
Short name T1035
Test name
Test status
Simulation time 469006020 ps
CPU time 19.67 seconds
Started Aug 28 10:35:23 PM UTC 24
Finished Aug 28 10:35:43 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775668689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.775668689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_mode_toggle.1420256699
Short name T1016
Test name
Test status
Simulation time 326178036 ps
CPU time 1.98 seconds
Started Aug 28 10:35:23 PM UTC 24
Finished Aug 28 10:35:26 PM UTC 24
Peak memory 226440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420256699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1420256699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_override.3547336810
Short name T994
Test name
Test status
Simulation time 33390662 ps
CPU time 0.96 seconds
Started Aug 28 10:35:00 PM UTC 24
Finished Aug 28 10:35:02 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547336810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3547336810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_perf.2842187401
Short name T1003
Test name
Test status
Simulation time 492910015 ps
CPU time 3.07 seconds
Started Aug 28 10:35:03 PM UTC 24
Finished Aug 28 10:35:07 PM UTC 24
Peak memory 239164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842187401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2842187401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.3671510237
Short name T1002
Test name
Test status
Simulation time 98758063 ps
CPU time 1.84 seconds
Started Aug 28 10:35:03 PM UTC 24
Finished Aug 28 10:35:06 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671510237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3671510237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.513256951
Short name T1030
Test name
Test status
Simulation time 1753327826 ps
CPU time 34.54 seconds
Started Aug 28 10:35:00 PM UTC 24
Finished Aug 28 10:35:35 PM UTC 24
Peak memory 393256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513256951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.513256951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_stress_all.3355113306
Short name T202
Test name
Test status
Simulation time 36305484510 ps
CPU time 249.22 seconds
Started Aug 28 10:35:05 PM UTC 24
Finished Aug 28 10:39:17 PM UTC 24
Peak memory 1020196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355113306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3355113306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.2854638131
Short name T1020
Test name
Test status
Simulation time 1810135272 ps
CPU time 24.52 seconds
Started Aug 28 10:35:03 PM UTC 24
Finished Aug 28 10:35:29 PM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854638131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2854638131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.1246081224
Short name T1017
Test name
Test status
Simulation time 6898116958 ps
CPU time 6.67 seconds
Started Aug 28 10:35:19 PM UTC 24
Finished Aug 28 10:35:27 PM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1246081224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_ad
dr.1246081224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.2295953640
Short name T1007
Test name
Test status
Simulation time 604462847 ps
CPU time 1.87 seconds
Started Aug 28 10:35:13 PM UTC 24
Finished Aug 28 10:35:16 PM UTC 24
Peak memory 218628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295953
640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.2295953640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.736063466
Short name T1009
Test name
Test status
Simulation time 376656144 ps
CPU time 1.53 seconds
Started Aug 28 10:35:16 PM UTC 24
Finished Aug 28 10:35:19 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7360634
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.736063466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.4003779681
Short name T1021
Test name
Test status
Simulation time 1653867501 ps
CPU time 4.62 seconds
Started Aug 28 10:35:25 PM UTC 24
Finished Aug 28 10:35:30 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003779
681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar
ks_acq.4003779681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.391478771
Short name T1018
Test name
Test status
Simulation time 130993623 ps
CPU time 1.9 seconds
Started Aug 28 10:35:26 PM UTC 24
Finished Aug 28 10:35:29 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914787
71 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermarks
_tx.391478771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.4168410319
Short name T1008
Test name
Test status
Simulation time 1167971690 ps
CPU time 9.14 seconds
Started Aug 28 10:35:08 PM UTC 24
Finished Aug 28 10:35:18 PM UTC 24
Peak memory 233772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416841
0319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.4168410319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.1738770509
Short name T1041
Test name
Test status
Simulation time 14501190497 ps
CPU time 43.69 seconds
Started Aug 28 10:35:09 PM UTC 24
Finished Aug 28 10:35:54 PM UTC 24
Peak memory 592092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1738770509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stres
s_wr.1738770509
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.322802129
Short name T1027
Test name
Test status
Simulation time 463173677 ps
CPU time 4.96 seconds
Started Aug 28 10:35:28 PM UTC 24
Finished Aug 28 10:35:34 PM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228021
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.322802129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.724131745
Short name T1025
Test name
Test status
Simulation time 4053779612 ps
CPU time 3.11 seconds
Started Aug 28 10:35:29 PM UTC 24
Finished Aug 28 10:35:33 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7241317
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_addr.724131745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_nack_txstretch.3332330413
Short name T1026
Test name
Test status
Simulation time 467905000 ps
CPU time 2.76 seconds
Started Aug 28 10:35:30 PM UTC 24
Finished Aug 28 10:35:34 PM UTC 24
Peak memory 233460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332330
413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_txstretch.3332330413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_perf.2268293876
Short name T1015
Test name
Test status
Simulation time 646000228 ps
CPU time 7.08 seconds
Started Aug 28 10:35:17 PM UTC 24
Finished Aug 28 10:35:25 PM UTC 24
Peak memory 231160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268293
876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.2268293876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.3474702336
Short name T1022
Test name
Test status
Simulation time 575200388 ps
CPU time 3.68 seconds
Started Aug 28 10:35:27 PM UTC 24
Finished Aug 28 10:35:32 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474702
336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.3474702336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.2323124504
Short name T1034
Test name
Test status
Simulation time 3869090220 ps
CPU time 35.37 seconds
Started Aug 28 10:35:05 PM UTC 24
Finished Aug 28 10:35:41 PM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323124504 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.2323124504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.3792877559
Short name T1262
Test name
Test status
Simulation time 19095105475 ps
CPU time 288.39 seconds
Started Aug 28 10:35:19 PM UTC 24
Finished Aug 28 10:40:11 PM UTC 24
Peak memory 2930844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379287
7559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.3792877559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.3136026950
Short name T1033
Test name
Test status
Simulation time 5404756386 ps
CPU time 32.4 seconds
Started Aug 28 10:35:07 PM UTC 24
Finished Aug 28 10:35:40 PM UTC 24
Peak memory 245848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136026950 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.3136026950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.3671053954
Short name T1479
Test name
Test status
Simulation time 42857728939 ps
CPU time 564.7 seconds
Started Aug 28 10:35:06 PM UTC 24
Finished Aug 28 10:44:37 PM UTC 24
Peak memory 5841044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671053954 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.3671053954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.2340699608
Short name T1029
Test name
Test status
Simulation time 2548291486 ps
CPU time 27.36 seconds
Started Aug 28 10:35:07 PM UTC 24
Finished Aug 28 10:35:35 PM UTC 24
Peak memory 315544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340699608 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.2340699608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.619779536
Short name T1013
Test name
Test status
Simulation time 4830444898 ps
CPU time 11.65 seconds
Started Aug 28 10:35:11 PM UTC 24
Finished Aug 28 10:35:24 PM UTC 24
Peak memory 231284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6197795
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.619779536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.1731420472
Short name T1019
Test name
Test status
Simulation time 110664351 ps
CPU time 2.2 seconds
Started Aug 28 10:35:26 PM UTC 24
Finished Aug 28 10:35:29 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731420
472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1731420472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_alert_test.2307763168
Short name T1051
Test name
Test status
Simulation time 51922596 ps
CPU time 0.92 seconds
Started Aug 28 10:36:06 PM UTC 24
Finished Aug 28 10:36:08 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307763168 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2307763168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.2971629316
Short name T1038
Test name
Test status
Simulation time 734001223 ps
CPU time 11.79 seconds
Started Aug 28 10:35:38 PM UTC 24
Finished Aug 28 10:35:51 PM UTC 24
Peak memory 250068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971629316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2971629316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.2837559988
Short name T1052
Test name
Test status
Simulation time 1203177600 ps
CPU time 32.49 seconds
Started Aug 28 10:35:35 PM UTC 24
Finished Aug 28 10:36:08 PM UTC 24
Peak memory 358480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837559988 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.2837559988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.4175062809
Short name T1191
Test name
Test status
Simulation time 3404184537 ps
CPU time 202.09 seconds
Started Aug 28 10:35:35 PM UTC 24
Finished Aug 28 10:39:00 PM UTC 24
Peak memory 436428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175062809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.4175062809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.1301673587
Short name T1067
Test name
Test status
Simulation time 1513572225 ps
CPU time 49.19 seconds
Started Aug 28 10:35:34 PM UTC 24
Finished Aug 28 10:36:24 PM UTC 24
Peak memory 559244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301673587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1301673587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.2651704322
Short name T1031
Test name
Test status
Simulation time 478493485 ps
CPU time 1.89 seconds
Started Aug 28 10:35:35 PM UTC 24
Finished Aug 28 10:35:37 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651704322 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.2651704322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3018542711
Short name T1032
Test name
Test status
Simulation time 101751384 ps
CPU time 4.33 seconds
Started Aug 28 10:35:35 PM UTC 24
Finished Aug 28 10:35:40 PM UTC 24
Peak memory 225308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018542711 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3018542711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.1367643418
Short name T1097
Test name
Test status
Simulation time 23682473171 ps
CPU time 78.65 seconds
Started Aug 28 10:35:32 PM UTC 24
Finished Aug 28 10:36:53 PM UTC 24
Peak memory 942232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367643418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1367643418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.1247143005
Short name T1054
Test name
Test status
Simulation time 1974127660 ps
CPU time 9.2 seconds
Started Aug 28 10:35:58 PM UTC 24
Finished Aug 28 10:36:09 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247143005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1247143005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_override.819836161
Short name T1028
Test name
Test status
Simulation time 28304994 ps
CPU time 0.96 seconds
Started Aug 28 10:35:32 PM UTC 24
Finished Aug 28 10:35:34 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819836161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.819836161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_perf.2510523567
Short name T1381
Test name
Test status
Simulation time 27962550280 ps
CPU time 440.43 seconds
Started Aug 28 10:35:36 PM UTC 24
Finished Aug 28 10:43:02 PM UTC 24
Peak memory 1720484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510523567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2510523567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.2309680432
Short name T1043
Test name
Test status
Simulation time 2542122681 ps
CPU time 17.65 seconds
Started Aug 28 10:35:36 PM UTC 24
Finished Aug 28 10:35:55 PM UTC 24
Peak memory 239224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309680432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.2309680432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.1184709749
Short name T1065
Test name
Test status
Simulation time 13085639585 ps
CPU time 49.29 seconds
Started Aug 28 10:35:31 PM UTC 24
Finished Aug 28 10:36:22 PM UTC 24
Peak memory 418056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184709749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1184709749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.2605614257
Short name T136
Test name
Test status
Simulation time 40169409457 ps
CPU time 1098.96 seconds
Started Aug 28 10:35:41 PM UTC 24
Finished Aug 28 10:54:13 PM UTC 24
Peak memory 3004692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605614257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2605614257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.3965865895
Short name T1049
Test name
Test status
Simulation time 1201031740 ps
CPU time 29.48 seconds
Started Aug 28 10:35:36 PM UTC 24
Finished Aug 28 10:36:07 PM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965865895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3965865895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.3148360390
Short name T999
Test name
Test status
Simulation time 3551864163 ps
CPU time 5.16 seconds
Started Aug 28 10:35:55 PM UTC 24
Finished Aug 28 10:36:01 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3148360390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_ad
dr.3148360390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.1327758063
Short name T1042
Test name
Test status
Simulation time 295169172 ps
CPU time 1.45 seconds
Started Aug 28 10:35:52 PM UTC 24
Finished Aug 28 10:35:54 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327758
063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.1327758063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.3169574716
Short name T1046
Test name
Test status
Simulation time 1688869504 ps
CPU time 4.36 seconds
Started Aug 28 10:35:58 PM UTC 24
Finished Aug 28 10:36:04 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169574
716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermar
ks_acq.3169574716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.1206638848
Short name T1045
Test name
Test status
Simulation time 137034492 ps
CPU time 1.84 seconds
Started Aug 28 10:35:58 PM UTC 24
Finished Aug 28 10:36:02 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206638
848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_tx.1206638848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.1114096432
Short name T987
Test name
Test status
Simulation time 3579457766 ps
CPU time 9.7 seconds
Started Aug 28 10:35:47 PM UTC 24
Finished Aug 28 10:35:58 PM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111409
6432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.1114096432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.881136077
Short name T1039
Test name
Test status
Simulation time 208383872 ps
CPU time 2.34 seconds
Started Aug 28 10:35:48 PM UTC 24
Finished Aug 28 10:35:51 PM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=881136077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.881136077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.2915819399
Short name T1053
Test name
Test status
Simulation time 1133019567 ps
CPU time 4.88 seconds
Started Aug 28 10:36:03 PM UTC 24
Finished Aug 28 10:36:09 PM UTC 24
Peak memory 226792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915819
399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.2915819399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.1571591201
Short name T1058
Test name
Test status
Simulation time 1152804566 ps
CPU time 4.83 seconds
Started Aug 28 10:36:05 PM UTC 24
Finished Aug 28 10:36:11 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571591
201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad
dr.1571591201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.1392829742
Short name T1055
Test name
Test status
Simulation time 594993136 ps
CPU time 2.14 seconds
Started Aug 28 10:36:06 PM UTC 24
Finished Aug 28 10:36:09 PM UTC 24
Peak memory 233496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392829
742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_txstretch.1392829742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_perf.1625424515
Short name T1048
Test name
Test status
Simulation time 784179608 ps
CPU time 8.88 seconds
Started Aug 28 10:35:55 PM UTC 24
Finished Aug 28 10:36:05 PM UTC 24
Peak memory 233768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625424
515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.1625424515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.347421011
Short name T1050
Test name
Test status
Simulation time 996263510 ps
CPU time 3.16 seconds
Started Aug 28 10:36:03 PM UTC 24
Finished Aug 28 10:36:07 PM UTC 24
Peak memory 216300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474210
11 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.347421011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.2558478871
Short name T91
Test name
Test status
Simulation time 2929935374 ps
CPU time 24.81 seconds
Started Aug 28 10:35:41 PM UTC 24
Finished Aug 28 10:36:08 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558478871 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.2558478871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.3486922551
Short name T1226
Test name
Test status
Simulation time 16704023178 ps
CPU time 223.6 seconds
Started Aug 28 10:35:55 PM UTC 24
Finished Aug 28 10:39:42 PM UTC 24
Peak memory 2201732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348692
2551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.3486922551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.1617158667
Short name T1040
Test name
Test status
Simulation time 723877900 ps
CPU time 7.44 seconds
Started Aug 28 10:35:43 PM UTC 24
Finished Aug 28 10:35:52 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617158667 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.1617158667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.2646768644
Short name T1720
Test name
Test status
Simulation time 50167166820 ps
CPU time 842.37 seconds
Started Aug 28 10:35:42 PM UTC 24
Finished Aug 28 10:49:54 PM UTC 24
Peak memory 7663832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646768644 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.2646768644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2158494051
Short name T1014
Test name
Test status
Simulation time 2928794131 ps
CPU time 12.47 seconds
Started Aug 28 10:35:44 PM UTC 24
Finished Aug 28 10:35:58 PM UTC 24
Peak memory 315784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158494051 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.2158494051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.1270732117
Short name T1047
Test name
Test status
Simulation time 5896655150 ps
CPU time 12.73 seconds
Started Aug 28 10:35:51 PM UTC 24
Finished Aug 28 10:36:05 PM UTC 24
Peak memory 233020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270732
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.1270732117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3669450463
Short name T1056
Test name
Test status
Simulation time 375211701 ps
CPU time 8.72 seconds
Started Aug 28 10:36:00 PM UTC 24
Finished Aug 28 10:36:10 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669450
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3669450463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_alert_test.1914676972
Short name T327
Test name
Test status
Simulation time 17852759 ps
CPU time 0.96 seconds
Started Aug 28 10:22:23 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914676972 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1914676972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.3501352133
Short name T175
Test name
Test status
Simulation time 314439876 ps
CPU time 7.23 seconds
Started Aug 28 10:22:06 PM UTC 24
Finished Aug 28 10:22:14 PM UTC 24
Peak memory 266496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501352133 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.3501352133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.664165232
Short name T385
Test name
Test status
Simulation time 12028565638 ps
CPU time 90.27 seconds
Started Aug 28 10:22:07 PM UTC 24
Finished Aug 28 10:23:40 PM UTC 24
Peak memory 538788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664165232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.664165232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.4268808602
Short name T106
Test name
Test status
Simulation time 4619537280 ps
CPU time 57.93 seconds
Started Aug 28 10:22:06 PM UTC 24
Finished Aug 28 10:23:06 PM UTC 24
Peak memory 682220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268808602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.4268808602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.2709368853
Short name T172
Test name
Test status
Simulation time 310073716 ps
CPU time 1.69 seconds
Started Aug 28 10:22:06 PM UTC 24
Finished Aug 28 10:22:09 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709368853 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.2709368853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.616345601
Short name T94
Test name
Test status
Simulation time 717095743 ps
CPU time 9.53 seconds
Started Aug 28 10:22:06 PM UTC 24
Finished Aug 28 10:22:17 PM UTC 24
Peak memory 216500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616345601 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.616345601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.1510495305
Short name T482
Test name
Test status
Simulation time 3757056675 ps
CPU time 223.21 seconds
Started Aug 28 10:22:05 PM UTC 24
Finished Aug 28 10:25:52 PM UTC 24
Peak memory 1159120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510495305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1510495305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.2364272296
Short name T13
Test name
Test status
Simulation time 1968757345 ps
CPU time 6.99 seconds
Started Aug 28 10:22:17 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 216416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364272296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2364272296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_override.3231359909
Short name T170
Test name
Test status
Simulation time 94355548 ps
CPU time 1.09 seconds
Started Aug 28 10:22:05 PM UTC 24
Finished Aug 28 10:22:07 PM UTC 24
Peak memory 214072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231359909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3231359909
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_perf.927736397
Short name T15
Test name
Test status
Simulation time 11980388845 ps
CPU time 39.68 seconds
Started Aug 28 10:22:07 PM UTC 24
Finished Aug 28 10:22:48 PM UTC 24
Peak memory 217004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927736397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.927736397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.2989394735
Short name T193
Test name
Test status
Simulation time 53547686 ps
CPU time 1.92 seconds
Started Aug 28 10:22:07 PM UTC 24
Finished Aug 28 10:22:10 PM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989394735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.2989394735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.1934060329
Short name T366
Test name
Test status
Simulation time 6673669496 ps
CPU time 71.09 seconds
Started Aug 28 10:22:04 PM UTC 24
Finished Aug 28 10:23:17 PM UTC 24
Peak memory 309408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934060329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1934060329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3846507488
Short name T306
Test name
Test status
Simulation time 2840953074 ps
CPU time 13.34 seconds
Started Aug 28 10:22:07 PM UTC 24
Finished Aug 28 10:22:22 PM UTC 24
Peak memory 226856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846507488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3846507488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.1779097772
Short name T209
Test name
Test status
Simulation time 205083072 ps
CPU time 1.25 seconds
Started Aug 28 10:22:22 PM UTC 24
Finished Aug 28 10:22:24 PM UTC 24
Peak memory 246856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779097772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1779097772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.2007251409
Short name T183
Test name
Test status
Simulation time 1235505640 ps
CPU time 11.86 seconds
Started Aug 28 10:22:14 PM UTC 24
Finished Aug 28 10:22:27 PM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2007251409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2007251409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.181424717
Short name T196
Test name
Test status
Simulation time 249073256 ps
CPU time 1.73 seconds
Started Aug 28 10:22:13 PM UTC 24
Finished Aug 28 10:22:16 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814247
17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.181424717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.2053082178
Short name T93
Test name
Test status
Simulation time 273313966 ps
CPU time 2.53 seconds
Started Aug 28 10:22:13 PM UTC 24
Finished Aug 28 10:22:17 PM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053082
178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.2053082178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.3825701616
Short name T312
Test name
Test status
Simulation time 2715047797 ps
CPU time 6.52 seconds
Started Aug 28 10:22:18 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 216896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825701
616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.3825701616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.872565959
Short name T100
Test name
Test status
Simulation time 224212956 ps
CPU time 1.87 seconds
Started Aug 28 10:22:19 PM UTC 24
Finished Aug 28 10:22:21 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8725659
59 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.872565959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.2943966980
Short name T97
Test name
Test status
Simulation time 762152038 ps
CPU time 8.45 seconds
Started Aug 28 10:22:11 PM UTC 24
Finished Aug 28 10:22:20 PM UTC 24
Peak memory 232900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294396
6980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.2943966980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.3883645503
Short name T61
Test name
Test status
Simulation time 14042618973 ps
CPU time 47.83 seconds
Started Aug 28 10:22:11 PM UTC 24
Finished Aug 28 10:23:00 PM UTC 24
Peak memory 954588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3883645503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.3883645503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.2893848193
Short name T163
Test name
Test status
Simulation time 1929957931 ps
CPU time 4.41 seconds
Started Aug 28 10:22:21 PM UTC 24
Finished Aug 28 10:22:26 PM UTC 24
Peak memory 226752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893848
193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.2893848193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.624113961
Short name T164
Test name
Test status
Simulation time 2153342346 ps
CPU time 3.93 seconds
Started Aug 28 10:22:22 PM UTC 24
Finished Aug 28 10:22:27 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6241139
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.624113961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_perf.2405630911
Short name T96
Test name
Test status
Simulation time 6128509289 ps
CPU time 5.32 seconds
Started Aug 28 10:22:13 PM UTC 24
Finished Aug 28 10:22:19 PM UTC 24
Peak memory 233560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405630
911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.2405630911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.2532773977
Short name T324
Test name
Test status
Simulation time 393224342 ps
CPU time 3.24 seconds
Started Aug 28 10:22:20 PM UTC 24
Finished Aug 28 10:22:24 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532773
977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.2532773977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.80724626
Short name T326
Test name
Test status
Simulation time 1117679997 ps
CPU time 15.39 seconds
Started Aug 28 10:22:08 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 227072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80724626 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.80724626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.4243105000
Short name T253
Test name
Test status
Simulation time 81163072510 ps
CPU time 134.59 seconds
Started Aug 28 10:22:13 PM UTC 24
Finished Aug 28 10:24:30 PM UTC 24
Peak memory 1441960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424310
5000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.4243105000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.1159053216
Short name T133
Test name
Test status
Simulation time 6204657552 ps
CPU time 33.47 seconds
Started Aug 28 10:22:10 PM UTC 24
Finished Aug 28 10:22:44 PM UTC 24
Peak memory 250076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159053216 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.1159053216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.2992145813
Short name T62
Test name
Test status
Simulation time 30038841911 ps
CPU time 16.91 seconds
Started Aug 28 10:22:09 PM UTC 24
Finished Aug 28 10:22:28 PM UTC 24
Peak memory 450908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992145813 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.2992145813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.1680603664
Short name T101
Test name
Test status
Simulation time 1406206472 ps
CPU time 9.71 seconds
Started Aug 28 10:22:11 PM UTC 24
Finished Aug 28 10:22:22 PM UTC 24
Peak memory 233660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680603664 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.1680603664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.1886556959
Short name T325
Test name
Test status
Simulation time 2839825758 ps
CPU time 11.57 seconds
Started Aug 28 10:22:12 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 231040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886556
959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.1886556959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.2908858850
Short name T323
Test name
Test status
Simulation time 77383823 ps
CPU time 3 seconds
Started Aug 28 10:22:20 PM UTC 24
Finished Aug 28 10:22:24 PM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908858
850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.2908858850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_alert_test.1871807706
Short name T1084
Test name
Test status
Simulation time 49528098 ps
CPU time 0.93 seconds
Started Aug 28 10:36:40 PM UTC 24
Finished Aug 28 10:36:42 PM UTC 24
Peak memory 215340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871807706 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1871807706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.538407054
Short name T1060
Test name
Test status
Simulation time 119817999 ps
CPU time 2.1 seconds
Started Aug 28 10:36:11 PM UTC 24
Finished Aug 28 10:36:14 PM UTC 24
Peak memory 233736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538407054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.538407054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1582683034
Short name T1062
Test name
Test status
Simulation time 504337184 ps
CPU time 9.77 seconds
Started Aug 28 10:36:09 PM UTC 24
Finished Aug 28 10:36:20 PM UTC 24
Peak memory 278672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582683034 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.1582683034
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.348333570
Short name T1204
Test name
Test status
Simulation time 52307524824 ps
CPU time 191.26 seconds
Started Aug 28 10:36:10 PM UTC 24
Finished Aug 28 10:39:24 PM UTC 24
Peak memory 686312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348333570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.348333570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.955072408
Short name T1167
Test name
Test status
Simulation time 8136152705 ps
CPU time 138.74 seconds
Started Aug 28 10:36:09 PM UTC 24
Finished Aug 28 10:38:31 PM UTC 24
Peak memory 649680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955072408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.955072408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.3405632725
Short name T1059
Test name
Test status
Simulation time 82758788 ps
CPU time 1.54 seconds
Started Aug 28 10:36:09 PM UTC 24
Finished Aug 28 10:36:12 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405632725 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.3405632725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1965531606
Short name T1061
Test name
Test status
Simulation time 221133031 ps
CPU time 8.83 seconds
Started Aug 28 10:36:09 PM UTC 24
Finished Aug 28 10:36:19 PM UTC 24
Peak memory 260168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965531606 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.1965531606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.1664640603
Short name T1282
Test name
Test status
Simulation time 17278990742 ps
CPU time 269.76 seconds
Started Aug 28 10:36:08 PM UTC 24
Finished Aug 28 10:40:42 PM UTC 24
Peak memory 1280264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664640603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1664640603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.456143406
Short name T1083
Test name
Test status
Simulation time 2439522708 ps
CPU time 9.34 seconds
Started Aug 28 10:36:30 PM UTC 24
Finished Aug 28 10:36:41 PM UTC 24
Peak memory 216708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456143406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.456143406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_mode_toggle.3846612014
Short name T1075
Test name
Test status
Simulation time 86090634 ps
CPU time 2.94 seconds
Started Aug 28 10:36:30 PM UTC 24
Finished Aug 28 10:36:34 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846612014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3846612014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_override.359569940
Short name T1057
Test name
Test status
Simulation time 29262753 ps
CPU time 1.01 seconds
Started Aug 28 10:36:08 PM UTC 24
Finished Aug 28 10:36:10 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359569940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.359569940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_perf.2716491057
Short name T1733
Test name
Test status
Simulation time 51858330745 ps
CPU time 1096.7 seconds
Started Aug 28 10:36:11 PM UTC 24
Finished Aug 28 10:54:40 PM UTC 24
Peak memory 2660816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716491057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2716491057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.3561052542
Short name T1127
Test name
Test status
Simulation time 23353855232 ps
CPU time 79.79 seconds
Started Aug 28 10:36:11 PM UTC 24
Finished Aug 28 10:37:33 PM UTC 24
Peak memory 226788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561052542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3561052542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.110308333
Short name T1089
Test name
Test status
Simulation time 5017977463 ps
CPU time 35.28 seconds
Started Aug 28 10:36:06 PM UTC 24
Finished Aug 28 10:36:43 PM UTC 24
Peak memory 413844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110308333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.110308333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.2251108436
Short name T1092
Test name
Test status
Simulation time 2506838909 ps
CPU time 33.47 seconds
Started Aug 28 10:36:11 PM UTC 24
Finished Aug 28 10:36:46 PM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251108436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2251108436
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.98347887
Short name T1077
Test name
Test status
Simulation time 878361743 ps
CPU time 7.69 seconds
Started Aug 28 10:36:28 PM UTC 24
Finished Aug 28 10:36:37 PM UTC 24
Peak memory 226876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=98347887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.98347887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.4201541220
Short name T1068
Test name
Test status
Simulation time 420224024 ps
CPU time 1.66 seconds
Started Aug 28 10:36:24 PM UTC 24
Finished Aug 28 10:36:26 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201541
220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.4201541220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.2704864673
Short name T1070
Test name
Test status
Simulation time 632665513 ps
CPU time 2.6 seconds
Started Aug 28 10:36:25 PM UTC 24
Finished Aug 28 10:36:28 PM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704864
673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.2704864673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3217424523
Short name T1078
Test name
Test status
Simulation time 783523465 ps
CPU time 3.65 seconds
Started Aug 28 10:36:32 PM UTC 24
Finished Aug 28 10:36:37 PM UTC 24
Peak memory 216588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217424
523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermar
ks_acq.3217424523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.3947435352
Short name T1079
Test name
Test status
Simulation time 372558597 ps
CPU time 1.76 seconds
Started Aug 28 10:36:34 PM UTC 24
Finished Aug 28 10:36:37 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947435
352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_tx.3947435352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.708212616
Short name T1071
Test name
Test status
Simulation time 4486915769 ps
CPU time 6.48 seconds
Started Aug 28 10:36:21 PM UTC 24
Finished Aug 28 10:36:29 PM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708212
616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.708212616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.3687456795
Short name T1073
Test name
Test status
Simulation time 12029753529 ps
CPU time 8.8 seconds
Started Aug 28 10:36:21 PM UTC 24
Finished Aug 28 10:36:31 PM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3687456795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres
s_wr.3687456795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.2942573565
Short name T1088
Test name
Test status
Simulation time 949331262 ps
CPU time 4.27 seconds
Started Aug 28 10:36:37 PM UTC 24
Finished Aug 28 10:36:43 PM UTC 24
Peak memory 227120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942573
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.2942573565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.2531585903
Short name T1090
Test name
Test status
Simulation time 557594886 ps
CPU time 4.95 seconds
Started Aug 28 10:36:38 PM UTC 24
Finished Aug 28 10:36:44 PM UTC 24
Peak memory 216788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531585
903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad
dr.2531585903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_perf.1936477859
Short name T1080
Test name
Test status
Simulation time 5797832446 ps
CPU time 11.6 seconds
Started Aug 28 10:36:26 PM UTC 24
Finished Aug 28 10:36:38 PM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936477
859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.1936477859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1198953432
Short name T1085
Test name
Test status
Simulation time 493564939 ps
CPU time 3.32 seconds
Started Aug 28 10:36:37 PM UTC 24
Finished Aug 28 10:36:42 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198953
432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.1198953432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.339081978
Short name T1093
Test name
Test status
Simulation time 948029337 ps
CPU time 33.69 seconds
Started Aug 28 10:36:13 PM UTC 24
Finished Aug 28 10:36:48 PM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339081978 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.339081978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.3512994821
Short name T1123
Test name
Test status
Simulation time 7330854987 ps
CPU time 61.13 seconds
Started Aug 28 10:36:27 PM UTC 24
Finished Aug 28 10:37:30 PM UTC 24
Peak memory 299176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351299
4821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.3512994821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.1997013754
Short name T1102
Test name
Test status
Simulation time 977853978 ps
CPU time 48.37 seconds
Started Aug 28 10:36:15 PM UTC 24
Finished Aug 28 10:37:05 PM UTC 24
Peak memory 228800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997013754 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.1997013754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.838565196
Short name T1379
Test name
Test status
Simulation time 61074845879 ps
CPU time 401.23 seconds
Started Aug 28 10:36:13 PM UTC 24
Finished Aug 28 10:42:59 PM UTC 24
Peak memory 4127132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838565196 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.838565196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.3363308205
Short name T1069
Test name
Test status
Simulation time 1246415063 ps
CPU time 5.63 seconds
Started Aug 28 10:36:20 PM UTC 24
Finished Aug 28 10:36:27 PM UTC 24
Peak memory 223076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363308205 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.3363308205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.3354200680
Short name T1076
Test name
Test status
Simulation time 5509738162 ps
CPU time 13.75 seconds
Started Aug 28 10:36:21 PM UTC 24
Finished Aug 28 10:36:36 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354200
680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.3354200680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.3005319881
Short name T1082
Test name
Test status
Simulation time 119221966 ps
CPU time 3.84 seconds
Started Aug 28 10:36:35 PM UTC 24
Finished Aug 28 10:36:40 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005319
881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3005319881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_alert_test.2515680657
Short name T1117
Test name
Test status
Simulation time 15883798 ps
CPU time 0.97 seconds
Started Aug 28 10:37:15 PM UTC 24
Finished Aug 28 10:37:17 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515680657 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2515680657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3303307462
Short name T1094
Test name
Test status
Simulation time 220581853 ps
CPU time 1.91 seconds
Started Aug 28 10:36:45 PM UTC 24
Finished Aug 28 10:36:48 PM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303307462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3303307462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3067784072
Short name T1100
Test name
Test status
Simulation time 514892124 ps
CPU time 15.26 seconds
Started Aug 28 10:36:43 PM UTC 24
Finished Aug 28 10:37:00 PM UTC 24
Peak memory 327640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067784072 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.3067784072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.944644393
Short name T1174
Test name
Test status
Simulation time 6197814535 ps
CPU time 109.89 seconds
Started Aug 28 10:36:43 PM UTC 24
Finished Aug 28 10:38:35 PM UTC 24
Peak memory 735432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944644393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.944644393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.687856505
Short name T1195
Test name
Test status
Simulation time 4204093316 ps
CPU time 142.11 seconds
Started Aug 28 10:36:42 PM UTC 24
Finished Aug 28 10:39:07 PM UTC 24
Peak memory 752084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687856505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.687856505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.419494629
Short name T1091
Test name
Test status
Simulation time 222531948 ps
CPU time 1.56 seconds
Started Aug 28 10:36:42 PM UTC 24
Finished Aug 28 10:36:45 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419494629 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.419494629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.615783816
Short name T1098
Test name
Test status
Simulation time 2138248559 ps
CPU time 9.41 seconds
Started Aug 28 10:36:43 PM UTC 24
Finished Aug 28 10:36:54 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615783816 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.615783816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.1068190035
Short name T1209
Test name
Test status
Simulation time 24531787386 ps
CPU time 162.13 seconds
Started Aug 28 10:36:41 PM UTC 24
Finished Aug 28 10:39:26 PM UTC 24
Peak memory 1433992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068190035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1068190035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.2414507076
Short name T271
Test name
Test status
Simulation time 708129382 ps
CPU time 12.35 seconds
Started Aug 28 10:37:08 PM UTC 24
Finished Aug 28 10:37:22 PM UTC 24
Peak memory 216792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414507076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2414507076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_override.1639712087
Short name T1086
Test name
Test status
Simulation time 29310500 ps
CPU time 0.99 seconds
Started Aug 28 10:36:41 PM UTC 24
Finished Aug 28 10:36:43 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639712087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1639712087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_perf.2186593439
Short name T1147
Test name
Test status
Simulation time 7379221768 ps
CPU time 80.93 seconds
Started Aug 28 10:36:44 PM UTC 24
Finished Aug 28 10:38:07 PM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186593439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2186593439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.2679469382
Short name T1095
Test name
Test status
Simulation time 274583163 ps
CPU time 3.45 seconds
Started Aug 28 10:36:44 PM UTC 24
Finished Aug 28 10:36:49 PM UTC 24
Peak memory 226768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679469382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2679469382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.1958254111
Short name T1130
Test name
Test status
Simulation time 2104768104 ps
CPU time 56.93 seconds
Started Aug 28 10:36:40 PM UTC 24
Finished Aug 28 10:37:38 PM UTC 24
Peak memory 325896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958254111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1958254111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.1089908701
Short name T1652
Test name
Test status
Simulation time 182430747391 ps
CPU time 866.12 seconds
Started Aug 28 10:36:47 PM UTC 24
Finished Aug 28 10:51:23 PM UTC 24
Peak memory 3002464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089908701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1089908701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.1774505754
Short name T1099
Test name
Test status
Simulation time 517030562 ps
CPU time 8.45 seconds
Started Aug 28 10:36:44 PM UTC 24
Finished Aug 28 10:36:54 PM UTC 24
Peak memory 233284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774505754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1774505754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.1803357547
Short name T1115
Test name
Test status
Simulation time 1584588209 ps
CPU time 7.01 seconds
Started Aug 28 10:37:07 PM UTC 24
Finished Aug 28 10:37:15 PM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1803357547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_ad
dr.1803357547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.2765505175
Short name T1104
Test name
Test status
Simulation time 227491648 ps
CPU time 1.16 seconds
Started Aug 28 10:37:03 PM UTC 24
Finished Aug 28 10:37:06 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765505
175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.2765505175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.1007359194
Short name T1107
Test name
Test status
Simulation time 376902180 ps
CPU time 2.76 seconds
Started Aug 28 10:37:04 PM UTC 24
Finished Aug 28 10:37:08 PM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007359
194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.1007359194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.4048183891
Short name T1113
Test name
Test status
Simulation time 457516889 ps
CPU time 3.73 seconds
Started Aug 28 10:37:09 PM UTC 24
Finished Aug 28 10:37:14 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048183
891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermar
ks_acq.4048183891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.4020048424
Short name T1111
Test name
Test status
Simulation time 266092464 ps
CPU time 1.96 seconds
Started Aug 28 10:37:10 PM UTC 24
Finished Aug 28 10:37:13 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020048
424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark
s_tx.4020048424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.2137839651
Short name T1109
Test name
Test status
Simulation time 1082332255 ps
CPU time 3.15 seconds
Started Aug 28 10:37:07 PM UTC 24
Finished Aug 28 10:37:11 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137839
651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.2137839651
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.4061235179
Short name T1106
Test name
Test status
Simulation time 2796462694 ps
CPU time 12.15 seconds
Started Aug 28 10:36:54 PM UTC 24
Finished Aug 28 10:37:07 PM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406123
5179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.4061235179
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.1198888877
Short name T1387
Test name
Test status
Simulation time 22431477570 ps
CPU time 373.66 seconds
Started Aug 28 10:36:55 PM UTC 24
Finished Aug 28 10:43:13 PM UTC 24
Peak memory 4120796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1198888877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stres
s_wr.1198888877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.1597013733
Short name T1118
Test name
Test status
Simulation time 1874021004 ps
CPU time 4.09 seconds
Started Aug 28 10:37:12 PM UTC 24
Finished Aug 28 10:37:17 PM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597013
733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.1597013733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.954200976
Short name T1120
Test name
Test status
Simulation time 1150423080 ps
CPU time 5.33 seconds
Started Aug 28 10:37:14 PM UTC 24
Finished Aug 28 10:37:21 PM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9542009
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.954200976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.434076139
Short name T1087
Test name
Test status
Simulation time 690030618 ps
CPU time 1.94 seconds
Started Aug 28 10:37:15 PM UTC 24
Finished Aug 28 10:37:18 PM UTC 24
Peak memory 232860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4340761
39 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.434076139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_perf.24388264
Short name T1114
Test name
Test status
Simulation time 843121581 ps
CPU time 9.35 seconds
Started Aug 28 10:37:04 PM UTC 24
Finished Aug 28 10:37:15 PM UTC 24
Peak memory 233316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438826
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.24388264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.2458529666
Short name T1119
Test name
Test status
Simulation time 1027012159 ps
CPU time 4.6 seconds
Started Aug 28 10:37:12 PM UTC 24
Finished Aug 28 10:37:18 PM UTC 24
Peak memory 216236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458529
666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.2458529666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.3927984101
Short name T1101
Test name
Test status
Simulation time 3126985150 ps
CPU time 13.77 seconds
Started Aug 28 10:36:49 PM UTC 24
Finished Aug 28 10:37:04 PM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927984101 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.3927984101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.3944189797
Short name T1168
Test name
Test status
Simulation time 26220987422 ps
CPU time 83.98 seconds
Started Aug 28 10:37:05 PM UTC 24
Finished Aug 28 10:38:31 PM UTC 24
Peak memory 303316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394418
9797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.3944189797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.2903261315
Short name T1122
Test name
Test status
Simulation time 630606955 ps
CPU time 33.09 seconds
Started Aug 28 10:36:50 PM UTC 24
Finished Aug 28 10:37:24 PM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903261315 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.2903261315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.867210594
Short name T1355
Test name
Test status
Simulation time 49455618698 ps
CPU time 336.94 seconds
Started Aug 28 10:36:50 PM UTC 24
Finished Aug 28 10:42:31 PM UTC 24
Peak memory 3701148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867210594 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.867210594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.3320996057
Short name T1110
Test name
Test status
Simulation time 3204992138 ps
CPU time 18.1 seconds
Started Aug 28 10:36:52 PM UTC 24
Finished Aug 28 10:37:11 PM UTC 24
Peak memory 385180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320996057 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.3320996057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.3214653502
Short name T1108
Test name
Test status
Simulation time 2843691989 ps
CPU time 12.88 seconds
Started Aug 28 10:36:55 PM UTC 24
Finished Aug 28 10:37:09 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214653
502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.3214653502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.282465544
Short name T1116
Test name
Test status
Simulation time 74236280 ps
CPU time 3.08 seconds
Started Aug 28 10:37:12 PM UTC 24
Finished Aug 28 10:37:16 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824655
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.282465544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_alert_test.2713723367
Short name T1153
Test name
Test status
Simulation time 24557147 ps
CPU time 0.97 seconds
Started Aug 28 10:38:07 PM UTC 24
Finished Aug 28 10:38:09 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713723367 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2713723367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.6857636
Short name T1128
Test name
Test status
Simulation time 168293249 ps
CPU time 1.77 seconds
Started Aug 28 10:37:30 PM UTC 24
Finished Aug 28 10:37:33 PM UTC 24
Peak memory 226356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6857636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos
t_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.6857636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.1971727527
Short name T1133
Test name
Test status
Simulation time 372092528 ps
CPU time 21.12 seconds
Started Aug 28 10:37:19 PM UTC 24
Finished Aug 28 10:37:41 PM UTC 24
Peak memory 286916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971727527 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.1971727527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.190316126
Short name T1302
Test name
Test status
Simulation time 6774534297 ps
CPU time 232.79 seconds
Started Aug 28 10:37:22 PM UTC 24
Finished Aug 28 10:41:19 PM UTC 24
Peak memory 745680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190316126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.190316126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.2498053552
Short name T1157
Test name
Test status
Simulation time 13976660704 ps
CPU time 53.11 seconds
Started Aug 28 10:37:19 PM UTC 24
Finished Aug 28 10:38:13 PM UTC 24
Peak memory 747728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498053552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2498053552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.4028620969
Short name T1121
Test name
Test status
Simulation time 196047914 ps
CPU time 1.75 seconds
Started Aug 28 10:37:19 PM UTC 24
Finished Aug 28 10:37:22 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028620969 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.4028620969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.3166773508
Short name T1124
Test name
Test status
Simulation time 1728079171 ps
CPU time 10.18 seconds
Started Aug 28 10:37:20 PM UTC 24
Finished Aug 28 10:37:31 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166773508 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.3166773508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.3390240642
Short name T1189
Test name
Test status
Simulation time 7903274380 ps
CPU time 92.13 seconds
Started Aug 28 10:37:19 PM UTC 24
Finished Aug 28 10:38:53 PM UTC 24
Peak memory 1208404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390240642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3390240642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.1274358404
Short name T1162
Test name
Test status
Simulation time 506827620 ps
CPU time 21.91 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:27 PM UTC 24
Peak memory 216652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274358404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1274358404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_override.3842811658
Short name T1112
Test name
Test status
Simulation time 17665346 ps
CPU time 0.93 seconds
Started Aug 28 10:37:17 PM UTC 24
Finished Aug 28 10:37:19 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842811658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3842811658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_perf.3655472332
Short name T1132
Test name
Test status
Simulation time 2887332575 ps
CPU time 16.75 seconds
Started Aug 28 10:37:22 PM UTC 24
Finished Aug 28 10:37:40 PM UTC 24
Peak memory 235328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655472332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3655472332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.1057299250
Short name T1145
Test name
Test status
Simulation time 2478078308 ps
CPU time 40.62 seconds
Started Aug 28 10:37:23 PM UTC 24
Finished Aug 28 10:38:05 PM UTC 24
Peak memory 237112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057299250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1057299250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.3963969963
Short name T1144
Test name
Test status
Simulation time 1922841882 ps
CPU time 43.96 seconds
Started Aug 28 10:37:16 PM UTC 24
Finished Aug 28 10:38:02 PM UTC 24
Peak memory 413836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963969963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3963969963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.1929475589
Short name T1129
Test name
Test status
Simulation time 2609884555 ps
CPU time 10.37 seconds
Started Aug 28 10:37:25 PM UTC 24
Finished Aug 28 10:37:37 PM UTC 24
Peak memory 229132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929475589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1929475589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.771818221
Short name T1141
Test name
Test status
Simulation time 1168357417 ps
CPU time 7.61 seconds
Started Aug 28 10:37:48 PM UTC 24
Finished Aug 28 10:37:57 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=771818221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.771818221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.1762324529
Short name T1134
Test name
Test status
Simulation time 346825399 ps
CPU time 2.12 seconds
Started Aug 28 10:37:42 PM UTC 24
Finished Aug 28 10:37:45 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762324
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.1762324529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.3041051419
Short name T1136
Test name
Test status
Simulation time 159305250 ps
CPU time 1.35 seconds
Started Aug 28 10:37:45 PM UTC 24
Finished Aug 28 10:37:47 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041051
419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.3041051419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.2990411562
Short name T1152
Test name
Test status
Simulation time 1805130247 ps
CPU time 4.11 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:09 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990411
562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermar
ks_acq.2990411562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.4066734574
Short name T1146
Test name
Test status
Simulation time 531679902 ps
CPU time 2.38 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:07 PM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066734
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_tx.4066734574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.378944871
Short name T1137
Test name
Test status
Simulation time 1317952286 ps
CPU time 11.04 seconds
Started Aug 28 10:37:38 PM UTC 24
Finished Aug 28 10:37:50 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378944
871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.378944871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.506334866
Short name T1172
Test name
Test status
Simulation time 9350469923 ps
CPU time 53.72 seconds
Started Aug 28 10:37:39 PM UTC 24
Finished Aug 28 10:38:34 PM UTC 24
Peak memory 1249684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=506334866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stress
_wr.506334866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.2832957634
Short name T1154
Test name
Test status
Simulation time 10588169509 ps
CPU time 4.27 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:09 PM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832957
634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.2832957634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.252974543
Short name T1150
Test name
Test status
Simulation time 1014283125 ps
CPU time 3.48 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:08 PM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529745
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.252974543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_perf.967684754
Short name T1140
Test name
Test status
Simulation time 789404304 ps
CPU time 7.61 seconds
Started Aug 28 10:37:46 PM UTC 24
Finished Aug 28 10:37:55 PM UTC 24
Peak memory 233580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9676847
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.967684754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.179755151
Short name T1151
Test name
Test status
Simulation time 969203138 ps
CPU time 3.82 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:09 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797551
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.179755151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.3608727260
Short name T1138
Test name
Test status
Simulation time 3191487483 ps
CPU time 18.33 seconds
Started Aug 28 10:37:32 PM UTC 24
Finished Aug 28 10:37:52 PM UTC 24
Peak memory 227124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608727260 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.3608727260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.611333662
Short name T1182
Test name
Test status
Simulation time 78897271779 ps
CPU time 56.99 seconds
Started Aug 28 10:37:46 PM UTC 24
Finished Aug 28 10:38:45 PM UTC 24
Peak memory 254280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611333
662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.611333662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.4011725810
Short name T1142
Test name
Test status
Simulation time 1828342922 ps
CPU time 22.97 seconds
Started Aug 28 10:37:33 PM UTC 24
Finished Aug 28 10:37:58 PM UTC 24
Peak memory 233348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011725810 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.4011725810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2059368438
Short name T1184
Test name
Test status
Simulation time 26447153873 ps
CPU time 69.78 seconds
Started Aug 28 10:37:33 PM UTC 24
Finished Aug 28 10:38:45 PM UTC 24
Peak memory 903320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059368438 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.2059368438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.310274446
Short name T1135
Test name
Test status
Simulation time 3748322728 ps
CPU time 9.44 seconds
Started Aug 28 10:37:35 PM UTC 24
Finished Aug 28 10:37:45 PM UTC 24
Peak memory 264500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310274446 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.310274446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.1286621274
Short name T1139
Test name
Test status
Simulation time 4484542775 ps
CPU time 12.24 seconds
Started Aug 28 10:37:40 PM UTC 24
Finished Aug 28 10:37:53 PM UTC 24
Peak memory 233144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286621
274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.1286621274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.104366356
Short name T1148
Test name
Test status
Simulation time 122487664 ps
CPU time 3.07 seconds
Started Aug 28 10:38:04 PM UTC 24
Finished Aug 28 10:38:08 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043663
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.104366356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_alert_test.2604853936
Short name T1183
Test name
Test status
Simulation time 44129161 ps
CPU time 0.98 seconds
Started Aug 28 10:38:43 PM UTC 24
Finished Aug 28 10:38:45 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604853936 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2604853936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.1649553645
Short name T1163
Test name
Test status
Simulation time 836280737 ps
CPU time 12.98 seconds
Started Aug 28 10:38:13 PM UTC 24
Finished Aug 28 10:38:27 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649553645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1649553645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.1976986193
Short name T1166
Test name
Test status
Simulation time 566607882 ps
CPU time 19.76 seconds
Started Aug 28 10:38:09 PM UTC 24
Finished Aug 28 10:38:30 PM UTC 24
Peak memory 280580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976986193 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.1976986193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.3442876862
Short name T1318
Test name
Test status
Simulation time 2997002734 ps
CPU time 200.41 seconds
Started Aug 28 10:38:10 PM UTC 24
Finished Aug 28 10:41:33 PM UTC 24
Peak memory 727232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442876862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3442876862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2473265221
Short name T1198
Test name
Test status
Simulation time 4195539406 ps
CPU time 68.22 seconds
Started Aug 28 10:38:09 PM UTC 24
Finished Aug 28 10:39:19 PM UTC 24
Peak memory 655564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473265221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2473265221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.2614798027
Short name T1156
Test name
Test status
Simulation time 1102392209 ps
CPU time 1.53 seconds
Started Aug 28 10:38:09 PM UTC 24
Finished Aug 28 10:38:12 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614798027 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.2614798027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.239723368
Short name T1161
Test name
Test status
Simulation time 168114461 ps
CPU time 13.12 seconds
Started Aug 28 10:38:10 PM UTC 24
Finished Aug 28 10:38:24 PM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239723368 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.239723368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.3023485094
Short name T1441
Test name
Test status
Simulation time 5316226170 ps
CPU time 355.08 seconds
Started Aug 28 10:38:08 PM UTC 24
Finished Aug 28 10:44:08 PM UTC 24
Peak memory 1604084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023485094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3023485094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.571021306
Short name T1194
Test name
Test status
Simulation time 2941654567 ps
CPU time 27.44 seconds
Started Aug 28 10:38:34 PM UTC 24
Finished Aug 28 10:39:03 PM UTC 24
Peak memory 216816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571021306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.571021306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_override.778898194
Short name T1155
Test name
Test status
Simulation time 83030173 ps
CPU time 1.02 seconds
Started Aug 28 10:38:08 PM UTC 24
Finished Aug 28 10:38:10 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778898194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.778898194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_perf.1462567121
Short name T1721
Test name
Test status
Simulation time 49950135796 ps
CPU time 699.61 seconds
Started Aug 28 10:38:11 PM UTC 24
Finished Aug 28 10:49:59 PM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462567121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1462567121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3616799054
Short name T1159
Test name
Test status
Simulation time 222571705 ps
CPU time 4.23 seconds
Started Aug 28 10:38:11 PM UTC 24
Finished Aug 28 10:38:16 PM UTC 24
Peak memory 226800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616799054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.3616799054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.2807491151
Short name T1188
Test name
Test status
Simulation time 1668595169 ps
CPU time 41.86 seconds
Started Aug 28 10:38:08 PM UTC 24
Finished Aug 28 10:38:52 PM UTC 24
Peak memory 385416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807491151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2807491151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.370119966
Short name T1160
Test name
Test status
Simulation time 1042693595 ps
CPU time 8.3 seconds
Started Aug 28 10:38:11 PM UTC 24
Finished Aug 28 10:38:20 PM UTC 24
Peak memory 227132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370119966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.370119966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.4280730308
Short name T1177
Test name
Test status
Simulation time 2290201806 ps
CPU time 6.96 seconds
Started Aug 28 10:38:32 PM UTC 24
Finished Aug 28 10:38:40 PM UTC 24
Peak memory 227152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4280730308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_ad
dr.4280730308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.3671430792
Short name T1170
Test name
Test status
Simulation time 462388528 ps
CPU time 1.68 seconds
Started Aug 28 10:38:30 PM UTC 24
Finished Aug 28 10:38:32 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671430
792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.3671430792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.1020882227
Short name T1173
Test name
Test status
Simulation time 220142180 ps
CPU time 1.2 seconds
Started Aug 28 10:38:32 PM UTC 24
Finished Aug 28 10:38:34 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020882
227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.1020882227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.1827585439
Short name T1176
Test name
Test status
Simulation time 797997396 ps
CPU time 2.86 seconds
Started Aug 28 10:38:35 PM UTC 24
Finished Aug 28 10:38:39 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827585
439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermar
ks_acq.1827585439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.1325648293
Short name T1175
Test name
Test status
Simulation time 1109338793 ps
CPU time 2.31 seconds
Started Aug 28 10:38:35 PM UTC 24
Finished Aug 28 10:38:39 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325648
293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.1325648293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.3603084735
Short name T1171
Test name
Test status
Simulation time 15419421448 ps
CPU time 7.55 seconds
Started Aug 28 10:38:24 PM UTC 24
Finished Aug 28 10:38:33 PM UTC 24
Peak memory 231048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360308
4735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.3603084735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.3445897284
Short name T1197
Test name
Test status
Simulation time 13834313247 ps
CPU time 49.94 seconds
Started Aug 28 10:38:27 PM UTC 24
Finished Aug 28 10:39:19 PM UTC 24
Peak memory 962972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3445897284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stres
s_wr.3445897284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.2914858359
Short name T1185
Test name
Test status
Simulation time 899266336 ps
CPU time 3.9 seconds
Started Aug 28 10:38:41 PM UTC 24
Finished Aug 28 10:38:46 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914858
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.2914858359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_perf.2642082300
Short name T1178
Test name
Test status
Simulation time 2862706947 ps
CPU time 8.54 seconds
Started Aug 28 10:38:32 PM UTC 24
Finished Aug 28 10:38:42 PM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642082
300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.2642082300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.46833153
Short name T1181
Test name
Test status
Simulation time 577134670 ps
CPU time 4.51 seconds
Started Aug 28 10:38:38 PM UTC 24
Finished Aug 28 10:38:44 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4683315
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.46833153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.826594483
Short name T1165
Test name
Test status
Simulation time 747364158 ps
CPU time 12.72 seconds
Started Aug 28 10:38:15 PM UTC 24
Finished Aug 28 10:38:29 PM UTC 24
Peak memory 233548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826594483 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.826594483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.1091620366
Short name T1219
Test name
Test status
Simulation time 32604724501 ps
CPU time 56.11 seconds
Started Aug 28 10:38:32 PM UTC 24
Finished Aug 28 10:39:30 PM UTC 24
Peak memory 250092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109162
0366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.1091620366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.3577978895
Short name T1199
Test name
Test status
Simulation time 1294930780 ps
CPU time 56.64 seconds
Started Aug 28 10:38:21 PM UTC 24
Finished Aug 28 10:39:19 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577978895 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.3577978895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.2951386929
Short name T1241
Test name
Test status
Simulation time 38003876918 ps
CPU time 96.26 seconds
Started Aug 28 10:38:17 PM UTC 24
Finished Aug 28 10:39:55 PM UTC 24
Peak memory 1366240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951386929 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.2951386929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.1797571591
Short name T1164
Test name
Test status
Simulation time 1847081552 ps
CPU time 4.67 seconds
Started Aug 28 10:38:21 PM UTC 24
Finished Aug 28 10:38:27 PM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797571591 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.1797571591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2697696734
Short name T1180
Test name
Test status
Simulation time 2473523290 ps
CPU time 13.99 seconds
Started Aug 28 10:38:28 PM UTC 24
Finished Aug 28 10:38:43 PM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697696
734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.2697696734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.444270738
Short name T1179
Test name
Test status
Simulation time 140172755 ps
CPU time 5.09 seconds
Started Aug 28 10:38:36 PM UTC 24
Finished Aug 28 10:38:43 PM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4442707
38 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.444270738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_alert_test.409132123
Short name T1211
Test name
Test status
Simulation time 16528585 ps
CPU time 0.87 seconds
Started Aug 28 10:39:27 PM UTC 24
Finished Aug 28 10:39:28 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409132123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.409132123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.1380028587
Short name T1190
Test name
Test status
Simulation time 83905159 ps
CPU time 2.04 seconds
Started Aug 28 10:38:53 PM UTC 24
Finished Aug 28 10:38:56 PM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380028587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1380028587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.1218762176
Short name T1192
Test name
Test status
Simulation time 838583094 ps
CPU time 13.26 seconds
Started Aug 28 10:38:46 PM UTC 24
Finished Aug 28 10:39:01 PM UTC 24
Peak memory 311640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218762176 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.1218762176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.1661735357
Short name T1303
Test name
Test status
Simulation time 10975387535 ps
CPU time 151.11 seconds
Started Aug 28 10:38:46 PM UTC 24
Finished Aug 28 10:41:20 PM UTC 24
Peak memory 414028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661735357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1661735357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.2523695982
Short name T1232
Test name
Test status
Simulation time 10518226631 ps
CPU time 59.15 seconds
Started Aug 28 10:38:46 PM UTC 24
Finished Aug 28 10:39:47 PM UTC 24
Peak memory 647468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523695982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2523695982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.4249928119
Short name T1187
Test name
Test status
Simulation time 122556658 ps
CPU time 1.6 seconds
Started Aug 28 10:38:46 PM UTC 24
Finished Aug 28 10:38:50 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249928119 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.4249928119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.211314273
Short name T1193
Test name
Test status
Simulation time 937327354 ps
CPU time 15.28 seconds
Started Aug 28 10:38:46 PM UTC 24
Finished Aug 28 10:39:03 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211314273 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.211314273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.1273894734
Short name T1319
Test name
Test status
Simulation time 10503362945 ps
CPU time 165.26 seconds
Started Aug 28 10:38:45 PM UTC 24
Finished Aug 28 10:41:33 PM UTC 24
Peak memory 1517764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273894734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1273894734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.3551512325
Short name T1225
Test name
Test status
Simulation time 1437204021 ps
CPU time 18.18 seconds
Started Aug 28 10:39:21 PM UTC 24
Finished Aug 28 10:39:40 PM UTC 24
Peak memory 216600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551512325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3551512325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_override.3359029240
Short name T1186
Test name
Test status
Simulation time 43927056 ps
CPU time 1.01 seconds
Started Aug 28 10:38:44 PM UTC 24
Finished Aug 28 10:38:46 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359029240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3359029240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_perf.2943890111
Short name T1227
Test name
Test status
Simulation time 6800540007 ps
CPU time 54.61 seconds
Started Aug 28 10:38:47 PM UTC 24
Finished Aug 28 10:39:44 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943890111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2943890111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.3389389477
Short name T1258
Test name
Test status
Simulation time 6151465174 ps
CPU time 77.03 seconds
Started Aug 28 10:38:47 PM UTC 24
Finished Aug 28 10:40:06 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389389477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3389389477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.2860660624
Short name T1257
Test name
Test status
Simulation time 5421820703 ps
CPU time 78.41 seconds
Started Aug 28 10:38:44 PM UTC 24
Finished Aug 28 10:40:04 PM UTC 24
Peak memory 313616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860660624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2860660624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.3715333911
Short name T1205
Test name
Test status
Simulation time 2178706405 ps
CPU time 31.73 seconds
Started Aug 28 10:38:51 PM UTC 24
Finished Aug 28 10:39:24 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715333911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3715333911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.2184613390
Short name T1213
Test name
Test status
Simulation time 1007726368 ps
CPU time 7.94 seconds
Started Aug 28 10:39:20 PM UTC 24
Finished Aug 28 10:39:29 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2184613390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_ad
dr.2184613390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.135286120
Short name T1196
Test name
Test status
Simulation time 378926411 ps
CPU time 2.93 seconds
Started Aug 28 10:39:14 PM UTC 24
Finished Aug 28 10:39:18 PM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352861
20 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.135286120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.2749027897
Short name T1202
Test name
Test status
Simulation time 420079445 ps
CPU time 1.55 seconds
Started Aug 28 10:39:19 PM UTC 24
Finished Aug 28 10:39:21 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749027
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.2749027897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.1020452310
Short name T1210
Test name
Test status
Simulation time 2968939537 ps
CPU time 3.44 seconds
Started Aug 28 10:39:22 PM UTC 24
Finished Aug 28 10:39:26 PM UTC 24
Peak memory 216716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020452
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermar
ks_acq.1020452310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.2071149100
Short name T1208
Test name
Test status
Simulation time 202685702 ps
CPU time 2.5 seconds
Started Aug 28 10:39:22 PM UTC 24
Finished Aug 28 10:39:26 PM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071149
100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.2071149100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_hrst.1771394348
Short name T1206
Test name
Test status
Simulation time 1577007210 ps
CPU time 3.72 seconds
Started Aug 28 10:39:20 PM UTC 24
Finished Aug 28 10:39:25 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771394
348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_hrst.1771394348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.1950526231
Short name T1200
Test name
Test status
Simulation time 2915609932 ps
CPU time 14.63 seconds
Started Aug 28 10:39:04 PM UTC 24
Finished Aug 28 10:39:20 PM UTC 24
Peak memory 223072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195052
6231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.1950526231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3824554647
Short name T1284
Test name
Test status
Simulation time 13450928496 ps
CPU time 97.15 seconds
Started Aug 28 10:39:04 PM UTC 24
Finished Aug 28 10:40:43 PM UTC 24
Peak memory 1779932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3824554647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.3824554647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.2119672533
Short name T1218
Test name
Test status
Simulation time 983553187 ps
CPU time 4.72 seconds
Started Aug 28 10:39:24 PM UTC 24
Finished Aug 28 10:39:30 PM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119672
533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.2119672533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.2279441341
Short name T1216
Test name
Test status
Simulation time 406757070 ps
CPU time 3.49 seconds
Started Aug 28 10:39:25 PM UTC 24
Finished Aug 28 10:39:30 PM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279441
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_ad
dr.2279441341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_perf.3545161168
Short name T1207
Test name
Test status
Simulation time 492357928 ps
CPU time 5.47 seconds
Started Aug 28 10:39:19 PM UTC 24
Finished Aug 28 10:39:25 PM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545161
168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.3545161168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.328108528
Short name T1217
Test name
Test status
Simulation time 516885584 ps
CPU time 4.8 seconds
Started Aug 28 10:39:24 PM UTC 24
Finished Aug 28 10:39:30 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281085
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.328108528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.3511815713
Short name T1149
Test name
Test status
Simulation time 3962751572 ps
CPU time 20.19 seconds
Started Aug 28 10:38:57 PM UTC 24
Finished Aug 28 10:39:18 PM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511815713 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.3511815713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2059746291
Short name T1356
Test name
Test status
Simulation time 37135984399 ps
CPU time 188.54 seconds
Started Aug 28 10:39:20 PM UTC 24
Finished Aug 28 10:42:31 PM UTC 24
Peak memory 1759460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205974
6291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.2059746291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.1512040725
Short name T1203
Test name
Test status
Simulation time 944823592 ps
CPU time 18.91 seconds
Started Aug 28 10:39:02 PM UTC 24
Finished Aug 28 10:39:22 PM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512040725 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.1512040725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.1494753177
Short name T1388
Test name
Test status
Simulation time 60723582158 ps
CPU time 252.62 seconds
Started Aug 28 10:39:01 PM UTC 24
Finished Aug 28 10:43:17 PM UTC 24
Peak memory 3125476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494753177 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.1494753177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.3141015778
Short name T1215
Test name
Test status
Simulation time 646876163 ps
CPU time 25.79 seconds
Started Aug 28 10:39:02 PM UTC 24
Finished Aug 28 10:39:29 PM UTC 24
Peak memory 327676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141015778 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.3141015778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.1479887165
Short name T1201
Test name
Test status
Simulation time 5620249628 ps
CPU time 12.49 seconds
Started Aug 28 10:39:07 PM UTC 24
Finished Aug 28 10:39:21 PM UTC 24
Peak memory 244112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479887
165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.1479887165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.1251845273
Short name T1223
Test name
Test status
Simulation time 615665078 ps
CPU time 13.61 seconds
Started Aug 28 10:39:23 PM UTC 24
Finished Aug 28 10:39:38 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251845
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.1251845273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_alert_test.4163463051
Short name T1249
Test name
Test status
Simulation time 18886504 ps
CPU time 0.92 seconds
Started Aug 28 10:39:56 PM UTC 24
Finished Aug 28 10:39:58 PM UTC 24
Peak memory 215292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163463051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.4163463051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.2412062399
Short name T1224
Test name
Test status
Simulation time 273486736 ps
CPU time 5.45 seconds
Started Aug 28 10:39:31 PM UTC 24
Finished Aug 28 10:39:38 PM UTC 24
Peak memory 250052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412062399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2412062399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.1570840504
Short name T1228
Test name
Test status
Simulation time 478288944 ps
CPU time 12.59 seconds
Started Aug 28 10:39:30 PM UTC 24
Finished Aug 28 10:39:44 PM UTC 24
Peak memory 325628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570840504 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.1570840504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.332588236
Short name T1403
Test name
Test status
Simulation time 13957280499 ps
CPU time 238.58 seconds
Started Aug 28 10:39:30 PM UTC 24
Finished Aug 28 10:43:33 PM UTC 24
Peak memory 772368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332588236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.332588236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.2555272650
Short name T1281
Test name
Test status
Simulation time 8786817748 ps
CPU time 69.53 seconds
Started Aug 28 10:39:29 PM UTC 24
Finished Aug 28 10:40:40 PM UTC 24
Peak memory 733336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555272650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2555272650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.4264859332
Short name T1220
Test name
Test status
Simulation time 138870760 ps
CPU time 2.03 seconds
Started Aug 28 10:39:30 PM UTC 24
Finished Aug 28 10:39:33 PM UTC 24
Peak memory 216248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264859332 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.4264859332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.1910924797
Short name T1229
Test name
Test status
Simulation time 184855315 ps
CPU time 12.49 seconds
Started Aug 28 10:39:30 PM UTC 24
Finished Aug 28 10:39:44 PM UTC 24
Peak memory 252296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910924797 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.1910924797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.4181841735
Short name T1453
Test name
Test status
Simulation time 5308846863 ps
CPU time 284.57 seconds
Started Aug 28 10:39:28 PM UTC 24
Finished Aug 28 10:44:16 PM UTC 24
Peak memory 1382536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181841735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4181841735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1635797710
Short name T1245
Test name
Test status
Simulation time 300158403 ps
CPU time 4.69 seconds
Started Aug 28 10:39:51 PM UTC 24
Finished Aug 28 10:39:56 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635797710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1635797710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_mode_toggle.2436144749
Short name T84
Test name
Test status
Simulation time 178286471 ps
CPU time 2.28 seconds
Started Aug 28 10:39:50 PM UTC 24
Finished Aug 28 10:39:53 PM UTC 24
Peak memory 227024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436144749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2436144749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_override.413018103
Short name T1212
Test name
Test status
Simulation time 18347547 ps
CPU time 0.96 seconds
Started Aug 28 10:39:27 PM UTC 24
Finished Aug 28 10:39:29 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413018103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.413018103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_perf.2026602802
Short name T1235
Test name
Test status
Simulation time 4147796969 ps
CPU time 17.01 seconds
Started Aug 28 10:39:31 PM UTC 24
Finished Aug 28 10:39:49 PM UTC 24
Peak memory 282432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026602802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2026602802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.2131110132
Short name T1221
Test name
Test status
Simulation time 79889199 ps
CPU time 1.85 seconds
Started Aug 28 10:39:31 PM UTC 24
Finished Aug 28 10:39:34 PM UTC 24
Peak memory 226028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131110132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2131110132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.305287873
Short name T1285
Test name
Test status
Simulation time 4708933637 ps
CPU time 78.76 seconds
Started Aug 28 10:39:27 PM UTC 24
Finished Aug 28 10:40:47 PM UTC 24
Peak memory 282900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305287873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.305287873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.4080321490
Short name T1231
Test name
Test status
Simulation time 2143442981 ps
CPU time 14.24 seconds
Started Aug 28 10:39:31 PM UTC 24
Finished Aug 28 10:39:47 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080321490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.4080321490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.1947185522
Short name T1243
Test name
Test status
Simulation time 2249433909 ps
CPU time 6.07 seconds
Started Aug 28 10:39:48 PM UTC 24
Finished Aug 28 10:39:55 PM UTC 24
Peak memory 233644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1947185522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_ad
dr.1947185522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.1305303293
Short name T1233
Test name
Test status
Simulation time 370737578 ps
CPU time 1.17 seconds
Started Aug 28 10:39:45 PM UTC 24
Finished Aug 28 10:39:47 PM UTC 24
Peak memory 226548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305303
293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.1305303293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.2972343245
Short name T1236
Test name
Test status
Simulation time 274225822 ps
CPU time 2.96 seconds
Started Aug 28 10:39:46 PM UTC 24
Finished Aug 28 10:39:50 PM UTC 24
Peak memory 216844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972343
245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.2972343245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.2087393209
Short name T1244
Test name
Test status
Simulation time 600774889 ps
CPU time 4.36 seconds
Started Aug 28 10:39:51 PM UTC 24
Finished Aug 28 10:39:56 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087393
209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermar
ks_acq.2087393209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.691653965
Short name T1240
Test name
Test status
Simulation time 106607493 ps
CPU time 1.72 seconds
Started Aug 28 10:39:52 PM UTC 24
Finished Aug 28 10:39:55 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6916539
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermarks
_tx.691653965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.614096786
Short name T1237
Test name
Test status
Simulation time 1179557963 ps
CPU time 8.96 seconds
Started Aug 28 10:39:41 PM UTC 24
Finished Aug 28 10:39:51 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614096
786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.614096786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.2076532252
Short name T1246
Test name
Test status
Simulation time 15807430688 ps
CPU time 12.79 seconds
Started Aug 28 10:39:43 PM UTC 24
Finished Aug 28 10:39:57 PM UTC 24
Peak memory 237776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2076532252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stres
s_wr.2076532252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.662471048
Short name T1252
Test name
Test status
Simulation time 529241169 ps
CPU time 3.32 seconds
Started Aug 28 10:39:55 PM UTC 24
Finished Aug 28 10:39:59 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6624710
48 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.662471048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.729007702
Short name T1255
Test name
Test status
Simulation time 518279003 ps
CPU time 4.52 seconds
Started Aug 28 10:39:55 PM UTC 24
Finished Aug 28 10:40:01 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7290077
02 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.729007702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_nack_txstretch.2133543706
Short name T1253
Test name
Test status
Simulation time 521055396 ps
CPU time 2.38 seconds
Started Aug 28 10:39:56 PM UTC 24
Finished Aug 28 10:40:00 PM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133543
706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_txstretch.2133543706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3552908271
Short name T1239
Test name
Test status
Simulation time 2750619604 ps
CPU time 5.4 seconds
Started Aug 28 10:39:47 PM UTC 24
Finished Aug 28 10:39:54 PM UTC 24
Peak memory 227144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552908
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.3552908271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.1487751470
Short name T1250
Test name
Test status
Simulation time 509130827 ps
CPU time 4.39 seconds
Started Aug 28 10:39:54 PM UTC 24
Finished Aug 28 10:39:59 PM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487751
470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.1487751470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.1811718770
Short name T1248
Test name
Test status
Simulation time 1344393602 ps
CPU time 20.56 seconds
Started Aug 28 10:39:36 PM UTC 24
Finished Aug 28 10:39:57 PM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811718770 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.1811718770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.2913988095
Short name T1400
Test name
Test status
Simulation time 22035504520 ps
CPU time 220.6 seconds
Started Aug 28 10:39:48 PM UTC 24
Finished Aug 28 10:43:32 PM UTC 24
Peak memory 2361812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291398
8095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.2913988095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.2508119355
Short name T1230
Test name
Test status
Simulation time 326025136 ps
CPU time 5.15 seconds
Started Aug 28 10:39:39 PM UTC 24
Finished Aug 28 10:39:45 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508119355 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.2508119355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.1928697779
Short name T1297
Test name
Test status
Simulation time 23854674646 ps
CPU time 96.45 seconds
Started Aug 28 10:39:36 PM UTC 24
Finished Aug 28 10:41:14 PM UTC 24
Peak memory 1052824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928697779 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.1928697779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.1014926482
Short name T1234
Test name
Test status
Simulation time 1263210360 ps
CPU time 7.92 seconds
Started Aug 28 10:39:39 PM UTC 24
Finished Aug 28 10:39:48 PM UTC 24
Peak memory 342092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014926482 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.1014926482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.3270370869
Short name T1242
Test name
Test status
Simulation time 4223044202 ps
CPU time 9.33 seconds
Started Aug 28 10:39:45 PM UTC 24
Finished Aug 28 10:39:55 PM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270370
869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.3270370869
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.3825518707
Short name T1247
Test name
Test status
Simulation time 50785880 ps
CPU time 2.09 seconds
Started Aug 28 10:39:54 PM UTC 24
Finished Aug 28 10:39:57 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825518
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.3825518707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_alert_test.1667970822
Short name T1277
Test name
Test status
Simulation time 35315213 ps
CPU time 1.02 seconds
Started Aug 28 10:40:36 PM UTC 24
Finished Aug 28 10:40:38 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667970822 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1667970822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.64886278
Short name T1259
Test name
Test status
Simulation time 311079505 ps
CPU time 5.19 seconds
Started Aug 28 10:40:01 PM UTC 24
Finished Aug 28 10:40:07 PM UTC 24
Peak memory 245864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64886278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.64886278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.3734228187
Short name T1260
Test name
Test status
Simulation time 526207833 ps
CPU time 10.73 seconds
Started Aug 28 10:39:59 PM UTC 24
Finished Aug 28 10:40:11 PM UTC 24
Peak memory 303240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734228187 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.3734228187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.1255378895
Short name T1407
Test name
Test status
Simulation time 3253881860 ps
CPU time 212.65 seconds
Started Aug 28 10:40:00 PM UTC 24
Finished Aug 28 10:43:36 PM UTC 24
Peak memory 737448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255378895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1255378895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.1300891031
Short name T1342
Test name
Test status
Simulation time 2244840038 ps
CPU time 130.76 seconds
Started Aug 28 10:39:57 PM UTC 24
Finished Aug 28 10:42:10 PM UTC 24
Peak memory 721104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300891031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1300891031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.2663358747
Short name T1254
Test name
Test status
Simulation time 117601840 ps
CPU time 1.78 seconds
Started Aug 28 10:39:58 PM UTC 24
Finished Aug 28 10:40:00 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663358747 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.2663358747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.2859050457
Short name T1263
Test name
Test status
Simulation time 993754956 ps
CPU time 17.08 seconds
Started Aug 28 10:39:59 PM UTC 24
Finished Aug 28 10:40:17 PM UTC 24
Peak memory 268572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859050457 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.2859050457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.1514528517
Short name T1289
Test name
Test status
Simulation time 5974435130 ps
CPU time 63.13 seconds
Started Aug 28 10:39:57 PM UTC 24
Finished Aug 28 10:41:02 PM UTC 24
Peak memory 979380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514528517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1514528517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.25983738
Short name T291
Test name
Test status
Simulation time 429181004 ps
CPU time 6.73 seconds
Started Aug 28 10:40:21 PM UTC 24
Finished Aug 28 10:40:29 PM UTC 24
Peak memory 216684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25983738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.25983738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_override.1355617696
Short name T1251
Test name
Test status
Simulation time 131267157 ps
CPU time 0.99 seconds
Started Aug 28 10:39:57 PM UTC 24
Finished Aug 28 10:39:59 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355617696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1355617696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_perf.1447828144
Short name T1267
Test name
Test status
Simulation time 4779658496 ps
CPU time 19.16 seconds
Started Aug 28 10:40:00 PM UTC 24
Finished Aug 28 10:40:20 PM UTC 24
Peak memory 329880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447828144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1447828144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.1640769456
Short name T1256
Test name
Test status
Simulation time 308537604 ps
CPU time 2.19 seconds
Started Aug 28 10:40:00 PM UTC 24
Finished Aug 28 10:40:03 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640769456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1640769456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.832348398
Short name T1278
Test name
Test status
Simulation time 1836977915 ps
CPU time 40.57 seconds
Started Aug 28 10:39:56 PM UTC 24
Finished Aug 28 10:40:38 PM UTC 24
Peak memory 364628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832348398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.832348398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.2346716829
Short name T292
Test name
Test status
Simulation time 2942778386 ps
CPU time 37.22 seconds
Started Aug 28 10:40:00 PM UTC 24
Finished Aug 28 10:40:39 PM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346716829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2346716829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.1934483884
Short name T1273
Test name
Test status
Simulation time 2211451394 ps
CPU time 9.63 seconds
Started Aug 28 10:40:20 PM UTC 24
Finished Aug 28 10:40:31 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1934483884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.1934483884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.4205301589
Short name T1268
Test name
Test status
Simulation time 397158170 ps
CPU time 1.46 seconds
Started Aug 28 10:40:18 PM UTC 24
Finished Aug 28 10:40:20 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205301
589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.4205301589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.1140690268
Short name T1269
Test name
Test status
Simulation time 226679825 ps
CPU time 1.45 seconds
Started Aug 28 10:40:18 PM UTC 24
Finished Aug 28 10:40:20 PM UTC 24
Peak memory 215124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140690
268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.1140690268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.1898762902
Short name T1214
Test name
Test status
Simulation time 437482030 ps
CPU time 3.68 seconds
Started Aug 28 10:40:23 PM UTC 24
Finished Aug 28 10:40:28 PM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898762
902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar
ks_acq.1898762902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.2725243151
Short name T1272
Test name
Test status
Simulation time 871590831 ps
CPU time 1.87 seconds
Started Aug 28 10:40:25 PM UTC 24
Finished Aug 28 10:40:29 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725243
151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermark
s_tx.2725243151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.179704087
Short name T1266
Test name
Test status
Simulation time 4055998261 ps
CPU time 9.2 seconds
Started Aug 28 10:40:09 PM UTC 24
Finished Aug 28 10:40:19 PM UTC 24
Peak memory 231284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179704
087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.179704087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.2376349954
Short name T1581
Test name
Test status
Simulation time 28437750414 ps
CPU time 384.5 seconds
Started Aug 28 10:40:12 PM UTC 24
Finished Aug 28 10:46:41 PM UTC 24
Peak memory 5806232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2376349954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stres
s_wr.2376349954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.76988469
Short name T60
Test name
Test status
Simulation time 600854461 ps
CPU time 5.7 seconds
Started Aug 28 10:40:31 PM UTC 24
Finished Aug 28 10:40:38 PM UTC 24
Peak memory 226780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7698846
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.76988469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.3237775780
Short name T1276
Test name
Test status
Simulation time 552794675 ps
CPU time 5.39 seconds
Started Aug 28 10:40:31 PM UTC 24
Finished Aug 28 10:40:37 PM UTC 24
Peak memory 216420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237775
780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.3237775780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.399050326
Short name T1275
Test name
Test status
Simulation time 178765378 ps
CPU time 2.26 seconds
Started Aug 28 10:40:32 PM UTC 24
Finished Aug 28 10:40:35 PM UTC 24
Peak memory 233540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990503
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_txstretch.399050326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_perf.3092413458
Short name T1271
Test name
Test status
Simulation time 585253085 ps
CPU time 5.32 seconds
Started Aug 28 10:40:18 PM UTC 24
Finished Aug 28 10:40:24 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092413
458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.3092413458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.1954099716
Short name T1274
Test name
Test status
Simulation time 402091213 ps
CPU time 3.82 seconds
Started Aug 28 10:40:30 PM UTC 24
Finished Aug 28 10:40:35 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954099
716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.1954099716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.1203618908
Short name T1261
Test name
Test status
Simulation time 390844327 ps
CPU time 8.73 seconds
Started Aug 28 10:40:01 PM UTC 24
Finished Aug 28 10:40:11 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203618908 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.1203618908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2586613047
Short name T1322
Test name
Test status
Simulation time 53061493406 ps
CPU time 81.85 seconds
Started Aug 28 10:40:19 PM UTC 24
Finished Aug 28 10:41:43 PM UTC 24
Peak memory 518560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258661
3047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.2586613047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.1114955373
Short name T1298
Test name
Test status
Simulation time 1280418947 ps
CPU time 67.85 seconds
Started Aug 28 10:40:05 PM UTC 24
Finished Aug 28 10:41:15 PM UTC 24
Peak memory 230856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114955373 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.1114955373
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.2606141406
Short name T1264
Test name
Test status
Simulation time 10872722251 ps
CPU time 11.51 seconds
Started Aug 28 10:40:04 PM UTC 24
Finished Aug 28 10:40:17 PM UTC 24
Peak memory 216720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606141406 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.2606141406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.745702613
Short name T1265
Test name
Test status
Simulation time 1658006517 ps
CPU time 9.9 seconds
Started Aug 28 10:40:07 PM UTC 24
Finished Aug 28 10:40:19 PM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745702613 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.745702613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.396958961
Short name T1270
Test name
Test status
Simulation time 16249082010 ps
CPU time 9.73 seconds
Started Aug 28 10:40:12 PM UTC 24
Finished Aug 28 10:40:23 PM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969589
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.396958961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.3102226299
Short name T1280
Test name
Test status
Simulation time 337255518 ps
CPU time 9.4 seconds
Started Aug 28 10:40:30 PM UTC 24
Finished Aug 28 10:40:40 PM UTC 24
Peak memory 229068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102226
299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.3102226299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_alert_test.2898362788
Short name T1308
Test name
Test status
Simulation time 17224548 ps
CPU time 0.94 seconds
Started Aug 28 10:41:23 PM UTC 24
Finished Aug 28 10:41:24 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898362788 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2898362788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.1036473742
Short name T1288
Test name
Test status
Simulation time 108467848 ps
CPU time 3.03 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 10:40:57 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036473742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1036473742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.2989364492
Short name T1287
Test name
Test status
Simulation time 2094973903 ps
CPU time 8.63 seconds
Started Aug 28 10:40:39 PM UTC 24
Finished Aug 28 10:40:49 PM UTC 24
Peak memory 335968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989364492 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.2989364492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.1381869784
Short name T1483
Test name
Test status
Simulation time 8340565764 ps
CPU time 224.34 seconds
Started Aug 28 10:40:51 PM UTC 24
Finished Aug 28 10:44:39 PM UTC 24
Peak memory 813260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381869784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1381869784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.2157999807
Short name T1329
Test name
Test status
Simulation time 5595054403 ps
CPU time 78.04 seconds
Started Aug 28 10:40:39 PM UTC 24
Finished Aug 28 10:41:59 PM UTC 24
Peak memory 526612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157999807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2157999807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.785893435
Short name T1283
Test name
Test status
Simulation time 341027183 ps
CPU time 1.68 seconds
Started Aug 28 10:40:39 PM UTC 24
Finished Aug 28 10:40:42 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785893435 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.785893435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.1067543196
Short name T1286
Test name
Test status
Simulation time 377107219 ps
CPU time 6.5 seconds
Started Aug 28 10:40:40 PM UTC 24
Finished Aug 28 10:40:48 PM UTC 24
Peak memory 216884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067543196 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.1067543196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1766504504
Short name T1457
Test name
Test status
Simulation time 3433534725 ps
CPU time 221.25 seconds
Started Aug 28 10:40:38 PM UTC 24
Finished Aug 28 10:44:23 PM UTC 24
Peak memory 976988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766504504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1766504504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.2346186200
Short name T1320
Test name
Test status
Simulation time 314822254 ps
CPU time 16.18 seconds
Started Aug 28 10:41:16 PM UTC 24
Finished Aug 28 10:41:34 PM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346186200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2346186200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_override.243904369
Short name T1279
Test name
Test status
Simulation time 17568066 ps
CPU time 1 seconds
Started Aug 28 10:40:38 PM UTC 24
Finished Aug 28 10:40:40 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243904369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.243904369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_perf.244130402
Short name T1430
Test name
Test status
Simulation time 9499522967 ps
CPU time 248.36 seconds
Started Aug 28 10:40:52 PM UTC 24
Finished Aug 28 10:45:03 PM UTC 24
Peak memory 1909156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244130402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.244130402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.458417310
Short name T1353
Test name
Test status
Simulation time 5901729806 ps
CPU time 95.2 seconds
Started Aug 28 10:40:52 PM UTC 24
Finished Aug 28 10:42:29 PM UTC 24
Peak memory 226828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458417310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.458417310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.396102956
Short name T1345
Test name
Test status
Simulation time 7189835545 ps
CPU time 97.39 seconds
Started Aug 28 10:40:36 PM UTC 24
Finished Aug 28 10:42:15 PM UTC 24
Peak memory 364768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396102956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.396102956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_stress_all.3381642614
Short name T1738
Test name
Test status
Simulation time 64932366543 ps
CPU time 1506.72 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 11:06:15 PM UTC 24
Peak memory 2609292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381642614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3381642614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.3407956212
Short name T1293
Test name
Test status
Simulation time 883160142 ps
CPU time 16.89 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 10:41:11 PM UTC 24
Peak memory 233336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407956212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3407956212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.3329490672
Short name T1311
Test name
Test status
Simulation time 5539323041 ps
CPU time 11.9 seconds
Started Aug 28 10:41:13 PM UTC 24
Finished Aug 28 10:41:26 PM UTC 24
Peak memory 231028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3329490672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad
dr.3329490672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.1142115170
Short name T1296
Test name
Test status
Simulation time 609728861 ps
CPU time 2.39 seconds
Started Aug 28 10:41:09 PM UTC 24
Finished Aug 28 10:41:12 PM UTC 24
Peak memory 216512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142115
170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.1142115170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.1884950567
Short name T1299
Test name
Test status
Simulation time 1090374305 ps
CPU time 3.15 seconds
Started Aug 28 10:41:12 PM UTC 24
Finished Aug 28 10:41:16 PM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884950
567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.1884950567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.461471683
Short name T1306
Test name
Test status
Simulation time 461964818 ps
CPU time 4.22 seconds
Started Aug 28 10:41:17 PM UTC 24
Finished Aug 28 10:41:22 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4614716
83 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermark
s_acq.461471683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.227897276
Short name T1305
Test name
Test status
Simulation time 614088790 ps
CPU time 1.73 seconds
Started Aug 28 10:41:19 PM UTC 24
Finished Aug 28 10:41:22 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278972
76 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermarks
_tx.227897276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.2755173302
Short name T1291
Test name
Test status
Simulation time 909867508 ps
CPU time 8.27 seconds
Started Aug 28 10:40:58 PM UTC 24
Finished Aug 28 10:41:07 PM UTC 24
Peak memory 233012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275517
3302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.2755173302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.2092968499
Short name T1618
Test name
Test status
Simulation time 20730498805 ps
CPU time 369.2 seconds
Started Aug 28 10:41:03 PM UTC 24
Finished Aug 28 10:47:17 PM UTC 24
Peak memory 5007504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2092968499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres
s_wr.2092968499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.1062682125
Short name T1310
Test name
Test status
Simulation time 1212738443 ps
CPU time 4.05 seconds
Started Aug 28 10:41:20 PM UTC 24
Finished Aug 28 10:41:25 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062682
125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.1062682125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.3822579156
Short name T1312
Test name
Test status
Simulation time 568793429 ps
CPU time 3.49 seconds
Started Aug 28 10:41:21 PM UTC 24
Finished Aug 28 10:41:26 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822579
156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad
dr.3822579156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_nack_txstretch.4012667478
Short name T1309
Test name
Test status
Simulation time 507008998 ps
CPU time 1.9 seconds
Started Aug 28 10:41:23 PM UTC 24
Finished Aug 28 10:41:25 PM UTC 24
Peak memory 232684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012667
478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_txstretch.4012667478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_perf.182028128
Short name T1301
Test name
Test status
Simulation time 405099368 ps
CPU time 5.46 seconds
Started Aug 28 10:41:12 PM UTC 24
Finished Aug 28 10:41:18 PM UTC 24
Peak memory 233504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820281
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.182028128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.2769919425
Short name T1307
Test name
Test status
Simulation time 432708161 ps
CPU time 3.97 seconds
Started Aug 28 10:41:19 PM UTC 24
Finished Aug 28 10:41:24 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769919
425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.2769919425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.2720263973
Short name T1295
Test name
Test status
Simulation time 5489173997 ps
CPU time 17.54 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 10:41:12 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720263973 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.2720263973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.2113482611
Short name T1454
Test name
Test status
Simulation time 36356578421 ps
CPU time 182.47 seconds
Started Aug 28 10:41:13 PM UTC 24
Finished Aug 28 10:44:18 PM UTC 24
Peak memory 2068640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211348
2611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.2113482611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.3681191214
Short name T1292
Test name
Test status
Simulation time 660935442 ps
CPU time 13.94 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 10:41:08 PM UTC 24
Peak memory 228848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681191214 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.3681191214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.1095658326
Short name T1651
Test name
Test status
Simulation time 38191505045 ps
CPU time 429.21 seconds
Started Aug 28 10:40:53 PM UTC 24
Finished Aug 28 10:48:07 PM UTC 24
Peak memory 4759960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095658326 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.1095658326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.4125467827
Short name T1294
Test name
Test status
Simulation time 4233989943 ps
CPU time 11.86 seconds
Started Aug 28 10:40:58 PM UTC 24
Finished Aug 28 10:41:11 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125467827 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.4125467827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3879829998
Short name T1300
Test name
Test status
Simulation time 1346180489 ps
CPU time 9.52 seconds
Started Aug 28 10:41:07 PM UTC 24
Finished Aug 28 10:41:18 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879829
998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3879829998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_alert_test.1900375448
Short name T1338
Test name
Test status
Simulation time 26005878 ps
CPU time 0.9 seconds
Started Aug 28 10:42:07 PM UTC 24
Finished Aug 28 10:42:08 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900375448 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1900375448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.464280186
Short name T1317
Test name
Test status
Simulation time 275926012 ps
CPU time 2.23 seconds
Started Aug 28 10:41:30 PM UTC 24
Finished Aug 28 10:41:33 PM UTC 24
Peak memory 227084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464280186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.464280186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.2660274048
Short name T1331
Test name
Test status
Simulation time 1017817442 ps
CPU time 34.09 seconds
Started Aug 28 10:41:27 PM UTC 24
Finished Aug 28 10:42:03 PM UTC 24
Peak memory 319196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660274048 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.2660274048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.1390525637
Short name T1368
Test name
Test status
Simulation time 9309821469 ps
CPU time 78.8 seconds
Started Aug 28 10:41:27 PM UTC 24
Finished Aug 28 10:42:48 PM UTC 24
Peak memory 413764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390525637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1390525637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.3025164803
Short name T1354
Test name
Test status
Simulation time 9143493944 ps
CPU time 61.36 seconds
Started Aug 28 10:41:26 PM UTC 24
Finished Aug 28 10:42:29 PM UTC 24
Peak memory 584204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025164803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.3025164803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.1148995405
Short name T1315
Test name
Test status
Simulation time 131696918 ps
CPU time 1.94 seconds
Started Aug 28 10:41:26 PM UTC 24
Finished Aug 28 10:41:29 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148995405 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.1148995405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.3839007667
Short name T1321
Test name
Test status
Simulation time 593941917 ps
CPU time 10.09 seconds
Started Aug 28 10:41:27 PM UTC 24
Finished Aug 28 10:41:38 PM UTC 24
Peak memory 216088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839007667 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.3839007667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.3269791222
Short name T1518
Test name
Test status
Simulation time 3610366209 ps
CPU time 246.24 seconds
Started Aug 28 10:41:25 PM UTC 24
Finished Aug 28 10:45:35 PM UTC 24
Peak memory 1110228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269791222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3269791222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.3583592036
Short name T1352
Test name
Test status
Simulation time 495331324 ps
CPU time 25.81 seconds
Started Aug 28 10:41:59 PM UTC 24
Finished Aug 28 10:42:26 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583592036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3583592036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_override.3692615760
Short name T1313
Test name
Test status
Simulation time 164443861 ps
CPU time 0.94 seconds
Started Aug 28 10:41:25 PM UTC 24
Finished Aug 28 10:41:27 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692615760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3692615760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_perf.3709841628
Short name T1337
Test name
Test status
Simulation time 2606229677 ps
CPU time 39.04 seconds
Started Aug 28 10:41:27 PM UTC 24
Finished Aug 28 10:42:08 PM UTC 24
Peak memory 577504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709841628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3709841628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.1084935686
Short name T1316
Test name
Test status
Simulation time 62906012 ps
CPU time 4.21 seconds
Started Aug 28 10:41:27 PM UTC 24
Finished Aug 28 10:41:33 PM UTC 24
Peak memory 233012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084935686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1084935686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.516297577
Short name T1323
Test name
Test status
Simulation time 1062906879 ps
CPU time 21.65 seconds
Started Aug 28 10:41:24 PM UTC 24
Finished Aug 28 10:41:47 PM UTC 24
Peak memory 350280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516297577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.516297577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.32172330
Short name T1336
Test name
Test status
Simulation time 802124543 ps
CPU time 36.75 seconds
Started Aug 28 10:41:28 PM UTC 24
Finished Aug 28 10:42:07 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32172330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.32172330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.3660127318
Short name T1330
Test name
Test status
Simulation time 2454210248 ps
CPU time 4.61 seconds
Started Aug 28 10:41:56 PM UTC 24
Finished Aug 28 10:42:02 PM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3660127318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_ad
dr.3660127318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.346976177
Short name T1327
Test name
Test status
Simulation time 183639392 ps
CPU time 1.71 seconds
Started Aug 28 10:41:52 PM UTC 24
Finished Aug 28 10:41:55 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469761
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.346976177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1529759540
Short name T1326
Test name
Test status
Simulation time 458962996 ps
CPU time 1.61 seconds
Started Aug 28 10:41:52 PM UTC 24
Finished Aug 28 10:41:55 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529759
540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.1529759540
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.2889397391
Short name T1334
Test name
Test status
Simulation time 2037023333 ps
CPU time 4.42 seconds
Started Aug 28 10:42:00 PM UTC 24
Finished Aug 28 10:42:06 PM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889397
391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar
ks_acq.2889397391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.2463812594
Short name T1333
Test name
Test status
Simulation time 319314319 ps
CPU time 1.52 seconds
Started Aug 28 10:42:02 PM UTC 24
Finished Aug 28 10:42:05 PM UTC 24
Peak memory 215028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463812
594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.2463812594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.2957606983
Short name T1324
Test name
Test status
Simulation time 946543359 ps
CPU time 7.4 seconds
Started Aug 28 10:41:39 PM UTC 24
Finished Aug 28 10:41:47 PM UTC 24
Peak memory 233068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295760
6983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.2957606983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.1970273123
Short name T1335
Test name
Test status
Simulation time 11439835225 ps
CPU time 21.27 seconds
Started Aug 28 10:41:43 PM UTC 24
Finished Aug 28 10:42:06 PM UTC 24
Peak memory 665820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1970273123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stres
s_wr.1970273123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1787028557
Short name T1340
Test name
Test status
Simulation time 526814621 ps
CPU time 4.24 seconds
Started Aug 28 10:42:04 PM UTC 24
Finished Aug 28 10:42:10 PM UTC 24
Peak memory 227080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787028
557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.1787028557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.3080214486
Short name T1343
Test name
Test status
Simulation time 901199842 ps
CPU time 4.05 seconds
Started Aug 28 10:42:05 PM UTC 24
Finished Aug 28 10:42:10 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080214
486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_ad
dr.3080214486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_perf.1021865220
Short name T1332
Test name
Test status
Simulation time 6482063426 ps
CPU time 7.48 seconds
Started Aug 28 10:41:55 PM UTC 24
Finished Aug 28 10:42:03 PM UTC 24
Peak memory 233796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021865
220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.1021865220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.2497368565
Short name T1339
Test name
Test status
Simulation time 881176480 ps
CPU time 4.38 seconds
Started Aug 28 10:42:03 PM UTC 24
Finished Aug 28 10:42:09 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497368
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.2497368565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.2433097391
Short name T92
Test name
Test status
Simulation time 4653093072 ps
CPU time 22.74 seconds
Started Aug 28 10:41:34 PM UTC 24
Finished Aug 28 10:41:58 PM UTC 24
Peak memory 227244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433097391 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.2433097391
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.3807561547
Short name T1734
Test name
Test status
Simulation time 50600417521 ps
CPU time 772.77 seconds
Started Aug 28 10:41:56 PM UTC 24
Finished Aug 28 10:54:57 PM UTC 24
Peak memory 5533852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380756
1547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.3807561547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.3541057077
Short name T1325
Test name
Test status
Simulation time 5286405605 ps
CPU time 19.65 seconds
Started Aug 28 10:41:34 PM UTC 24
Finished Aug 28 10:41:55 PM UTC 24
Peak memory 243932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541057077 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.3541057077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.1547176358
Short name T1726
Test name
Test status
Simulation time 46535347866 ps
CPU time 635.05 seconds
Started Aug 28 10:41:34 PM UTC 24
Finished Aug 28 10:52:16 PM UTC 24
Peak memory 6731992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547176358 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.1547176358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.3073054209
Short name T1378
Test name
Test status
Simulation time 3817341279 ps
CPU time 82.04 seconds
Started Aug 28 10:41:35 PM UTC 24
Finished Aug 28 10:42:59 PM UTC 24
Peak memory 594064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073054209 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.3073054209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.569850245
Short name T1328
Test name
Test status
Simulation time 1095223285 ps
CPU time 11.43 seconds
Started Aug 28 10:41:44 PM UTC 24
Finished Aug 28 10:41:57 PM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5698502
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.569850245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.2307036081
Short name T1341
Test name
Test status
Simulation time 379826675 ps
CPU time 9.56 seconds
Started Aug 28 10:42:02 PM UTC 24
Finished Aug 28 10:42:13 PM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307036
081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.2307036081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_alert_test.1630071283
Short name T1375
Test name
Test status
Simulation time 15671307 ps
CPU time 0.91 seconds
Started Aug 28 10:42:51 PM UTC 24
Finished Aug 28 10:42:53 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630071283 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1630071283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.3416032769
Short name T1348
Test name
Test status
Simulation time 425283154 ps
CPU time 2.35 seconds
Started Aug 28 10:42:16 PM UTC 24
Finished Aug 28 10:42:20 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416032769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3416032769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.2451843810
Short name T1347
Test name
Test status
Simulation time 886877704 ps
CPU time 6.07 seconds
Started Aug 28 10:42:11 PM UTC 24
Finished Aug 28 10:42:18 PM UTC 24
Peak memory 264540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451843810 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.2451843810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.2261610827
Short name T1511
Test name
Test status
Simulation time 3027827414 ps
CPU time 187.03 seconds
Started Aug 28 10:42:11 PM UTC 24
Finished Aug 28 10:45:21 PM UTC 24
Peak memory 643488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261610827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2261610827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.1718122346
Short name T1396
Test name
Test status
Simulation time 11642774852 ps
CPU time 75.81 seconds
Started Aug 28 10:42:10 PM UTC 24
Finished Aug 28 10:43:28 PM UTC 24
Peak memory 751848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718122346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1718122346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.2030959791
Short name T1344
Test name
Test status
Simulation time 115491707 ps
CPU time 2.13 seconds
Started Aug 28 10:42:11 PM UTC 24
Finished Aug 28 10:42:14 PM UTC 24
Peak memory 216808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030959791 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.2030959791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.4277130074
Short name T1349
Test name
Test status
Simulation time 453756496 ps
CPU time 8.29 seconds
Started Aug 28 10:42:11 PM UTC 24
Finished Aug 28 10:42:20 PM UTC 24
Peak memory 266380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277130074 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.4277130074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.1649483571
Short name T1389
Test name
Test status
Simulation time 3240077209 ps
CPU time 68.11 seconds
Started Aug 28 10:42:09 PM UTC 24
Finished Aug 28 10:43:19 PM UTC 24
Peak memory 973012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649483571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1649483571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.987737233
Short name T1372
Test name
Test status
Simulation time 1801316904 ps
CPU time 9.01 seconds
Started Aug 28 10:42:42 PM UTC 24
Finished Aug 28 10:42:52 PM UTC 24
Peak memory 216580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987737233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.987737233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_override.2297861121
Short name T1304
Test name
Test status
Simulation time 29814687 ps
CPU time 1.06 seconds
Started Aug 28 10:42:09 PM UTC 24
Finished Aug 28 10:42:11 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297861121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2297861121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_perf.4264751748
Short name T1351
Test name
Test status
Simulation time 3088839597 ps
CPU time 11.66 seconds
Started Aug 28 10:42:12 PM UTC 24
Finished Aug 28 10:42:25 PM UTC 24
Peak memory 233712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264751748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.4264751748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.3938934180
Short name T1406
Test name
Test status
Simulation time 6023279935 ps
CPU time 88.67 seconds
Started Aug 28 10:42:14 PM UTC 24
Finished Aug 28 10:43:45 PM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938934180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.3938934180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.1574827939
Short name T1401
Test name
Test status
Simulation time 1804597122 ps
CPU time 83.41 seconds
Started Aug 28 10:42:08 PM UTC 24
Finished Aug 28 10:43:33 PM UTC 24
Peak memory 344392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574827939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1574827939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.249531983
Short name T1369
Test name
Test status
Simulation time 2565993494 ps
CPU time 34.17 seconds
Started Aug 28 10:42:15 PM UTC 24
Finished Aug 28 10:42:51 PM UTC 24
Peak memory 226896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249531983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.249531983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.2081040359
Short name T1365
Test name
Test status
Simulation time 10788195725 ps
CPU time 8.97 seconds
Started Aug 28 10:42:35 PM UTC 24
Finished Aug 28 10:42:45 PM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2081040359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_ad
dr.2081040359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.2387950277
Short name T1357
Test name
Test status
Simulation time 171448985 ps
CPU time 1.45 seconds
Started Aug 28 10:42:32 PM UTC 24
Finished Aug 28 10:42:35 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387950
277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.2387950277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.3902812574
Short name T1359
Test name
Test status
Simulation time 676941349 ps
CPU time 1.98 seconds
Started Aug 28 10:42:32 PM UTC 24
Finished Aug 28 10:42:35 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902812
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.3902812574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.3964817844
Short name T1367
Test name
Test status
Simulation time 662925485 ps
CPU time 3.25 seconds
Started Aug 28 10:42:42 PM UTC 24
Finished Aug 28 10:42:46 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964817
844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermar
ks_acq.3964817844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.2045530223
Short name T1366
Test name
Test status
Simulation time 443827249 ps
CPU time 2.05 seconds
Started Aug 28 10:42:43 PM UTC 24
Finished Aug 28 10:42:46 PM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045530
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermark
s_tx.2045530223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.3850356800
Short name T1361
Test name
Test status
Simulation time 659779579 ps
CPU time 3.54 seconds
Started Aug 28 10:42:37 PM UTC 24
Finished Aug 28 10:42:41 PM UTC 24
Peak memory 228920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850356
800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_hrst.3850356800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.1419533640
Short name T1360
Test name
Test status
Simulation time 2721271662 ps
CPU time 11.79 seconds
Started Aug 28 10:42:26 PM UTC 24
Finished Aug 28 10:42:39 PM UTC 24
Peak memory 244028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141953
3640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.1419533640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.1842160767
Short name T1397
Test name
Test status
Simulation time 5464103133 ps
CPU time 61.39 seconds
Started Aug 28 10:42:27 PM UTC 24
Finished Aug 28 10:43:30 PM UTC 24
Peak memory 1450208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1842160767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres
s_wr.1842160767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.2898254402
Short name T1374
Test name
Test status
Simulation time 456532624 ps
CPU time 4.32 seconds
Started Aug 28 10:42:47 PM UTC 24
Finished Aug 28 10:42:52 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898254
402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.2898254402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.337657606
Short name T1373
Test name
Test status
Simulation time 1957122466 ps
CPU time 3.9 seconds
Started Aug 28 10:42:47 PM UTC 24
Finished Aug 28 10:42:52 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376576
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.337657606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.1972799030
Short name T1371
Test name
Test status
Simulation time 648845594 ps
CPU time 2.13 seconds
Started Aug 28 10:42:48 PM UTC 24
Finished Aug 28 10:42:51 PM UTC 24
Peak memory 233408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972799
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.1972799030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_perf.1413338116
Short name T1362
Test name
Test status
Simulation time 3101518929 ps
CPU time 6.71 seconds
Started Aug 28 10:42:33 PM UTC 24
Finished Aug 28 10:42:41 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413338
116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.1413338116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.583124688
Short name T1370
Test name
Test status
Simulation time 1855898023 ps
CPU time 4.08 seconds
Started Aug 28 10:42:46 PM UTC 24
Finished Aug 28 10:42:51 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5831246
88 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.583124688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.946103964
Short name T1358
Test name
Test status
Simulation time 3732383363 ps
CPU time 14.3 seconds
Started Aug 28 10:42:20 PM UTC 24
Finished Aug 28 10:42:35 PM UTC 24
Peak memory 226988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946103964 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.946103964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.2472905907
Short name T1521
Test name
Test status
Simulation time 49194370094 ps
CPU time 185.43 seconds
Started Aug 28 10:42:35 PM UTC 24
Finished Aug 28 10:45:43 PM UTC 24
Peak memory 2265328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247290
5907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.2472905907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.4230892797
Short name T1380
Test name
Test status
Simulation time 694735543 ps
CPU time 36.84 seconds
Started Aug 28 10:42:22 PM UTC 24
Finished Aug 28 10:43:00 PM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230892797 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.4230892797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.305822593
Short name T1346
Test name
Test status
Simulation time 54006680261 ps
CPU time 83.36 seconds
Started Aug 28 10:42:21 PM UTC 24
Finished Aug 28 10:43:46 PM UTC 24
Peak memory 1130716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305822593 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.305822593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.3281508781
Short name T1455
Test name
Test status
Simulation time 2647247169 ps
CPU time 113.56 seconds
Started Aug 28 10:42:25 PM UTC 24
Finished Aug 28 10:44:21 PM UTC 24
Peak memory 796824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281508781 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.3281508781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.2840559030
Short name T1364
Test name
Test status
Simulation time 1110230238 ps
CPU time 10.92 seconds
Started Aug 28 10:42:30 PM UTC 24
Finished Aug 28 10:42:42 PM UTC 24
Peak memory 233760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840559
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.2840559030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.3650658308
Short name T1376
Test name
Test status
Simulation time 531467682 ps
CPU time 10.35 seconds
Started Aug 28 10:42:43 PM UTC 24
Finished Aug 28 10:42:54 PM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650658
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3650658308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_alert_test.1134926044
Short name T130
Test name
Test status
Simulation time 118810643 ps
CPU time 0.87 seconds
Started Aug 28 10:22:42 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134926044 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1134926044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.3973812431
Short name T22
Test name
Test status
Simulation time 346448493 ps
CPU time 1.78 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:22:30 PM UTC 24
Peak memory 232552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973812431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3973812431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.1826663401
Short name T330
Test name
Test status
Simulation time 220017431 ps
CPU time 4.36 seconds
Started Aug 28 10:22:25 PM UTC 24
Finished Aug 28 10:22:31 PM UTC 24
Peak memory 260164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826663401 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.1826663401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.2086002728
Short name T166
Test name
Test status
Simulation time 9365531571 ps
CPU time 58.7 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:23:27 PM UTC 24
Peak memory 399580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086002728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2086002728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.3656785312
Short name T188
Test name
Test status
Simulation time 2654078029 ps
CPU time 73.71 seconds
Started Aug 28 10:22:24 PM UTC 24
Finished Aug 28 10:23:40 PM UTC 24
Peak memory 717224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656785312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.3656785312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.905497867
Short name T184
Test name
Test status
Simulation time 127421443 ps
CPU time 1.66 seconds
Started Aug 28 10:22:25 PM UTC 24
Finished Aug 28 10:22:28 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905497867 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.905497867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.4091869456
Short name T126
Test name
Test status
Simulation time 221895580 ps
CPU time 14.84 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 260384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091869456 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.4091869456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.218818367
Short name T88
Test name
Test status
Simulation time 48260523879 ps
CPU time 130.31 seconds
Started Aug 28 10:22:24 PM UTC 24
Finished Aug 28 10:24:37 PM UTC 24
Peak memory 831708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218818367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.218818367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.2574770809
Short name T267
Test name
Test status
Simulation time 1915642197 ps
CPU time 19.26 seconds
Started Aug 28 10:22:35 PM UTC 24
Finished Aug 28 10:22:55 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574770809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2574770809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_mode_toggle.2827261811
Short name T31
Test name
Test status
Simulation time 263487904 ps
CPU time 2.08 seconds
Started Aug 28 10:22:35 PM UTC 24
Finished Aug 28 10:22:38 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827261811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2827261811
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_override.3444211457
Short name T149
Test name
Test status
Simulation time 58403811 ps
CPU time 0.92 seconds
Started Aug 28 10:22:23 PM UTC 24
Finished Aug 28 10:22:25 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444211457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3444211457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_perf.3062870377
Short name T16
Test name
Test status
Simulation time 24818588283 ps
CPU time 28.23 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:22:56 PM UTC 24
Peak memory 420060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062870377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3062870377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.791375657
Short name T329
Test name
Test status
Simulation time 294037609 ps
CPU time 2.91 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:22:31 PM UTC 24
Peak memory 239348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791375657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.791375657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.4015939724
Short name T337
Test name
Test status
Simulation time 640057012 ps
CPU time 10.82 seconds
Started Aug 28 10:22:27 PM UTC 24
Finished Aug 28 10:22:39 PM UTC 24
Peak memory 233436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015939724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.4015939724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2289210761
Short name T131
Test name
Test status
Simulation time 1306190753 ps
CPU time 1.57 seconds
Started Aug 28 10:22:42 PM UTC 24
Finished Aug 28 10:22:44 PM UTC 24
Peak memory 246616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289210761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2289210761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.3309155471
Short name T345
Test name
Test status
Simulation time 1508645696 ps
CPU time 11.89 seconds
Started Aug 28 10:22:33 PM UTC 24
Finished Aug 28 10:22:46 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3309155471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3309155471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.1214574198
Short name T333
Test name
Test status
Simulation time 238346216 ps
CPU time 1.65 seconds
Started Aug 28 10:22:31 PM UTC 24
Finished Aug 28 10:22:34 PM UTC 24
Peak memory 214452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214574
198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.1214574198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.2725354565
Short name T334
Test name
Test status
Simulation time 774514106 ps
CPU time 2.14 seconds
Started Aug 28 10:22:31 PM UTC 24
Finished Aug 28 10:22:35 PM UTC 24
Peak memory 216328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725354
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.2725354565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.938487678
Short name T128
Test name
Test status
Simulation time 1329186253 ps
CPU time 6.12 seconds
Started Aug 28 10:22:36 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9384876
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_acq.938487678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.3991414934
Short name T340
Test name
Test status
Simulation time 365413118 ps
CPU time 1.5 seconds
Started Aug 28 10:22:38 PM UTC 24
Finished Aug 28 10:22:41 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991414
934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.3991414934
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_hrst.403940986
Short name T200
Test name
Test status
Simulation time 475872764 ps
CPU time 2.93 seconds
Started Aug 28 10:22:34 PM UTC 24
Finished Aug 28 10:22:38 PM UTC 24
Peak memory 216648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039409
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.403940986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.4139130410
Short name T338
Test name
Test status
Simulation time 1193125211 ps
CPU time 9.16 seconds
Started Aug 28 10:22:29 PM UTC 24
Finished Aug 28 10:22:39 PM UTC 24
Peak memory 243820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413913
0410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.4139130410
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.1226195307
Short name T336
Test name
Test status
Simulation time 3856445547 ps
CPU time 7.11 seconds
Started Aug 28 10:22:29 PM UTC 24
Finished Aug 28 10:22:37 PM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1226195307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress
_wr.1226195307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.3051121442
Short name T344
Test name
Test status
Simulation time 1051329056 ps
CPU time 4.67 seconds
Started Aug 28 10:22:39 PM UTC 24
Finished Aug 28 10:22:45 PM UTC 24
Peak memory 226688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051121
442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.3051121442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.15004376
Short name T343
Test name
Test status
Simulation time 527370136 ps
CPU time 4.63 seconds
Started Aug 28 10:22:39 PM UTC 24
Finished Aug 28 10:22:45 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500437
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.15004376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_perf.2106261273
Short name T127
Test name
Test status
Simulation time 3550329391 ps
CPU time 8.85 seconds
Started Aug 28 10:22:33 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 233684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106261
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.2106261273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.1392688241
Short name T129
Test name
Test status
Simulation time 442890426 ps
CPU time 4.06 seconds
Started Aug 28 10:22:38 PM UTC 24
Finished Aug 28 10:22:43 PM UTC 24
Peak memory 216372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392688
241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.1392688241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.355852198
Short name T229
Test name
Test status
Simulation time 1007121238 ps
CPU time 19.58 seconds
Started Aug 28 10:22:28 PM UTC 24
Finished Aug 28 10:22:49 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355852198 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.355852198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.105524799
Short name T309
Test name
Test status
Simulation time 39507313239 ps
CPU time 227.18 seconds
Started Aug 28 10:22:33 PM UTC 24
Finished Aug 28 10:26:23 PM UTC 24
Peak memory 3314068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105524
799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.105524799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2817638050
Short name T280
Test name
Test status
Simulation time 951221658 ps
CPU time 47.63 seconds
Started Aug 28 10:22:28 PM UTC 24
Finished Aug 28 10:23:17 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817638050 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2817638050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3385150795
Short name T508
Test name
Test status
Simulation time 42388067252 ps
CPU time 220.93 seconds
Started Aug 28 10:22:28 PM UTC 24
Finished Aug 28 10:26:12 PM UTC 24
Peak memory 3080348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385150795 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.3385150795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3544191443
Short name T335
Test name
Test status
Simulation time 1146937591 ps
CPU time 6.7 seconds
Started Aug 28 10:22:29 PM UTC 24
Finished Aug 28 10:22:37 PM UTC 24
Peak memory 272468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544191443 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.3544191443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.1990605259
Short name T341
Test name
Test status
Simulation time 5387140694 ps
CPU time 10.14 seconds
Started Aug 28 10:22:30 PM UTC 24
Finished Aug 28 10:22:42 PM UTC 24
Peak memory 226952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990605
259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.1990605259
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2905477325
Short name T342
Test name
Test status
Simulation time 128756336 ps
CPU time 3.28 seconds
Started Aug 28 10:22:38 PM UTC 24
Finished Aug 28 10:22:42 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905477
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2905477325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_alert_test.2905243416
Short name T1408
Test name
Test status
Simulation time 28556253 ps
CPU time 0.95 seconds
Started Aug 28 10:43:35 PM UTC 24
Finished Aug 28 10:43:37 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905243416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2905243416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.4148002943
Short name T1385
Test name
Test status
Simulation time 260968520 ps
CPU time 5.57 seconds
Started Aug 28 10:43:01 PM UTC 24
Finished Aug 28 10:43:08 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148002943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.4148002943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.3442512332
Short name T1383
Test name
Test status
Simulation time 2259802797 ps
CPU time 8.44 seconds
Started Aug 28 10:42:54 PM UTC 24
Finished Aug 28 10:43:03 PM UTC 24
Peak memory 293088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442512332 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.3442512332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.235541108
Short name T1448
Test name
Test status
Simulation time 7247471052 ps
CPU time 75.2 seconds
Started Aug 28 10:42:55 PM UTC 24
Finished Aug 28 10:44:12 PM UTC 24
Peak memory 336140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235541108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.235541108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.961560765
Short name T1440
Test name
Test status
Simulation time 9867352345 ps
CPU time 73.29 seconds
Started Aug 28 10:42:53 PM UTC 24
Finished Aug 28 10:44:08 PM UTC 24
Peak memory 618640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961560765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.961560765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.1273880893
Short name T1384
Test name
Test status
Simulation time 916717066 ps
CPU time 9.69 seconds
Started Aug 28 10:42:55 PM UTC 24
Finished Aug 28 10:43:06 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273880893 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.1273880893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.2550798943
Short name T1486
Test name
Test status
Simulation time 14636942155 ps
CPU time 110.45 seconds
Started Aug 28 10:42:53 PM UTC 24
Finished Aug 28 10:44:45 PM UTC 24
Peak memory 1208472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550798943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2550798943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.504673225
Short name T1411
Test name
Test status
Simulation time 3784411697 ps
CPU time 7.85 seconds
Started Aug 28 10:43:28 PM UTC 24
Finished Aug 28 10:43:38 PM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504673225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.504673225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_override.2544270574
Short name T1377
Test name
Test status
Simulation time 19366871 ps
CPU time 0.97 seconds
Started Aug 28 10:42:52 PM UTC 24
Finished Aug 28 10:42:54 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544270574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2544270574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3840579490
Short name T1386
Test name
Test status
Simulation time 6917451253 ps
CPU time 10.38 seconds
Started Aug 28 10:42:57 PM UTC 24
Finished Aug 28 10:43:08 PM UTC 24
Peak memory 233300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840579490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3840579490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.600440004
Short name T1382
Test name
Test status
Simulation time 244876000 ps
CPU time 1.59 seconds
Started Aug 28 10:43:00 PM UTC 24
Finished Aug 28 10:43:03 PM UTC 24
Peak memory 216616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600440004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.600440004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.674016392
Short name T1392
Test name
Test status
Simulation time 6972639314 ps
CPU time 28.7 seconds
Started Aug 28 10:42:52 PM UTC 24
Finished Aug 28 10:43:22 PM UTC 24
Peak memory 309452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674016392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.674016392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.2040969100
Short name T1390
Test name
Test status
Simulation time 778546258 ps
CPU time 17.37 seconds
Started Aug 28 10:43:00 PM UTC 24
Finished Aug 28 10:43:19 PM UTC 24
Peak memory 243724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040969100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2040969100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.86420129
Short name T1404
Test name
Test status
Simulation time 4045705141 ps
CPU time 8.08 seconds
Started Aug 28 10:43:24 PM UTC 24
Finished Aug 28 10:43:34 PM UTC 24
Peak memory 222796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=86420129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.86420129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1578942949
Short name T1393
Test name
Test status
Simulation time 219284894 ps
CPU time 1.85 seconds
Started Aug 28 10:43:20 PM UTC 24
Finished Aug 28 10:43:23 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578942
949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1578942949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.1059273704
Short name T1394
Test name
Test status
Simulation time 231826912 ps
CPU time 1.79 seconds
Started Aug 28 10:43:22 PM UTC 24
Finished Aug 28 10:43:25 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059273
704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.1059273704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.2686587324
Short name T1409
Test name
Test status
Simulation time 1039867786 ps
CPU time 5.1 seconds
Started Aug 28 10:43:31 PM UTC 24
Finished Aug 28 10:43:37 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686587
324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermar
ks_acq.2686587324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.2620304047
Short name T1405
Test name
Test status
Simulation time 263055417 ps
CPU time 2.14 seconds
Started Aug 28 10:43:32 PM UTC 24
Finished Aug 28 10:43:35 PM UTC 24
Peak memory 216316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620304
047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_tx.2620304047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_hrst.975914693
Short name T1399
Test name
Test status
Simulation time 1266226989 ps
CPU time 3.67 seconds
Started Aug 28 10:43:26 PM UTC 24
Finished Aug 28 10:43:32 PM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9759146
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_hrst.975914693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.41659281
Short name T1391
Test name
Test status
Simulation time 1161144126 ps
CPU time 9.55 seconds
Started Aug 28 10:43:10 PM UTC 24
Finished Aug 28 10:43:21 PM UTC 24
Peak memory 228872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416592
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.41659281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.1751347443
Short name T1547
Test name
Test status
Simulation time 16059496957 ps
CPU time 164.99 seconds
Started Aug 28 10:43:14 PM UTC 24
Finished Aug 28 10:46:02 PM UTC 24
Peak memory 2363548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1751347443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stres
s_wr.1751347443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.3664989998
Short name T1413
Test name
Test status
Simulation time 1992819676 ps
CPU time 3.2 seconds
Started Aug 28 10:43:34 PM UTC 24
Finished Aug 28 10:43:38 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664989
998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.3664989998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.3143216356
Short name T1416
Test name
Test status
Simulation time 1010221408 ps
CPU time 4.06 seconds
Started Aug 28 10:43:34 PM UTC 24
Finished Aug 28 10:43:39 PM UTC 24
Peak memory 216604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143216
356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.3143216356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.1164981649
Short name T1410
Test name
Test status
Simulation time 617788568 ps
CPU time 2.12 seconds
Started Aug 28 10:43:34 PM UTC 24
Finished Aug 28 10:43:37 PM UTC 24
Peak memory 233740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164981
649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.1164981649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_perf.4199549774
Short name T1398
Test name
Test status
Simulation time 7032658186 ps
CPU time 6.74 seconds
Started Aug 28 10:43:23 PM UTC 24
Finished Aug 28 10:43:31 PM UTC 24
Peak memory 233132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199549
774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.4199549774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.2928298682
Short name T1414
Test name
Test status
Simulation time 2019644925 ps
CPU time 4.45 seconds
Started Aug 28 10:43:33 PM UTC 24
Finished Aug 28 10:43:38 PM UTC 24
Peak memory 216364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928298
682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.2928298682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.1457013696
Short name T1418
Test name
Test status
Simulation time 3824696911 ps
CPU time 35.74 seconds
Started Aug 28 10:43:03 PM UTC 24
Finished Aug 28 10:43:40 PM UTC 24
Peak memory 227004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457013696 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.1457013696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.3609520203
Short name T1426
Test name
Test status
Simulation time 5538835308 ps
CPU time 31.62 seconds
Started Aug 28 10:43:23 PM UTC 24
Finished Aug 28 10:43:56 PM UTC 24
Peak memory 248088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360952
0203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.3609520203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.3866291369
Short name T1415
Test name
Test status
Simulation time 2664076195 ps
CPU time 30.71 seconds
Started Aug 28 10:43:07 PM UTC 24
Finished Aug 28 10:43:39 PM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866291369 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.3866291369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.1997267006
Short name T1727
Test name
Test status
Simulation time 44051566692 ps
CPU time 559.76 seconds
Started Aug 28 10:43:04 PM UTC 24
Finished Aug 28 10:52:31 PM UTC 24
Peak memory 6011096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997267006 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.1997267006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.3021706568
Short name T1402
Test name
Test status
Simulation time 2200802286 ps
CPU time 23.32 seconds
Started Aug 28 10:43:09 PM UTC 24
Finished Aug 28 10:43:33 PM UTC 24
Peak memory 446680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021706568 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.3021706568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.3739951023
Short name T1395
Test name
Test status
Simulation time 19995345088 ps
CPU time 7.9 seconds
Started Aug 28 10:43:18 PM UTC 24
Finished Aug 28 10:43:27 PM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739951
023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.3739951023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_alert_test.1121381007
Short name T1443
Test name
Test status
Simulation time 27846421 ps
CPU time 0.91 seconds
Started Aug 28 10:44:07 PM UTC 24
Finished Aug 28 10:44:09 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121381007 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1121381007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.4068895026
Short name T1419
Test name
Test status
Simulation time 1096826543 ps
CPU time 1.78 seconds
Started Aug 28 10:43:40 PM UTC 24
Finished Aug 28 10:43:43 PM UTC 24
Peak memory 226376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068895026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.4068895026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.2191283451
Short name T1421
Test name
Test status
Simulation time 1480590710 ps
CPU time 9.62 seconds
Started Aug 28 10:43:38 PM UTC 24
Finished Aug 28 10:43:49 PM UTC 24
Peak memory 292888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191283451 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.2191283451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.4161788433
Short name T1487
Test name
Test status
Simulation time 8784020803 ps
CPU time 67.44 seconds
Started Aug 28 10:43:39 PM UTC 24
Finished Aug 28 10:44:48 PM UTC 24
Peak memory 606436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161788433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.4161788433
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.564187726
Short name T1542
Test name
Test status
Simulation time 9077207989 ps
CPU time 137.87 seconds
Started Aug 28 10:43:37 PM UTC 24
Finished Aug 28 10:45:58 PM UTC 24
Peak memory 737740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564187726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.564187726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.1243882239
Short name T1417
Test name
Test status
Simulation time 332190059 ps
CPU time 1.84 seconds
Started Aug 28 10:43:37 PM UTC 24
Finished Aug 28 10:43:40 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243882239 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.1243882239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.266300364
Short name T1420
Test name
Test status
Simulation time 1299800014 ps
CPU time 5.65 seconds
Started Aug 28 10:43:39 PM UTC 24
Finished Aug 28 10:43:45 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266300364 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.266300364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.209435932
Short name T1688
Test name
Test status
Simulation time 39655066546 ps
CPU time 299.88 seconds
Started Aug 28 10:43:36 PM UTC 24
Finished Aug 28 10:48:41 PM UTC 24
Peak memory 1335448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209435932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.209435932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.850815897
Short name T1433
Test name
Test status
Simulation time 492895924 ps
CPU time 4.63 seconds
Started Aug 28 10:43:57 PM UTC 24
Finished Aug 28 10:44:03 PM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850815897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.850815897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_override.4235526825
Short name T1412
Test name
Test status
Simulation time 26581799 ps
CPU time 1.04 seconds
Started Aug 28 10:43:36 PM UTC 24
Finished Aug 28 10:43:38 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235526825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.4235526825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_perf.4119347346
Short name T1452
Test name
Test status
Simulation time 7173618543 ps
CPU time 35.98 seconds
Started Aug 28 10:43:39 PM UTC 24
Finished Aug 28 10:44:16 PM UTC 24
Peak memory 233932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119347346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.4119347346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.3528451879
Short name T1429
Test name
Test status
Simulation time 6423264444 ps
CPU time 19.43 seconds
Started Aug 28 10:43:39 PM UTC 24
Finished Aug 28 10:43:59 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528451879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3528451879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.2209008084
Short name T1456
Test name
Test status
Simulation time 7273116680 ps
CPU time 43.26 seconds
Started Aug 28 10:43:36 PM UTC 24
Finished Aug 28 10:44:21 PM UTC 24
Peak memory 360652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209008084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2209008084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.716235897
Short name T1588
Test name
Test status
Simulation time 6050283381 ps
CPU time 188.26 seconds
Started Aug 28 10:43:40 PM UTC 24
Finished Aug 28 10:46:51 PM UTC 24
Peak memory 911680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716235897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.716235897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.2096107902
Short name T1423
Test name
Test status
Simulation time 574115086 ps
CPU time 12.42 seconds
Started Aug 28 10:43:40 PM UTC 24
Finished Aug 28 10:43:53 PM UTC 24
Peak memory 232880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096107902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2096107902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.3507815114
Short name T1432
Test name
Test status
Simulation time 7076389119 ps
CPU time 5.67 seconds
Started Aug 28 10:43:56 PM UTC 24
Finished Aug 28 10:44:03 PM UTC 24
Peak memory 227140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3507815114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad
dr.3507815114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.2248890841
Short name T1422
Test name
Test status
Simulation time 194880042 ps
CPU time 1.71 seconds
Started Aug 28 10:43:51 PM UTC 24
Finished Aug 28 10:43:53 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248890
841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.2248890841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.3217179094
Short name T1427
Test name
Test status
Simulation time 155558575 ps
CPU time 1.76 seconds
Started Aug 28 10:43:54 PM UTC 24
Finished Aug 28 10:43:56 PM UTC 24
Peak memory 216340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217179
094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.3217179094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.2299513571
Short name T1435
Test name
Test status
Simulation time 587557262 ps
CPU time 5.62 seconds
Started Aug 28 10:43:59 PM UTC 24
Finished Aug 28 10:44:06 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299513
571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermar
ks_acq.2299513571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.3289855056
Short name T1434
Test name
Test status
Simulation time 542690764 ps
CPU time 2.35 seconds
Started Aug 28 10:44:00 PM UTC 24
Finished Aug 28 10:44:04 PM UTC 24
Peak memory 216380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289855
056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_tx.3289855056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.3623574987
Short name T1431
Test name
Test status
Simulation time 317075216 ps
CPU time 2.98 seconds
Started Aug 28 10:43:56 PM UTC 24
Finished Aug 28 10:44:00 PM UTC 24
Peak memory 226928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623574
987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.3623574987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.1213826530
Short name T1425
Test name
Test status
Simulation time 1794057359 ps
CPU time 8.76 seconds
Started Aug 28 10:43:45 PM UTC 24
Finished Aug 28 10:43:55 PM UTC 24
Peak memory 230908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121382
6530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.1213826530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.2513087546
Short name T1709
Test name
Test status
Simulation time 17898431433 ps
CPU time 309.27 seconds
Started Aug 28 10:43:46 PM UTC 24
Finished Aug 28 10:49:00 PM UTC 24
Peak memory 4481180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2513087546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stres
s_wr.2513087546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.893399123
Short name T1445
Test name
Test status
Simulation time 509589083 ps
CPU time 4.56 seconds
Started Aug 28 10:44:04 PM UTC 24
Finished Aug 28 10:44:09 PM UTC 24
Peak memory 226748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8933991
23 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.893399123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.2210225507
Short name T1442
Test name
Test status
Simulation time 440105458 ps
CPU time 3.63 seconds
Started Aug 28 10:44:04 PM UTC 24
Finished Aug 28 10:44:08 PM UTC 24
Peak memory 216596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210225
507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_ad
dr.2210225507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.2892483638
Short name T1439
Test name
Test status
Simulation time 1279190997 ps
CPU time 1.89 seconds
Started Aug 28 10:44:05 PM UTC 24
Finished Aug 28 10:44:08 PM UTC 24
Peak memory 232564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892483
638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.2892483638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_perf.2906070130
Short name T1437
Test name
Test status
Simulation time 2059869206 ps
CPU time 11.44 seconds
Started Aug 28 10:43:54 PM UTC 24
Finished Aug 28 10:44:06 PM UTC 24
Peak memory 233544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906070
130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.2906070130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.1977274903
Short name T1436
Test name
Test status
Simulation time 457268200 ps
CPU time 4.55 seconds
Started Aug 28 10:44:00 PM UTC 24
Finished Aug 28 10:44:06 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977274
903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.1977274903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.3048070458
Short name T1363
Test name
Test status
Simulation time 2473979736 ps
CPU time 7.47 seconds
Started Aug 28 10:43:40 PM UTC 24
Finished Aug 28 10:43:49 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048070458 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.3048070458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.3532859030
Short name T287
Test name
Test status
Simulation time 9205564450 ps
CPU time 98.82 seconds
Started Aug 28 10:43:55 PM UTC 24
Finished Aug 28 10:45:36 PM UTC 24
Peak memory 573848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353285
9030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.3532859030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.659311473
Short name T1446
Test name
Test status
Simulation time 2976743631 ps
CPU time 28.15 seconds
Started Aug 28 10:43:41 PM UTC 24
Finished Aug 28 10:44:11 PM UTC 24
Peak memory 243864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659311473 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.659311473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.1157847004
Short name T1594
Test name
Test status
Simulation time 61726398481 ps
CPU time 192.07 seconds
Started Aug 28 10:43:41 PM UTC 24
Finished Aug 28 10:46:56 PM UTC 24
Peak memory 2498840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157847004 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.1157847004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.167259933
Short name T1424
Test name
Test status
Simulation time 2161640450 ps
CPU time 10.33 seconds
Started Aug 28 10:43:43 PM UTC 24
Finished Aug 28 10:43:55 PM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167259933 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.167259933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.1411499054
Short name T1428
Test name
Test status
Simulation time 2567207427 ps
CPU time 10.68 seconds
Started Aug 28 10:43:46 PM UTC 24
Finished Aug 28 10:43:58 PM UTC 24
Peak memory 243872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411499
054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.1411499054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.2190810001
Short name T1438
Test name
Test status
Simulation time 151318450 ps
CPU time 5.7 seconds
Started Aug 28 10:44:00 PM UTC 24
Finished Aug 28 10:44:07 PM UTC 24
Peak memory 216768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190810
001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.2190810001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_alert_test.3369202911
Short name T1478
Test name
Test status
Simulation time 16283376 ps
CPU time 1.04 seconds
Started Aug 28 10:44:34 PM UTC 24
Finished Aug 28 10:44:36 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369202911 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3369202911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.948160957
Short name T1451
Test name
Test status
Simulation time 137140264 ps
CPU time 2.93 seconds
Started Aug 28 10:44:12 PM UTC 24
Finished Aug 28 10:44:16 PM UTC 24
Peak memory 230980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948160957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.948160957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.2307412399
Short name T1462
Test name
Test status
Simulation time 2540226283 ps
CPU time 16.27 seconds
Started Aug 28 10:44:09 PM UTC 24
Finished Aug 28 10:44:27 PM UTC 24
Peak memory 282888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307412399 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.2307412399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.3131137001
Short name T1559
Test name
Test status
Simulation time 20027547455 ps
CPU time 139.56 seconds
Started Aug 28 10:44:09 PM UTC 24
Finished Aug 28 10:46:31 PM UTC 24
Peak memory 966800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131137001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3131137001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.590059830
Short name T1523
Test name
Test status
Simulation time 2504985774 ps
CPU time 94.71 seconds
Started Aug 28 10:44:08 PM UTC 24
Finished Aug 28 10:45:45 PM UTC 24
Peak memory 725464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590059830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.590059830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.4154521648
Short name T260
Test name
Test status
Simulation time 158220636 ps
CPU time 2.11 seconds
Started Aug 28 10:44:09 PM UTC 24
Finished Aug 28 10:44:12 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154521648 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.4154521648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.3838455399
Short name T1450
Test name
Test status
Simulation time 780625987 ps
CPU time 4.77 seconds
Started Aug 28 10:44:09 PM UTC 24
Finished Aug 28 10:44:15 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838455399 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.3838455399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1030910936
Short name T1572
Test name
Test status
Simulation time 19592368774 ps
CPU time 141.73 seconds
Started Aug 28 10:44:08 PM UTC 24
Finished Aug 28 10:46:33 PM UTC 24
Peak memory 1374412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030910936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1030910936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.2232546471
Short name T1469
Test name
Test status
Simulation time 1059005669 ps
CPU time 3.82 seconds
Started Aug 28 10:44:28 PM UTC 24
Finished Aug 28 10:44:33 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232546471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2232546471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.71200082
Short name T1471
Test name
Test status
Simulation time 521093318 ps
CPU time 6.07 seconds
Started Aug 28 10:44:27 PM UTC 24
Finished Aug 28 10:44:34 PM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71200082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.71200082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_override.314705011
Short name T1444
Test name
Test status
Simulation time 28707037 ps
CPU time 1.04 seconds
Started Aug 28 10:44:07 PM UTC 24
Finished Aug 28 10:44:09 PM UTC 24
Peak memory 214332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314705011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.314705011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_perf.1335093783
Short name T1731
Test name
Test status
Simulation time 51370810356 ps
CPU time 531.25 seconds
Started Aug 28 10:44:10 PM UTC 24
Finished Aug 28 10:53:09 PM UTC 24
Peak memory 232912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335093783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1335093783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.216497504
Short name T1449
Test name
Test status
Simulation time 63084669 ps
CPU time 2.21 seconds
Started Aug 28 10:44:10 PM UTC 24
Finished Aug 28 10:44:14 PM UTC 24
Peak memory 216240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216497504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.216497504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.1131401684
Short name T1465
Test name
Test status
Simulation time 956979247 ps
CPU time 21.99 seconds
Started Aug 28 10:44:07 PM UTC 24
Finished Aug 28 10:44:30 PM UTC 24
Peak memory 297036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131401684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1131401684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_stress_all.1914054285
Short name T249
Test name
Test status
Simulation time 30149438439 ps
CPU time 496.02 seconds
Started Aug 28 10:44:13 PM UTC 24
Finished Aug 28 10:52:35 PM UTC 24
Peak memory 1491148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914054285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1914054285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.852570806
Short name T1458
Test name
Test status
Simulation time 971788806 ps
CPU time 10.66 seconds
Started Aug 28 10:44:12 PM UTC 24
Finished Aug 28 10:44:23 PM UTC 24
Peak memory 226836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852570806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.852570806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.1707596699
Short name T1467
Test name
Test status
Simulation time 4027889071 ps
CPU time 5.89 seconds
Started Aug 28 10:44:25 PM UTC 24
Finished Aug 28 10:44:32 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1707596699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_ad
dr.1707596699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.3240036735
Short name T1459
Test name
Test status
Simulation time 289636229 ps
CPU time 1.61 seconds
Started Aug 28 10:44:21 PM UTC 24
Finished Aug 28 10:44:24 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240036
735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.3240036735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.4010308109
Short name T1460
Test name
Test status
Simulation time 534634584 ps
CPU time 1.61 seconds
Started Aug 28 10:44:23 PM UTC 24
Finished Aug 28 10:44:26 PM UTC 24
Peak memory 216524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010308
109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.4010308109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.2463508635
Short name T1475
Test name
Test status
Simulation time 2590632319 ps
CPU time 4.73 seconds
Started Aug 28 10:44:30 PM UTC 24
Finished Aug 28 10:44:36 PM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463508
635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermar
ks_acq.2463508635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.927234070
Short name T1470
Test name
Test status
Simulation time 382537452 ps
CPU time 1.48 seconds
Started Aug 28 10:44:31 PM UTC 24
Finished Aug 28 10:44:33 PM UTC 24
Peak memory 214212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9272340
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermarks
_tx.927234070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2488259320
Short name T1463
Test name
Test status
Simulation time 1156144122 ps
CPU time 10.48 seconds
Started Aug 28 10:44:17 PM UTC 24
Finished Aug 28 10:44:29 PM UTC 24
Peak memory 233676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248825
9320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.2488259320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.1232079553
Short name T1488
Test name
Test status
Simulation time 7676347735 ps
CPU time 30.06 seconds
Started Aug 28 10:44:17 PM UTC 24
Finished Aug 28 10:44:48 PM UTC 24
Peak memory 1001624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1232079553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stres
s_wr.1232079553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.2109737960
Short name T1481
Test name
Test status
Simulation time 2834928087 ps
CPU time 4.6 seconds
Started Aug 28 10:44:32 PM UTC 24
Finished Aug 28 10:44:38 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109737
960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.2109737960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.845006275
Short name T1482
Test name
Test status
Simulation time 435217484 ps
CPU time 3.74 seconds
Started Aug 28 10:44:33 PM UTC 24
Finished Aug 28 10:44:38 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8450062
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_addr.845006275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_perf.2037483183
Short name T1473
Test name
Test status
Simulation time 6988213694 ps
CPU time 9.28 seconds
Started Aug 28 10:44:25 PM UTC 24
Finished Aug 28 10:44:35 PM UTC 24
Peak memory 243964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037483
183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.2037483183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.3141623820
Short name T1476
Test name
Test status
Simulation time 1830803317 ps
CPU time 3.96 seconds
Started Aug 28 10:44:31 PM UTC 24
Finished Aug 28 10:44:36 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141623
820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.3141623820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.3873025667
Short name T1466
Test name
Test status
Simulation time 2200287904 ps
CPU time 16.57 seconds
Started Aug 28 10:44:13 PM UTC 24
Finished Aug 28 10:44:30 PM UTC 24
Peak memory 226992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873025667 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.3873025667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.4270978162
Short name T1515
Test name
Test status
Simulation time 8230218773 ps
CPU time 62.7 seconds
Started Aug 28 10:44:25 PM UTC 24
Finished Aug 28 10:45:29 PM UTC 24
Peak memory 288992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427097
8162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.4270978162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.4228025174
Short name T1464
Test name
Test status
Simulation time 892232462 ps
CPU time 12.94 seconds
Started Aug 28 10:44:16 PM UTC 24
Finished Aug 28 10:44:30 PM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228025174 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.4228025174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.1702439728
Short name T1543
Test name
Test status
Simulation time 22131960261 ps
CPU time 102.23 seconds
Started Aug 28 10:44:15 PM UTC 24
Finished Aug 28 10:45:59 PM UTC 24
Peak memory 692448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702439728 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.1702439728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.348069324
Short name T1474
Test name
Test status
Simulation time 848151584 ps
CPU time 18.15 seconds
Started Aug 28 10:44:16 PM UTC 24
Finished Aug 28 10:44:35 PM UTC 24
Peak memory 272572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348069324 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.348069324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.3290160493
Short name T1468
Test name
Test status
Simulation time 1365042983 ps
CPU time 13.01 seconds
Started Aug 28 10:44:18 PM UTC 24
Finished Aug 28 10:44:32 PM UTC 24
Peak memory 233700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290160
493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.3290160493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.371283078
Short name T1472
Test name
Test status
Simulation time 83672129 ps
CPU time 2.11 seconds
Started Aug 28 10:44:31 PM UTC 24
Finished Aug 28 10:44:34 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712830
78 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.371283078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_alert_test.1816384256
Short name T1501
Test name
Test status
Simulation time 18669520 ps
CPU time 0.95 seconds
Started Aug 28 10:45:08 PM UTC 24
Finished Aug 28 10:45:10 PM UTC 24
Peak memory 215404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816384256 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1816384256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.4025882753
Short name T1485
Test name
Test status
Simulation time 72991688 ps
CPU time 1.95 seconds
Started Aug 28 10:44:39 PM UTC 24
Finished Aug 28 10:44:42 PM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025882753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4025882753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.101108704
Short name T1489
Test name
Test status
Simulation time 1582808717 ps
CPU time 11.49 seconds
Started Aug 28 10:44:37 PM UTC 24
Finished Aug 28 10:44:49 PM UTC 24
Peak memory 301072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101108704 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.101108704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2879348476
Short name T1522
Test name
Test status
Simulation time 4563140007 ps
CPU time 64.32 seconds
Started Aug 28 10:44:38 PM UTC 24
Finished Aug 28 10:45:44 PM UTC 24
Peak memory 473352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879348476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.2879348476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.4237972420
Short name T1609
Test name
Test status
Simulation time 7789583375 ps
CPU time 144.67 seconds
Started Aug 28 10:44:37 PM UTC 24
Finished Aug 28 10:47:04 PM UTC 24
Peak memory 665812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237972420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4237972420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.3132683516
Short name T1484
Test name
Test status
Simulation time 321888251 ps
CPU time 1.54 seconds
Started Aug 28 10:44:37 PM UTC 24
Finished Aug 28 10:44:39 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132683516 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.3132683516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.2819949114
Short name T1491
Test name
Test status
Simulation time 610338276 ps
CPU time 13.1 seconds
Started Aug 28 10:44:37 PM UTC 24
Finished Aug 28 10:44:51 PM UTC 24
Peak memory 245776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819949114 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.2819949114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.238791325
Short name T1579
Test name
Test status
Simulation time 18730113910 ps
CPU time 120.83 seconds
Started Aug 28 10:44:36 PM UTC 24
Finished Aug 28 10:46:39 PM UTC 24
Peak memory 1294612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238791325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.238791325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2042768195
Short name T1512
Test name
Test status
Simulation time 1296902907 ps
CPU time 17.64 seconds
Started Aug 28 10:45:04 PM UTC 24
Finished Aug 28 10:45:23 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042768195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2042768195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_override.3997536081
Short name T1480
Test name
Test status
Simulation time 92412728 ps
CPU time 1.03 seconds
Started Aug 28 10:44:36 PM UTC 24
Finished Aug 28 10:44:38 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997536081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3997536081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_perf.919023627
Short name T1573
Test name
Test status
Simulation time 2580445392 ps
CPU time 113.03 seconds
Started Aug 28 10:44:38 PM UTC 24
Finished Aug 28 10:46:33 PM UTC 24
Peak memory 239480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919023627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.919023627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.1123840381
Short name T1517
Test name
Test status
Simulation time 1397881877 ps
CPU time 58.76 seconds
Started Aug 28 10:44:34 PM UTC 24
Finished Aug 28 10:45:35 PM UTC 24
Peak memory 342092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123840381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1123840381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.966716452
Short name T1494
Test name
Test status
Simulation time 3540975386 ps
CPU time 23.14 seconds
Started Aug 28 10:44:39 PM UTC 24
Finished Aug 28 10:45:03 PM UTC 24
Peak memory 233108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966716452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.966716452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.655751507
Short name T1499
Test name
Test status
Simulation time 893606717 ps
CPU time 8.47 seconds
Started Aug 28 10:44:57 PM UTC 24
Finished Aug 28 10:45:07 PM UTC 24
Peak memory 228876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=655751507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.655751507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.969763253
Short name T251
Test name
Test status
Simulation time 357491369 ps
CPU time 1.59 seconds
Started Aug 28 10:44:52 PM UTC 24
Finished Aug 28 10:44:55 PM UTC 24
Peak memory 216564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9697632
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.969763253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.1445532716
Short name T1493
Test name
Test status
Simulation time 589749231 ps
CPU time 1.83 seconds
Started Aug 28 10:44:54 PM UTC 24
Finished Aug 28 10:44:57 PM UTC 24
Peak memory 226504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445532
716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.1445532716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.283810845
Short name T1505
Test name
Test status
Simulation time 725058591 ps
CPU time 5.96 seconds
Started Aug 28 10:45:05 PM UTC 24
Finished Aug 28 10:45:12 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838108
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_acq.283810845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.3559941906
Short name T1500
Test name
Test status
Simulation time 80718999 ps
CPU time 1.58 seconds
Started Aug 28 10:45:05 PM UTC 24
Finished Aug 28 10:45:08 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559941
906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.3559941906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.4283116383
Short name T1477
Test name
Test status
Simulation time 1959320749 ps
CPU time 9.51 seconds
Started Aug 28 10:44:49 PM UTC 24
Finished Aug 28 10:44:59 PM UTC 24
Peak memory 233212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428311
6383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.4283116383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.937955042
Short name T1519
Test name
Test status
Simulation time 19033968313 ps
CPU time 47.75 seconds
Started Aug 28 10:44:50 PM UTC 24
Finished Aug 28 10:45:39 PM UTC 24
Peak memory 897044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=937955042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stress
_wr.937955042
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.3951498880
Short name T1507
Test name
Test status
Simulation time 1879635564 ps
CPU time 4.54 seconds
Started Aug 28 10:45:07 PM UTC 24
Finished Aug 28 10:45:13 PM UTC 24
Peak memory 226632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951498
880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.3951498880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.1011977499
Short name T1506
Test name
Test status
Simulation time 476982463 ps
CPU time 4.41 seconds
Started Aug 28 10:45:07 PM UTC 24
Finished Aug 28 10:45:13 PM UTC 24
Peak memory 216464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011977
499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_ad
dr.1011977499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.1049179650
Short name T1503
Test name
Test status
Simulation time 575965024 ps
CPU time 2.48 seconds
Started Aug 28 10:45:08 PM UTC 24
Finished Aug 28 10:45:12 PM UTC 24
Peak memory 233688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049179
650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_txstretch.1049179650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_perf.1640393787
Short name T1495
Test name
Test status
Simulation time 14163185588 ps
CPU time 8.81 seconds
Started Aug 28 10:44:55 PM UTC 24
Finished Aug 28 10:45:05 PM UTC 24
Peak memory 245924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640393
787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.1640393787
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.3288512647
Short name T1504
Test name
Test status
Simulation time 1492294693 ps
CPU time 3.87 seconds
Started Aug 28 10:45:07 PM UTC 24
Finished Aug 28 10:45:12 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288512
647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.3288512647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.1139980721
Short name T1492
Test name
Test status
Simulation time 8497581198 ps
CPU time 13.13 seconds
Started Aug 28 10:44:40 PM UTC 24
Finished Aug 28 10:44:55 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139980721 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.1139980721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1591098888
Short name T1619
Test name
Test status
Simulation time 88971551882 ps
CPU time 141.18 seconds
Started Aug 28 10:44:55 PM UTC 24
Finished Aug 28 10:47:19 PM UTC 24
Peak memory 1159516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159109
8888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.1591098888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.3853095813
Short name T1498
Test name
Test status
Simulation time 5271328713 ps
CPU time 19.73 seconds
Started Aug 28 10:44:45 PM UTC 24
Finished Aug 28 10:45:06 PM UTC 24
Peak memory 233784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853095813 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.3853095813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.4172789347
Short name T1546
Test name
Test status
Simulation time 35617724818 ps
CPU time 77.27 seconds
Started Aug 28 10:44:42 PM UTC 24
Finished Aug 28 10:46:02 PM UTC 24
Peak memory 1022112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172789347 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.4172789347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.2298414907
Short name T1490
Test name
Test status
Simulation time 1299695772 ps
CPU time 3.14 seconds
Started Aug 28 10:44:46 PM UTC 24
Finished Aug 28 10:44:50 PM UTC 24
Peak memory 222664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298414907 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.2298414907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.1408546318
Short name T1496
Test name
Test status
Simulation time 5187187296 ps
CPU time 14.34 seconds
Started Aug 28 10:44:51 PM UTC 24
Finished Aug 28 10:45:06 PM UTC 24
Peak memory 233640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408546
318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.1408546318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.1374278295
Short name T1502
Test name
Test status
Simulation time 81551957 ps
CPU time 3.17 seconds
Started Aug 28 10:45:06 PM UTC 24
Finished Aug 28 10:45:10 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374278
295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.1374278295
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_alert_test.2640009339
Short name T1536
Test name
Test status
Simulation time 17697125 ps
CPU time 0.99 seconds
Started Aug 28 10:45:54 PM UTC 24
Finished Aug 28 10:45:56 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640009339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2640009339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.3210879470
Short name T1514
Test name
Test status
Simulation time 93653464 ps
CPU time 2.48 seconds
Started Aug 28 10:45:24 PM UTC 24
Finished Aug 28 10:45:27 PM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210879470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3210879470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.2667862420
Short name T1510
Test name
Test status
Simulation time 283258182 ps
CPU time 6.02 seconds
Started Aug 28 10:45:14 PM UTC 24
Finished Aug 28 10:45:21 PM UTC 24
Peak memory 260532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667862420 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.2667862420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.2959213044
Short name T1561
Test name
Test status
Simulation time 7217878282 ps
CPU time 65.12 seconds
Started Aug 28 10:45:15 PM UTC 24
Finished Aug 28 10:46:23 PM UTC 24
Peak memory 549144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959213044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2959213044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.259298976
Short name T1620
Test name
Test status
Simulation time 4805285707 ps
CPU time 168.95 seconds
Started Aug 28 10:45:12 PM UTC 24
Finished Aug 28 10:48:04 PM UTC 24
Peak memory 807192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259298976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.259298976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.3904221178
Short name T1509
Test name
Test status
Simulation time 82711463 ps
CPU time 1.66 seconds
Started Aug 28 10:45:13 PM UTC 24
Finished Aug 28 10:45:16 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904221178 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.3904221178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.3337068172
Short name T1513
Test name
Test status
Simulation time 283737459 ps
CPU time 11.97 seconds
Started Aug 28 10:45:14 PM UTC 24
Finished Aug 28 10:45:27 PM UTC 24
Peak memory 243740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337068172 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.3337068172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2933270188
Short name T1591
Test name
Test status
Simulation time 7823841449 ps
CPU time 98.08 seconds
Started Aug 28 10:45:12 PM UTC 24
Finished Aug 28 10:46:53 PM UTC 24
Peak memory 1175704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933270188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2933270188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_override.1346580353
Short name T1508
Test name
Test status
Simulation time 110235004 ps
CPU time 0.97 seconds
Started Aug 28 10:45:11 PM UTC 24
Finished Aug 28 10:45:13 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346580353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1346580353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_perf.991414107
Short name T1548
Test name
Test status
Simulation time 2868484707 ps
CPU time 47.43 seconds
Started Aug 28 10:45:17 PM UTC 24
Finished Aug 28 10:46:06 PM UTC 24
Peak memory 241892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991414107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.991414107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2416320908
Short name T1524
Test name
Test status
Simulation time 866305976 ps
CPU time 22.96 seconds
Started Aug 28 10:45:22 PM UTC 24
Finished Aug 28 10:45:46 PM UTC 24
Peak memory 276612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416320908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2416320908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.2410490575
Short name T1575
Test name
Test status
Simulation time 5588230820 ps
CPU time 82.24 seconds
Started Aug 28 10:45:11 PM UTC 24
Finished Aug 28 10:46:36 PM UTC 24
Peak memory 330008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410490575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2410490575
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.1640210098
Short name T1550
Test name
Test status
Simulation time 3661223905 ps
CPU time 43.41 seconds
Started Aug 28 10:45:22 PM UTC 24
Finished Aug 28 10:46:07 PM UTC 24
Peak memory 227052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640210098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1640210098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.3980567955
Short name T1538
Test name
Test status
Simulation time 2102261833 ps
CPU time 8.24 seconds
Started Aug 28 10:45:47 PM UTC 24
Finished Aug 28 10:45:56 PM UTC 24
Peak memory 230928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3980567955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad
dr.3980567955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.1161179251
Short name T252
Test name
Test status
Simulation time 183583727 ps
CPU time 1.18 seconds
Started Aug 28 10:45:44 PM UTC 24
Finished Aug 28 10:45:46 PM UTC 24
Peak memory 226484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161179
251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.1161179251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.1821720198
Short name T1527
Test name
Test status
Simulation time 242067164 ps
CPU time 1.73 seconds
Started Aug 28 10:45:45 PM UTC 24
Finished Aug 28 10:45:48 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821720
198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.1821720198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.4227864834
Short name T1533
Test name
Test status
Simulation time 800236464 ps
CPU time 4.83 seconds
Started Aug 28 10:45:48 PM UTC 24
Finished Aug 28 10:45:54 PM UTC 24
Peak memory 216888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227864
834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermar
ks_acq.4227864834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.4167797658
Short name T1529
Test name
Test status
Simulation time 129825500 ps
CPU time 1.51 seconds
Started Aug 28 10:45:48 PM UTC 24
Finished Aug 28 10:45:51 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167797
658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermark
s_tx.4167797658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_hrst.50964910
Short name T1530
Test name
Test status
Simulation time 250993141 ps
CPU time 3.38 seconds
Started Aug 28 10:45:47 PM UTC 24
Finished Aug 28 10:45:52 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5096491
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_hrst.50964910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2937299385
Short name T1528
Test name
Test status
Simulation time 4064739081 ps
CPU time 10.21 seconds
Started Aug 28 10:45:36 PM UTC 24
Finished Aug 28 10:45:48 PM UTC 24
Peak memory 243984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293729
9385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.2937299385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.2561960343
Short name T1730
Test name
Test status
Simulation time 24990868239 ps
CPU time 438.09 seconds
Started Aug 28 10:45:37 PM UTC 24
Finished Aug 28 10:53:00 PM UTC 24
Peak memory 6088924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2561960343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stres
s_wr.2561960343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.2771636464
Short name T1539
Test name
Test status
Simulation time 485305613 ps
CPU time 3.95 seconds
Started Aug 28 10:45:52 PM UTC 24
Finished Aug 28 10:45:57 PM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771636
464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.2771636464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.3663614577
Short name T1541
Test name
Test status
Simulation time 3195425816 ps
CPU time 3.84 seconds
Started Aug 28 10:45:53 PM UTC 24
Finished Aug 28 10:45:58 PM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663614
577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad
dr.3663614577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.2771993778
Short name T1537
Test name
Test status
Simulation time 449516007 ps
CPU time 2.22 seconds
Started Aug 28 10:45:53 PM UTC 24
Finished Aug 28 10:45:56 PM UTC 24
Peak memory 233424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771993
778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.2771993778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_perf.2219639953
Short name T1532
Test name
Test status
Simulation time 2853185740 ps
CPU time 6.23 seconds
Started Aug 28 10:45:46 PM UTC 24
Finished Aug 28 10:45:53 PM UTC 24
Peak memory 233780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219639
953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.2219639953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.1306612545
Short name T1535
Test name
Test status
Simulation time 438364653 ps
CPU time 3.99 seconds
Started Aug 28 10:45:51 PM UTC 24
Finished Aug 28 10:45:56 PM UTC 24
Peak memory 216304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306612
545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.1306612545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.3234351600
Short name T1534
Test name
Test status
Simulation time 594179059 ps
CPU time 24.91 seconds
Started Aug 28 10:45:28 PM UTC 24
Finished Aug 28 10:45:54 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234351600 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.3234351600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1116736756
Short name T1729
Test name
Test status
Simulation time 92530498696 ps
CPU time 420.06 seconds
Started Aug 28 10:45:46 PM UTC 24
Finished Aug 28 10:52:51 PM UTC 24
Peak memory 3270808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111673
6756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.1116736756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.4199017270
Short name T1525
Test name
Test status
Simulation time 716886789 ps
CPU time 10.87 seconds
Started Aug 28 10:45:34 PM UTC 24
Finished Aug 28 10:45:46 PM UTC 24
Peak memory 230924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199017270 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.4199017270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.637599326
Short name T1728
Test name
Test status
Simulation time 65968961278 ps
CPU time 426.22 seconds
Started Aug 28 10:45:30 PM UTC 24
Finished Aug 28 10:52:42 PM UTC 24
Peak memory 4341916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637599326 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.637599326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.2752125908
Short name T1526
Test name
Test status
Simulation time 2989481305 ps
CPU time 10.42 seconds
Started Aug 28 10:45:35 PM UTC 24
Finished Aug 28 10:45:47 PM UTC 24
Peak memory 293068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752125908 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.2752125908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.1690918031
Short name T1531
Test name
Test status
Simulation time 2949492607 ps
CPU time 10.87 seconds
Started Aug 28 10:45:40 PM UTC 24
Finished Aug 28 10:45:52 PM UTC 24
Peak memory 227016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690918
031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.1690918031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.3352787205
Short name T1545
Test name
Test status
Simulation time 511026145 ps
CPU time 10.27 seconds
Started Aug 28 10:45:49 PM UTC 24
Finished Aug 28 10:46:01 PM UTC 24
Peak memory 232840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352787
205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3352787205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1099988539
Short name T1497
Test name
Test status
Simulation time 45940112 ps
CPU time 0.92 seconds
Started Aug 28 10:46:29 PM UTC 24
Finished Aug 28 10:46:32 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099988539 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1099988539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.3672706334
Short name T1553
Test name
Test status
Simulation time 540748895 ps
CPU time 9.72 seconds
Started Aug 28 10:46:01 PM UTC 24
Finished Aug 28 10:46:11 PM UTC 24
Peak memory 226996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672706334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3672706334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.2488701462
Short name T1549
Test name
Test status
Simulation time 441903618 ps
CPU time 7.85 seconds
Started Aug 28 10:45:57 PM UTC 24
Finished Aug 28 10:46:06 PM UTC 24
Peak memory 309628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488701462 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.2488701462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.1653279396
Short name T1695
Test name
Test status
Simulation time 6064144447 ps
CPU time 169.1 seconds
Started Aug 28 10:45:57 PM UTC 24
Finished Aug 28 10:48:49 PM UTC 24
Peak memory 694736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653279396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1653279396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2478503335
Short name T1590
Test name
Test status
Simulation time 2852353755 ps
CPU time 53.7 seconds
Started Aug 28 10:45:57 PM UTC 24
Finished Aug 28 10:46:53 PM UTC 24
Peak memory 579820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478503335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2478503335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.4022091536
Short name T1544
Test name
Test status
Simulation time 1960079239 ps
CPU time 1.4 seconds
Started Aug 28 10:45:57 PM UTC 24
Finished Aug 28 10:46:00 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022091536 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.4022091536
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.408950082
Short name T1552
Test name
Test status
Simulation time 335185552 ps
CPU time 12.39 seconds
Started Aug 28 10:45:57 PM UTC 24
Finished Aug 28 10:46:11 PM UTC 24
Peak memory 249944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408950082 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.408950082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.4160192525
Short name T1638
Test name
Test status
Simulation time 11640896450 ps
CPU time 102.39 seconds
Started Aug 28 10:45:56 PM UTC 24
Finished Aug 28 10:47:40 PM UTC 24
Peak memory 1319156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160192525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.4160192525
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2079766747
Short name T1576
Test name
Test status
Simulation time 1386912731 ps
CPU time 13.92 seconds
Started Aug 28 10:46:21 PM UTC 24
Finished Aug 28 10:46:36 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079766747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2079766747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_override.1198849087
Short name T1540
Test name
Test status
Simulation time 49225171 ps
CPU time 0.86 seconds
Started Aug 28 10:45:55 PM UTC 24
Finished Aug 28 10:45:57 PM UTC 24
Peak memory 214336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198849087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1198849087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_perf.1215250758
Short name T1569
Test name
Test status
Simulation time 6552767525 ps
CPU time 31.97 seconds
Started Aug 28 10:45:58 PM UTC 24
Finished Aug 28 10:46:32 PM UTC 24
Peak memory 216912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215250758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1215250758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.4027342711
Short name T1558
Test name
Test status
Simulation time 1504512936 ps
CPU time 20.66 seconds
Started Aug 28 10:45:58 PM UTC 24
Finished Aug 28 10:46:20 PM UTC 24
Peak memory 288728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027342711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.4027342711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.4007603610
Short name T1600
Test name
Test status
Simulation time 5787891112 ps
CPU time 62.32 seconds
Started Aug 28 10:45:55 PM UTC 24
Finished Aug 28 10:46:59 PM UTC 24
Peak memory 330048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007603610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.4007603610
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.19120765
Short name T1551
Test name
Test status
Simulation time 1941375875 ps
CPU time 10.15 seconds
Started Aug 28 10:46:00 PM UTC 24
Finished Aug 28 10:46:11 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19120765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.19120765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.1312303845
Short name T1563
Test name
Test status
Simulation time 811667659 ps
CPU time 6.07 seconds
Started Aug 28 10:46:18 PM UTC 24
Finished Aug 28 10:46:25 PM UTC 24
Peak memory 229116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1312303845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad
dr.1312303845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.2252084699
Short name T1554
Test name
Test status
Simulation time 321828115 ps
CPU time 2.44 seconds
Started Aug 28 10:46:12 PM UTC 24
Finished Aug 28 10:46:16 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252084
699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.2252084699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.2084462797
Short name T1556
Test name
Test status
Simulation time 1030811027 ps
CPU time 2.06 seconds
Started Aug 28 10:46:14 PM UTC 24
Finished Aug 28 10:46:18 PM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084462
797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.2084462797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.3657884573
Short name T1566
Test name
Test status
Simulation time 912593106 ps
CPU time 4.08 seconds
Started Aug 28 10:46:23 PM UTC 24
Finished Aug 28 10:46:28 PM UTC 24
Peak memory 216312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657884
573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.3657884573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.2677222476
Short name T1564
Test name
Test status
Simulation time 149786940 ps
CPU time 1.83 seconds
Started Aug 28 10:46:23 PM UTC 24
Finished Aug 28 10:46:26 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677222
476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermark
s_tx.2677222476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.2127433854
Short name T1557
Test name
Test status
Simulation time 4508494857 ps
CPU time 9.78 seconds
Started Aug 28 10:46:07 PM UTC 24
Finished Aug 28 10:46:18 PM UTC 24
Peak memory 233084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212743
3854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.2127433854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2376200963
Short name T1737
Test name
Test status
Simulation time 41502276718 ps
CPU time 929.49 seconds
Started Aug 28 10:46:08 PM UTC 24
Finished Aug 28 11:01:47 PM UTC 24
Peak memory 10447068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2376200963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stres
s_wr.2376200963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.3520527960
Short name T1568
Test name
Test status
Simulation time 507852342 ps
CPU time 4.37 seconds
Started Aug 28 10:46:25 PM UTC 24
Finished Aug 28 10:46:31 PM UTC 24
Peak memory 226940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520527
960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.3520527960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1631281157
Short name T1571
Test name
Test status
Simulation time 926042503 ps
CPU time 4.33 seconds
Started Aug 28 10:46:27 PM UTC 24
Finished Aug 28 10:46:33 PM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631281
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.1631281157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_perf.313587712
Short name T1562
Test name
Test status
Simulation time 4418212859 ps
CPU time 6.67 seconds
Started Aug 28 10:46:17 PM UTC 24
Finished Aug 28 10:46:24 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135877
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.313587712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.996792196
Short name T1565
Test name
Test status
Simulation time 471734637 ps
CPU time 4.58 seconds
Started Aug 28 10:46:25 PM UTC 24
Finished Aug 28 10:46:31 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9967921
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.996792196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2285053194
Short name T1555
Test name
Test status
Simulation time 1326985246 ps
CPU time 12.17 seconds
Started Aug 28 10:46:03 PM UTC 24
Finished Aug 28 10:46:16 PM UTC 24
Peak memory 233552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285053194 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.2285053194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.2869482827
Short name T1648
Test name
Test status
Simulation time 53672164857 ps
CPU time 99.56 seconds
Started Aug 28 10:46:17 PM UTC 24
Finished Aug 28 10:47:58 PM UTC 24
Peak memory 745876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286948
2827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.2869482827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.1742289678
Short name T1567
Test name
Test status
Simulation time 4902635034 ps
CPU time 21.94 seconds
Started Aug 28 10:46:07 PM UTC 24
Finished Aug 28 10:46:30 PM UTC 24
Peak memory 231656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742289678 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.1742289678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1910005378
Short name T1696
Test name
Test status
Simulation time 27161499638 ps
CPU time 163.78 seconds
Started Aug 28 10:46:03 PM UTC 24
Finished Aug 28 10:48:49 PM UTC 24
Peak memory 1943772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910005378 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.1910005378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3231258987
Short name T1599
Test name
Test status
Simulation time 2279179677 ps
CPU time 50.24 seconds
Started Aug 28 10:46:07 PM UTC 24
Finished Aug 28 10:46:59 PM UTC 24
Peak memory 719052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231258987 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.3231258987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.3831493892
Short name T1560
Test name
Test status
Simulation time 1234420182 ps
CPU time 10.19 seconds
Started Aug 28 10:46:11 PM UTC 24
Finished Aug 28 10:46:23 PM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831493
892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.3831493892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_alert_test.459811936
Short name T1603
Test name
Test status
Simulation time 119087143 ps
CPU time 0.95 seconds
Started Aug 28 10:47:00 PM UTC 24
Finished Aug 28 10:47:02 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459811936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.459811936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.2361336202
Short name T1582
Test name
Test status
Simulation time 297222982 ps
CPU time 5.25 seconds
Started Aug 28 10:46:36 PM UTC 24
Finished Aug 28 10:46:43 PM UTC 24
Peak memory 226900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361336202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2361336202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.3591511254
Short name T1580
Test name
Test status
Simulation time 275464938 ps
CPU time 6.06 seconds
Started Aug 28 10:46:33 PM UTC 24
Finished Aug 28 10:46:40 PM UTC 24
Peak memory 274456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591511254 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.3591511254
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1798119230
Short name T1674
Test name
Test status
Simulation time 3018520622 ps
CPU time 104.72 seconds
Started Aug 28 10:46:34 PM UTC 24
Finished Aug 28 10:48:21 PM UTC 24
Peak memory 590168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798119230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1798119230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.974356298
Short name T1625
Test name
Test status
Simulation time 5158303295 ps
CPU time 53.41 seconds
Started Aug 28 10:46:33 PM UTC 24
Finished Aug 28 10:47:28 PM UTC 24
Peak memory 596200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974356298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.974356298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2252139592
Short name T1577
Test name
Test status
Simulation time 163558958 ps
CPU time 2.31 seconds
Started Aug 28 10:46:33 PM UTC 24
Finished Aug 28 10:46:37 PM UTC 24
Peak memory 216760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252139592 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.2252139592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2875075608
Short name T1583
Test name
Test status
Simulation time 231449448 ps
CPU time 8.84 seconds
Started Aug 28 10:46:34 PM UTC 24
Finished Aug 28 10:46:44 PM UTC 24
Peak memory 258124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875075608 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.2875075608
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3459547612
Short name T1708
Test name
Test status
Simulation time 4154934599 ps
CPU time 240.63 seconds
Started Aug 28 10:46:32 PM UTC 24
Finished Aug 28 10:50:36 PM UTC 24
Peak memory 1102048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459547612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3459547612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.1052624638
Short name T1610
Test name
Test status
Simulation time 804437359 ps
CPU time 8.53 seconds
Started Aug 28 10:46:55 PM UTC 24
Finished Aug 28 10:47:04 PM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052624638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1052624638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_override.2057552743
Short name T1574
Test name
Test status
Simulation time 55273946 ps
CPU time 0.99 seconds
Started Aug 28 10:46:32 PM UTC 24
Finished Aug 28 10:46:34 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057552743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2057552743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_perf.624126655
Short name T1627
Test name
Test status
Simulation time 25505107758 ps
CPU time 56.81 seconds
Started Aug 28 10:46:34 PM UTC 24
Finished Aug 28 10:47:32 PM UTC 24
Peak memory 299284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624126655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.624126655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2116903250
Short name T1578
Test name
Test status
Simulation time 234013226 ps
CPU time 2.36 seconds
Started Aug 28 10:46:34 PM UTC 24
Finished Aug 28 10:46:37 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116903250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.2116903250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1626116708
Short name T1661
Test name
Test status
Simulation time 12414104145 ps
CPU time 101.35 seconds
Started Aug 28 10:46:31 PM UTC 24
Finished Aug 28 10:48:14 PM UTC 24
Peak memory 397516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626116708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1626116708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.2301255395
Short name T1589
Test name
Test status
Simulation time 668130351 ps
CPU time 15.86 seconds
Started Aug 28 10:46:35 PM UTC 24
Finished Aug 28 10:46:52 PM UTC 24
Peak memory 231220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301255395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2301255395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.427606456
Short name T1592
Test name
Test status
Simulation time 454373602 ps
CPU time 1.78 seconds
Started Aug 28 10:46:51 PM UTC 24
Finished Aug 28 10:46:54 PM UTC 24
Peak memory 218504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276064
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.427606456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.1970052957
Short name T1593
Test name
Test status
Simulation time 310561886 ps
CPU time 1.53 seconds
Started Aug 28 10:46:52 PM UTC 24
Finished Aug 28 10:46:55 PM UTC 24
Peak memory 226488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970052
957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.1970052957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.3075971319
Short name T1601
Test name
Test status
Simulation time 5129086927 ps
CPU time 4.5 seconds
Started Aug 28 10:46:55 PM UTC 24
Finished Aug 28 10:47:00 PM UTC 24
Peak memory 216960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075971
319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar
ks_acq.3075971319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.898417072
Short name T1597
Test name
Test status
Simulation time 206429255 ps
CPU time 1.31 seconds
Started Aug 28 10:46:56 PM UTC 24
Finished Aug 28 10:46:58 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8984170
72 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermarks
_tx.898417072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2577989344
Short name T1596
Test name
Test status
Simulation time 1172466581 ps
CPU time 2.84 seconds
Started Aug 28 10:46:53 PM UTC 24
Finished Aug 28 10:46:57 PM UTC 24
Peak memory 226692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577989
344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_hrst.2577989344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2980332018
Short name T1584
Test name
Test status
Simulation time 1061418912 ps
CPU time 6.93 seconds
Started Aug 28 10:46:42 PM UTC 24
Finished Aug 28 10:46:50 PM UTC 24
Peak memory 228860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298033
2018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.2980332018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2425908794
Short name T1677
Test name
Test status
Simulation time 14842961785 ps
CPU time 228.97 seconds
Started Aug 28 10:46:44 PM UTC 24
Finished Aug 28 10:50:36 PM UTC 24
Peak memory 3793044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2425908794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stres
s_wr.2425908794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.3886264469
Short name T1608
Test name
Test status
Simulation time 3629077414 ps
CPU time 4.87 seconds
Started Aug 28 10:46:58 PM UTC 24
Finished Aug 28 10:47:04 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886264
469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.3886264469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.257536954
Short name T1611
Test name
Test status
Simulation time 573308909 ps
CPU time 4.35 seconds
Started Aug 28 10:46:59 PM UTC 24
Finished Aug 28 10:47:04 PM UTC 24
Peak memory 216472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575369
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.257536954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.2278346780
Short name T1604
Test name
Test status
Simulation time 2521814636 ps
CPU time 2.41 seconds
Started Aug 28 10:46:59 PM UTC 24
Finished Aug 28 10:47:02 PM UTC 24
Peak memory 233420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278346
780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_txstretch.2278346780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2088905176
Short name T1602
Test name
Test status
Simulation time 2036951173 ps
CPU time 7.12 seconds
Started Aug 28 10:46:52 PM UTC 24
Finished Aug 28 10:47:00 PM UTC 24
Peak memory 229064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088905
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.2088905176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2654630845
Short name T1605
Test name
Test status
Simulation time 6376053773 ps
CPU time 3.86 seconds
Started Aug 28 10:46:58 PM UTC 24
Finished Aug 28 10:47:03 PM UTC 24
Peak memory 216496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654630
845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.2654630845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.3836182633
Short name T1585
Test name
Test status
Simulation time 2512515785 ps
CPU time 10.62 seconds
Started Aug 28 10:46:37 PM UTC 24
Finished Aug 28 10:46:50 PM UTC 24
Peak memory 226984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836182633 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.3836182633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.1399466624
Short name T1653
Test name
Test status
Simulation time 30773440254 ps
CPU time 74.75 seconds
Started Aug 28 10:46:52 PM UTC 24
Finished Aug 28 10:48:09 PM UTC 24
Peak memory 1085732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139946
6624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.1399466624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1166460374
Short name T1612
Test name
Test status
Simulation time 4863181397 ps
CPU time 24.08 seconds
Started Aug 28 10:46:40 PM UTC 24
Finished Aug 28 10:47:05 PM UTC 24
Peak memory 243920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166460374 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.1166460374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2062094212
Short name T1684
Test name
Test status
Simulation time 38001230257 ps
CPU time 112.94 seconds
Started Aug 28 10:46:39 PM UTC 24
Finished Aug 28 10:48:34 PM UTC 24
Peak memory 2064472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062094212 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.2062094212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1522039494
Short name T1586
Test name
Test status
Simulation time 3053574263 ps
CPU time 9.1 seconds
Started Aug 28 10:46:41 PM UTC 24
Finished Aug 28 10:46:51 PM UTC 24
Peak memory 321688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522039494 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.1522039494
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.3131138272
Short name T1598
Test name
Test status
Simulation time 5259252586 ps
CPU time 12.29 seconds
Started Aug 28 10:46:45 PM UTC 24
Finished Aug 28 10:46:58 PM UTC 24
Peak memory 231092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131138
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.3131138272
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3848494445
Short name T1606
Test name
Test status
Simulation time 240470964 ps
CPU time 5.24 seconds
Started Aug 28 10:46:57 PM UTC 24
Finished Aug 28 10:47:03 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848494
445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3848494445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1864820947
Short name T1640
Test name
Test status
Simulation time 19553164 ps
CPU time 0.91 seconds
Started Aug 28 10:47:41 PM UTC 24
Finished Aug 28 10:47:43 PM UTC 24
Peak memory 215824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864820947 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1864820947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2418913729
Short name T1615
Test name
Test status
Simulation time 85814100 ps
CPU time 2.28 seconds
Started Aug 28 10:47:06 PM UTC 24
Finished Aug 28 10:47:09 PM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418913729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2418913729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3732061084
Short name T1616
Test name
Test status
Simulation time 242300386 ps
CPU time 7.27 seconds
Started Aug 28 10:47:03 PM UTC 24
Finished Aug 28 10:47:12 PM UTC 24
Peak memory 262428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732061084 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.3732061084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1839692969
Short name T1711
Test name
Test status
Simulation time 2040209033 ps
CPU time 123.46 seconds
Started Aug 28 10:47:05 PM UTC 24
Finished Aug 28 10:49:10 PM UTC 24
Peak memory 473284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839692969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1839692969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.4234959136
Short name T1719
Test name
Test status
Simulation time 3601257287 ps
CPU time 160.65 seconds
Started Aug 28 10:47:03 PM UTC 24
Finished Aug 28 10:49:48 PM UTC 24
Peak memory 813516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234959136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.4234959136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.532157219
Short name T1613
Test name
Test status
Simulation time 144490338 ps
CPU time 1.48 seconds
Started Aug 28 10:47:03 PM UTC 24
Finished Aug 28 10:47:06 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532157219 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.532157219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.577838758
Short name T1617
Test name
Test status
Simulation time 401339716 ps
CPU time 7.85 seconds
Started Aug 28 10:47:05 PM UTC 24
Finished Aug 28 10:47:13 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577838758 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.577838758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.3886080939
Short name T1660
Test name
Test status
Simulation time 3718558966 ps
CPU time 71 seconds
Started Aug 28 10:47:01 PM UTC 24
Finished Aug 28 10:48:14 PM UTC 24
Peak memory 1011928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886080939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3886080939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3471027563
Short name T1636
Test name
Test status
Simulation time 689162454 ps
CPU time 6.03 seconds
Started Aug 28 10:47:33 PM UTC 24
Finished Aug 28 10:47:40 PM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471027563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3471027563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_override.1222980747
Short name T1607
Test name
Test status
Simulation time 88801355 ps
CPU time 1.08 seconds
Started Aug 28 10:47:01 PM UTC 24
Finished Aug 28 10:47:03 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222980747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1222980747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1050614173
Short name T1722
Test name
Test status
Simulation time 7242922611 ps
CPU time 173.35 seconds
Started Aug 28 10:47:05 PM UTC 24
Finished Aug 28 10:50:01 PM UTC 24
Peak memory 216692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050614173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1050614173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.4254954449
Short name T1614
Test name
Test status
Simulation time 74442154 ps
CPU time 1.4 seconds
Started Aug 28 10:47:05 PM UTC 24
Finished Aug 28 10:47:07 PM UTC 24
Peak memory 214268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254954449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.4254954449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1146694798
Short name T1650
Test name
Test status
Simulation time 1136417124 ps
CPU time 65.53 seconds
Started Aug 28 10:47:00 PM UTC 24
Finished Aug 28 10:48:07 PM UTC 24
Peak memory 399568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146694798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1146694798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3820017164
Short name T1639
Test name
Test status
Simulation time 783547589 ps
CPU time 35.72 seconds
Started Aug 28 10:47:05 PM UTC 24
Finished Aug 28 10:47:42 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820017164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3820017164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.1984410330
Short name T1629
Test name
Test status
Simulation time 1890533617 ps
CPU time 8.4 seconds
Started Aug 28 10:47:26 PM UTC 24
Finished Aug 28 10:47:35 PM UTC 24
Peak memory 233272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1984410330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad
dr.1984410330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.1601289317
Short name T1621
Test name
Test status
Simulation time 328339623 ps
CPU time 1.84 seconds
Started Aug 28 10:47:20 PM UTC 24
Finished Aug 28 10:47:22 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601289
317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.1601289317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2563183646
Short name T1623
Test name
Test status
Simulation time 1007192576 ps
CPU time 1.89 seconds
Started Aug 28 10:47:23 PM UTC 24
Finished Aug 28 10:47:26 PM UTC 24
Peak memory 216552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563183
646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.2563183646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.2515274931
Short name T1631
Test name
Test status
Simulation time 357546241 ps
CPU time 3.99 seconds
Started Aug 28 10:47:33 PM UTC 24
Finished Aug 28 10:47:38 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515274
931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermar
ks_acq.2515274931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1287966563
Short name T1630
Test name
Test status
Simulation time 513014145 ps
CPU time 2.04 seconds
Started Aug 28 10:47:34 PM UTC 24
Finished Aug 28 10:47:37 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287966
563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_tx.1287966563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.3536348419
Short name T1626
Test name
Test status
Simulation time 199379593 ps
CPU time 2.95 seconds
Started Aug 28 10:47:28 PM UTC 24
Finished Aug 28 10:47:32 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536348
419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_hrst.3536348419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2925046221
Short name T1622
Test name
Test status
Simulation time 1408938180 ps
CPU time 11.86 seconds
Started Aug 28 10:47:12 PM UTC 24
Finished Aug 28 10:47:25 PM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292504
6221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.2925046221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3365334564
Short name T1632
Test name
Test status
Simulation time 11543687251 ps
CPU time 22.94 seconds
Started Aug 28 10:47:14 PM UTC 24
Finished Aug 28 10:47:39 PM UTC 24
Peak memory 354520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3365334564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.3365334564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.40266261
Short name T1645
Test name
Test status
Simulation time 2177308866 ps
CPU time 4.47 seconds
Started Aug 28 10:47:39 PM UTC 24
Finished Aug 28 10:47:44 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026626
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.40266261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.1493365783
Short name T1644
Test name
Test status
Simulation time 4276824801 ps
CPU time 4.3 seconds
Started Aug 28 10:47:39 PM UTC 24
Finished Aug 28 10:47:44 PM UTC 24
Peak memory 216656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493365
783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad
dr.1493365783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3567748201
Short name T1642
Test name
Test status
Simulation time 688676580 ps
CPU time 2.67 seconds
Started Aug 28 10:47:40 PM UTC 24
Finished Aug 28 10:47:43 PM UTC 24
Peak memory 233412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567748
201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.3567748201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_perf.4058320760
Short name T1628
Test name
Test status
Simulation time 2785955177 ps
CPU time 9.35 seconds
Started Aug 28 10:47:24 PM UTC 24
Finished Aug 28 10:47:34 PM UTC 24
Peak memory 226888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058320
760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.4058320760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.661514067
Short name T1637
Test name
Test status
Simulation time 1706228774 ps
CPU time 2.86 seconds
Started Aug 28 10:47:36 PM UTC 24
Finished Aug 28 10:47:40 PM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6615140
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.661514067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.3860592211
Short name T1635
Test name
Test status
Simulation time 3682238950 ps
CPU time 32.86 seconds
Started Aug 28 10:47:06 PM UTC 24
Finished Aug 28 10:47:40 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860592211 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.3860592211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1098949773
Short name T1712
Test name
Test status
Simulation time 23304881293 ps
CPU time 107.07 seconds
Started Aug 28 10:47:26 PM UTC 24
Finished Aug 28 10:49:15 PM UTC 24
Peak memory 807344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109894
9773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.1098949773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.133649972
Short name T1643
Test name
Test status
Simulation time 1406342783 ps
CPU time 33.84 seconds
Started Aug 28 10:47:08 PM UTC 24
Finished Aug 28 10:47:43 PM UTC 24
Peak memory 233660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133649972 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.133649972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1353931107
Short name T1735
Test name
Test status
Simulation time 47031133861 ps
CPU time 644.53 seconds
Started Aug 28 10:47:07 PM UTC 24
Finished Aug 28 10:57:59 PM UTC 24
Peak memory 6949016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353931107 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.1353931107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.4169095114
Short name T1624
Test name
Test status
Simulation time 1217633233 ps
CPU time 10.46 seconds
Started Aug 28 10:47:15 PM UTC 24
Finished Aug 28 10:47:27 PM UTC 24
Peak memory 233512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169095
114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.4169095114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2263949218
Short name T1634
Test name
Test status
Simulation time 94261071 ps
CPU time 3.69 seconds
Started Aug 28 10:47:35 PM UTC 24
Finished Aug 28 10:47:40 PM UTC 24
Peak memory 216456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263949
218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2263949218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1119008262
Short name T1667
Test name
Test status
Simulation time 76461104 ps
CPU time 0.96 seconds
Started Aug 28 10:48:16 PM UTC 24
Finished Aug 28 10:48:19 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119008262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1119008262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1973892438
Short name T1595
Test name
Test status
Simulation time 254926775 ps
CPU time 3 seconds
Started Aug 28 10:47:46 PM UTC 24
Finished Aug 28 10:47:50 PM UTC 24
Peak memory 227200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973892438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1973892438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.3010176774
Short name T1570
Test name
Test status
Simulation time 459603765 ps
CPU time 4.55 seconds
Started Aug 28 10:47:43 PM UTC 24
Finished Aug 28 10:47:49 PM UTC 24
Peak memory 237588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010176774 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.3010176774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.725052282
Short name T1717
Test name
Test status
Simulation time 2035901203 ps
CPU time 113.58 seconds
Started Aug 28 10:47:43 PM UTC 24
Finished Aug 28 10:49:39 PM UTC 24
Peak memory 446796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725052282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.725052282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.1477702831
Short name T1715
Test name
Test status
Simulation time 3374263515 ps
CPU time 105.16 seconds
Started Aug 28 10:47:41 PM UTC 24
Finished Aug 28 10:49:28 PM UTC 24
Peak memory 596200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477702831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1477702831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2466625652
Short name T1646
Test name
Test status
Simulation time 400318251 ps
CPU time 1.4 seconds
Started Aug 28 10:47:42 PM UTC 24
Finished Aug 28 10:47:44 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466625652 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.2466625652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.74990000
Short name T1633
Test name
Test status
Simulation time 634264619 ps
CPU time 13.38 seconds
Started Aug 28 10:47:43 PM UTC 24
Finished Aug 28 10:47:58 PM UTC 24
Peak memory 251924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74990000 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.74990000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3395317210
Short name T1699
Test name
Test status
Simulation time 5274823437 ps
CPU time 70.04 seconds
Started Aug 28 10:47:41 PM UTC 24
Finished Aug 28 10:48:53 PM UTC 24
Peak memory 891288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395317210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3395317210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2423714998
Short name T1671
Test name
Test status
Simulation time 2410432036 ps
CPU time 7.41 seconds
Started Aug 28 10:48:11 PM UTC 24
Finished Aug 28 10:48:20 PM UTC 24
Peak memory 216776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423714998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2423714998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_override.549308557
Short name T1641
Test name
Test status
Simulation time 18549821 ps
CPU time 0.97 seconds
Started Aug 28 10:47:41 PM UTC 24
Finished Aug 28 10:47:43 PM UTC 24
Peak memory 215236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549308557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.549308557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_perf.2006205085
Short name T1681
Test name
Test status
Simulation time 3223763248 ps
CPU time 42.72 seconds
Started Aug 28 10:47:44 PM UTC 24
Finished Aug 28 10:48:29 PM UTC 24
Peak memory 216892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006205085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2006205085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.755389879
Short name T1647
Test name
Test status
Simulation time 57139688 ps
CPU time 1.67 seconds
Started Aug 28 10:47:44 PM UTC 24
Finished Aug 28 10:47:47 PM UTC 24
Peak memory 214264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755389879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.755389879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2552470546
Short name T1693
Test name
Test status
Simulation time 6386624816 ps
CPU time 65.74 seconds
Started Aug 28 10:47:41 PM UTC 24
Finished Aug 28 10:48:48 PM UTC 24
Peak memory 309564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552470546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2552470546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2206913149
Short name T1649
Test name
Test status
Simulation time 8823505831 ps
CPU time 18.73 seconds
Started Aug 28 10:47:44 PM UTC 24
Finished Aug 28 10:48:04 PM UTC 24
Peak memory 233916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206913149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2206913149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3332044314
Short name T1665
Test name
Test status
Simulation time 2974711439 ps
CPU time 4.63 seconds
Started Aug 28 10:48:10 PM UTC 24
Finished Aug 28 10:48:16 PM UTC 24
Peak memory 229004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3332044314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad
dr.3332044314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.2219789092
Short name T1654
Test name
Test status
Simulation time 422905204 ps
CPU time 2.52 seconds
Started Aug 28 10:48:05 PM UTC 24
Finished Aug 28 10:48:09 PM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219789
092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.2219789092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1727766855
Short name T1656
Test name
Test status
Simulation time 184031589 ps
CPU time 2.01 seconds
Started Aug 28 10:48:07 PM UTC 24
Finished Aug 28 10:48:10 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727766
855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.1727766855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3984179360
Short name T1666
Test name
Test status
Simulation time 583968591 ps
CPU time 4.65 seconds
Started Aug 28 10:48:11 PM UTC 24
Finished Aug 28 10:48:17 PM UTC 24
Peak memory 216460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984179
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar
ks_acq.3984179360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2360276068
Short name T1662
Test name
Test status
Simulation time 238149685 ps
CPU time 1.4 seconds
Started Aug 28 10:48:12 PM UTC 24
Finished Aug 28 10:48:14 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360276
068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.2360276068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.472126762
Short name T1663
Test name
Test status
Simulation time 748441688 ps
CPU time 4.08 seconds
Started Aug 28 10:48:10 PM UTC 24
Finished Aug 28 10:48:15 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4721267
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_hrst.472126762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.294333814
Short name T1659
Test name
Test status
Simulation time 7081741547 ps
CPU time 13.07 seconds
Started Aug 28 10:47:58 PM UTC 24
Finished Aug 28 10:48:12 PM UTC 24
Peak memory 226956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294333
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.294333814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2280001675
Short name T1716
Test name
Test status
Simulation time 15978950512 ps
CPU time 96.35 seconds
Started Aug 28 10:47:59 PM UTC 24
Finished Aug 28 10:49:37 PM UTC 24
Peak memory 1980892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2280001675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres
s_wr.2280001675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.2440916401
Short name T1675
Test name
Test status
Simulation time 3666942287 ps
CPU time 4.62 seconds
Started Aug 28 10:48:15 PM UTC 24
Finished Aug 28 10:48:21 PM UTC 24
Peak memory 227248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440916
401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.2440916401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.4090862327
Short name T1672
Test name
Test status
Simulation time 541226612 ps
CPU time 3.66 seconds
Started Aug 28 10:48:15 PM UTC 24
Finished Aug 28 10:48:20 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090862
327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_ad
dr.4090862327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.924485954
Short name T1669
Test name
Test status
Simulation time 295654251 ps
CPU time 2.12 seconds
Started Aug 28 10:48:15 PM UTC 24
Finished Aug 28 10:48:19 PM UTC 24
Peak memory 233432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9244859
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_txstretch.924485954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_perf.1572921335
Short name T1664
Test name
Test status
Simulation time 1040801636 ps
CPU time 6.04 seconds
Started Aug 28 10:48:08 PM UTC 24
Finished Aug 28 10:48:16 PM UTC 24
Peak memory 233752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572921
335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.1572921335
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.763354315
Short name T1670
Test name
Test status
Simulation time 8735140370 ps
CPU time 4.76 seconds
Started Aug 28 10:48:13 PM UTC 24
Finished Aug 28 10:48:19 PM UTC 24
Peak memory 216428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7633543
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.763354315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2303450266
Short name T1679
Test name
Test status
Simulation time 977731093 ps
CPU time 35.41 seconds
Started Aug 28 10:47:48 PM UTC 24
Finished Aug 28 10:48:25 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303450266 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.2303450266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3005572210
Short name T1714
Test name
Test status
Simulation time 109270884072 ps
CPU time 73.9 seconds
Started Aug 28 10:48:09 PM UTC 24
Finished Aug 28 10:49:24 PM UTC 24
Peak memory 645280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300557
2210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.3005572210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.67892674
Short name T1587
Test name
Test status
Simulation time 310148822 ps
CPU time 5.42 seconds
Started Aug 28 10:47:51 PM UTC 24
Finished Aug 28 10:47:57 PM UTC 24
Peak memory 216772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67892674 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.67892674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1497423054
Short name T1655
Test name
Test status
Simulation time 16167515967 ps
CPU time 18.78 seconds
Started Aug 28 10:47:50 PM UTC 24
Finished Aug 28 10:48:10 PM UTC 24
Peak memory 216820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497423054 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1497423054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.873425843
Short name T1657
Test name
Test status
Simulation time 6892690462 ps
CPU time 9.39 seconds
Started Aug 28 10:47:59 PM UTC 24
Finished Aug 28 10:48:11 PM UTC 24
Peak memory 234052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8734258
43 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.873425843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.2476733711
Short name T1673
Test name
Test status
Simulation time 177465147 ps
CPU time 5.86 seconds
Started Aug 28 10:48:13 PM UTC 24
Finished Aug 28 10:48:21 PM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476733
711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2476733711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_alert_test.2966412662
Short name T1702
Test name
Test status
Simulation time 47629984 ps
CPU time 0.94 seconds
Started Aug 28 10:48:54 PM UTC 24
Finished Aug 28 10:48:56 PM UTC 24
Peak memory 214320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966412662 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2966412662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.328377175
Short name T1686
Test name
Test status
Simulation time 257989168 ps
CPU time 11.69 seconds
Started Aug 28 10:48:22 PM UTC 24
Finished Aug 28 10:48:35 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328377175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.328377175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.1358692268
Short name T1682
Test name
Test status
Simulation time 279240007 ps
CPU time 8.05 seconds
Started Aug 28 10:48:20 PM UTC 24
Finished Aug 28 10:48:29 PM UTC 24
Peak memory 270356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358692268 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.1358692268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.3045682743
Short name T1658
Test name
Test status
Simulation time 12765202536 ps
CPU time 154.41 seconds
Started Aug 28 10:48:21 PM UTC 24
Finished Aug 28 10:50:58 PM UTC 24
Peak memory 226948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045682743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3045682743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2836965840
Short name T1718
Test name
Test status
Simulation time 2411913618 ps
CPU time 79.09 seconds
Started Aug 28 10:48:20 PM UTC 24
Finished Aug 28 10:49:41 PM UTC 24
Peak memory 688400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836965840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2836965840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2246441961
Short name T1676
Test name
Test status
Simulation time 90046431 ps
CPU time 1.28 seconds
Started Aug 28 10:48:20 PM UTC 24
Finished Aug 28 10:48:22 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246441961 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.2246441961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.788403865
Short name T1680
Test name
Test status
Simulation time 601318890 ps
CPU time 5.41 seconds
Started Aug 28 10:48:21 PM UTC 24
Finished Aug 28 10:48:27 PM UTC 24
Peak memory 216540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788403865 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.788403865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3669698984
Short name T1723
Test name
Test status
Simulation time 17631733267 ps
CPU time 131.22 seconds
Started Aug 28 10:48:18 PM UTC 24
Finished Aug 28 10:50:31 PM UTC 24
Peak memory 1597660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669698984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3669698984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3329401652
Short name T1707
Test name
Test status
Simulation time 384429646 ps
CPU time 7.12 seconds
Started Aug 28 10:48:48 PM UTC 24
Finished Aug 28 10:48:57 PM UTC 24
Peak memory 216520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329401652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3329401652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_override.3270726572
Short name T1668
Test name
Test status
Simulation time 18200422 ps
CPU time 0.96 seconds
Started Aug 28 10:48:17 PM UTC 24
Finished Aug 28 10:48:19 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270726572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3270726572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_perf.4290956888
Short name T46
Test name
Test status
Simulation time 30144883619 ps
CPU time 135.93 seconds
Started Aug 28 10:48:21 PM UTC 24
Finished Aug 28 10:50:39 PM UTC 24
Peak memory 1245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290956888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.4290956888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3328914723
Short name T1678
Test name
Test status
Simulation time 84841329 ps
CPU time 1.7 seconds
Started Aug 28 10:48:21 PM UTC 24
Finished Aug 28 10:48:24 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328914723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.3328914723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.3219735842
Short name T1703
Test name
Test status
Simulation time 3111944100 ps
CPU time 38.29 seconds
Started Aug 28 10:48:16 PM UTC 24
Finished Aug 28 10:48:56 PM UTC 24
Peak memory 430304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219735842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3219735842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3710824527
Short name T1692
Test name
Test status
Simulation time 1769219988 ps
CPU time 24.7 seconds
Started Aug 28 10:48:22 PM UTC 24
Finished Aug 28 10:48:48 PM UTC 24
Peak memory 233520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710824527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3710824527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.3423156333
Short name T1694
Test name
Test status
Simulation time 5240517568 ps
CPU time 6.76 seconds
Started Aug 28 10:48:41 PM UTC 24
Finished Aug 28 10:48:49 PM UTC 24
Peak memory 229008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3423156333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad
dr.3423156333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.2651184775
Short name T1687
Test name
Test status
Simulation time 224104239 ps
CPU time 2.45 seconds
Started Aug 28 10:48:36 PM UTC 24
Finished Aug 28 10:48:40 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651184
775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.2651184775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.3321456133
Short name T1690
Test name
Test status
Simulation time 214796506 ps
CPU time 2.05 seconds
Started Aug 28 10:48:40 PM UTC 24
Finished Aug 28 10:48:43 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321456
133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.3321456133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1999216136
Short name T1701
Test name
Test status
Simulation time 1119775901 ps
CPU time 4.87 seconds
Started Aug 28 10:48:50 PM UTC 24
Finished Aug 28 10:48:55 PM UTC 24
Peak memory 216576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999216
136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermar
ks_acq.1999216136
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.4169682520
Short name T1698
Test name
Test status
Simulation time 357980553 ps
CPU time 1.54 seconds
Started Aug 28 10:48:50 PM UTC 24
Finished Aug 28 10:48:52 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169682
520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark
s_tx.4169682520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1081858142
Short name T1689
Test name
Test status
Simulation time 995802780 ps
CPU time 9.79 seconds
Started Aug 28 10:48:30 PM UTC 24
Finished Aug 28 10:48:41 PM UTC 24
Peak memory 233932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108185
8142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.1081858142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1027882129
Short name T1725
Test name
Test status
Simulation time 27355088879 ps
CPU time 208.3 seconds
Started Aug 28 10:48:35 PM UTC 24
Finished Aug 28 10:52:06 PM UTC 24
Peak memory 3313816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1027882129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stres
s_wr.1027882129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.4220605160
Short name T1705
Test name
Test status
Simulation time 1002184903 ps
CPU time 4.51 seconds
Started Aug 28 10:48:51 PM UTC 24
Finished Aug 28 10:48:56 PM UTC 24
Peak memory 226812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220605
160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.4220605160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3588596939
Short name T1706
Test name
Test status
Simulation time 541687947 ps
CPU time 4.65 seconds
Started Aug 28 10:48:51 PM UTC 24
Finished Aug 28 10:48:57 PM UTC 24
Peak memory 216536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588596
939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.3588596939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2689586311
Short name T1697
Test name
Test status
Simulation time 722239998 ps
CPU time 9.05 seconds
Started Aug 28 10:48:40 PM UTC 24
Finished Aug 28 10:48:50 PM UTC 24
Peak memory 226756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689586
311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.2689586311
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.3106289711
Short name T1700
Test name
Test status
Simulation time 5031485284 ps
CPU time 3.11 seconds
Started Aug 28 10:48:51 PM UTC 24
Finished Aug 28 10:48:55 PM UTC 24
Peak memory 216496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106289
711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.3106289711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1853950844
Short name T1710
Test name
Test status
Simulation time 15077793455 ps
CPU time 41.24 seconds
Started Aug 28 10:48:24 PM UTC 24
Finished Aug 28 10:49:07 PM UTC 24
Peak memory 231284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853950844 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.1853950844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1195111645
Short name T1736
Test name
Test status
Simulation time 36844906961 ps
CPU time 725.52 seconds
Started Aug 28 10:48:41 PM UTC 24
Finished Aug 28 11:00:54 PM UTC 24
Peak memory 7102620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119511
1645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.1195111645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.1322014597
Short name T1713
Test name
Test status
Simulation time 4060762392 ps
CPU time 52.59 seconds
Started Aug 28 10:48:29 PM UTC 24
Finished Aug 28 10:49:23 PM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322014597 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.1322014597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.2060749092
Short name T1724
Test name
Test status
Simulation time 44229772016 ps
CPU time 138.42 seconds
Started Aug 28 10:48:25 PM UTC 24
Finished Aug 28 10:50:46 PM UTC 24
Peak memory 2154720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060749092 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.2060749092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.660575327
Short name T1685
Test name
Test status
Simulation time 204128543 ps
CPU time 3.46 seconds
Started Aug 28 10:48:30 PM UTC 24
Finished Aug 28 10:48:34 PM UTC 24
Peak memory 216448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660575327 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.660575327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3758810435
Short name T1691
Test name
Test status
Simulation time 1331949339 ps
CPU time 10.7 seconds
Started Aug 28 10:48:35 PM UTC 24
Finished Aug 28 10:48:47 PM UTC 24
Peak memory 233860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758810
435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.3758810435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.3521446789
Short name T1704
Test name
Test status
Simulation time 118388019 ps
CPU time 4.59 seconds
Started Aug 28 10:48:51 PM UTC 24
Finished Aug 28 10:48:56 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521446
789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.3521446789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_alert_test.3766961903
Short name T332
Test name
Test status
Simulation time 19801050 ps
CPU time 0.92 seconds
Started Aug 28 10:23:03 PM UTC 24
Finished Aug 28 10:23:05 PM UTC 24
Peak memory 214316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766961903 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3766961903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.3231746976
Short name T348
Test name
Test status
Simulation time 148953328 ps
CPU time 5.48 seconds
Started Aug 28 10:22:45 PM UTC 24
Finished Aug 28 10:22:52 PM UTC 24
Peak memory 233612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231746976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3231746976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.291676158
Short name T228
Test name
Test status
Simulation time 380639064 ps
CPU time 7.37 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:22:52 PM UTC 24
Peak memory 301080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291676158 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.291676158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1561988694
Short name T409
Test name
Test status
Simulation time 6120947680 ps
CPU time 97.08 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:24:23 PM UTC 24
Peak memory 688404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561988694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1561988694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2404728361
Short name T190
Test name
Test status
Simulation time 4094550727 ps
CPU time 73.26 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:23:59 PM UTC 24
Peak memory 551060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404728361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2404728361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.65138409
Short name T255
Test name
Test status
Simulation time 282210712 ps
CPU time 1.33 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:22:46 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65138409 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.65138409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.120643400
Short name T165
Test name
Test status
Simulation time 1526058698 ps
CPU time 7.41 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:22:53 PM UTC 24
Peak memory 249936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120643400 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.120643400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.374337092
Short name T191
Test name
Test status
Simulation time 4812688669 ps
CPU time 122.55 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:24:49 PM UTC 24
Peak memory 1360080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374337092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.374337092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.2936777055
Short name T270
Test name
Test status
Simulation time 2621060668 ps
CPU time 13.59 seconds
Started Aug 28 10:22:58 PM UTC 24
Finished Aug 28 10:23:13 PM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936777055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2936777055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_override.2170182064
Short name T346
Test name
Test status
Simulation time 48902080 ps
CPU time 1.02 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:22:46 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170182064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2170182064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_perf.4104632956
Short name T98
Test name
Test status
Simulation time 7916759388 ps
CPU time 11.47 seconds
Started Aug 28 10:22:44 PM UTC 24
Finished Aug 28 10:22:57 PM UTC 24
Peak memory 364640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104632956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.4104632956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.3405532856
Short name T347
Test name
Test status
Simulation time 280823974 ps
CPU time 1.85 seconds
Started Aug 28 10:22:45 PM UTC 24
Finished Aug 28 10:22:48 PM UTC 24
Peak memory 226412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405532856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.3405532856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3492340824
Short name T363
Test name
Test status
Simulation time 1281541841 ps
CPU time 26.07 seconds
Started Aug 28 10:22:43 PM UTC 24
Finished Aug 28 10:23:10 PM UTC 24
Peak memory 309284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492340824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3492340824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.2071575258
Short name T352
Test name
Test status
Simulation time 837341603 ps
CPU time 14.13 seconds
Started Aug 28 10:22:45 PM UTC 24
Finished Aug 28 10:23:00 PM UTC 24
Peak memory 233596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071575258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2071575258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.559718956
Short name T359
Test name
Test status
Simulation time 6264121419 ps
CPU time 9.12 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:23:07 PM UTC 24
Peak memory 233956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=559718956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.559718956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.1772069546
Short name T132
Test name
Test status
Simulation time 604155692 ps
CPU time 1.65 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:22:59 PM UTC 24
Peak memory 214324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772069
546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.1772069546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.2654546194
Short name T350
Test name
Test status
Simulation time 186478254 ps
CPU time 1.16 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:22:59 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654546
194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.2654546194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.592625758
Short name T354
Test name
Test status
Simulation time 1467072471 ps
CPU time 4.58 seconds
Started Aug 28 10:22:59 PM UTC 24
Finished Aug 28 10:23:05 PM UTC 24
Peak memory 216696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5926257
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_acq.592625758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.1747041084
Short name T353
Test name
Test status
Simulation time 899231585 ps
CPU time 2.57 seconds
Started Aug 28 10:23:00 PM UTC 24
Finished Aug 28 10:23:04 PM UTC 24
Peak memory 216252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747041
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_tx.1747041084
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.1041602169
Short name T328
Test name
Test status
Simulation time 1020515103 ps
CPU time 7.26 seconds
Started Aug 28 10:22:55 PM UTC 24
Finished Aug 28 10:23:04 PM UTC 24
Peak memory 226932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104160
2169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.1041602169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.3756198398
Short name T408
Test name
Test status
Simulation time 29155483224 ps
CPU time 81.26 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:24:20 PM UTC 24
Peak memory 1601688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3756198398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress
_wr.3756198398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.2251072816
Short name T58
Test name
Test status
Simulation time 1082567041 ps
CPU time 3.23 seconds
Started Aug 28 10:23:02 PM UTC 24
Finished Aug 28 10:23:06 PM UTC 24
Peak memory 226636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251072
816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.2251072816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.2125911114
Short name T360
Test name
Test status
Simulation time 1051498369 ps
CPU time 4.55 seconds
Started Aug 28 10:23:02 PM UTC 24
Finished Aug 28 10:23:07 PM UTC 24
Peak memory 216404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125911
114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.2125911114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.3938193003
Short name T66
Test name
Test status
Simulation time 852670858 ps
CPU time 2.62 seconds
Started Aug 28 10:23:03 PM UTC 24
Finished Aug 28 10:23:06 PM UTC 24
Peak memory 233564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938193
003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_txstretch.3938193003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_perf.3323691164
Short name T99
Test name
Test status
Simulation time 1411100685 ps
CPU time 7.45 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:23:05 PM UTC 24
Peak memory 233284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323691
164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.3323691164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.3901872030
Short name T356
Test name
Test status
Simulation time 2198705294 ps
CPU time 3.27 seconds
Started Aug 28 10:23:01 PM UTC 24
Finished Aug 28 10:23:06 PM UTC 24
Peak memory 216688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901872
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.3901872030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.4101295602
Short name T362
Test name
Test status
Simulation time 759397268 ps
CPU time 13.43 seconds
Started Aug 28 10:22:55 PM UTC 24
Finished Aug 28 10:23:10 PM UTC 24
Peak memory 227128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101295602 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.4101295602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.439555451
Short name T311
Test name
Test status
Simulation time 85725620388 ps
CPU time 150.95 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:25:30 PM UTC 24
Peak memory 1241540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439555
451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.439555451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1995571291
Short name T378
Test name
Test status
Simulation time 1730947173 ps
CPU time 32.83 seconds
Started Aug 28 10:22:55 PM UTC 24
Finished Aug 28 10:23:29 PM UTC 24
Peak memory 244164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995571291 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.1995571291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.512585977
Short name T452
Test name
Test status
Simulation time 52892453118 ps
CPU time 135.56 seconds
Started Aug 28 10:22:55 PM UTC 24
Finished Aug 28 10:25:13 PM UTC 24
Peak memory 2193624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512585977 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.512585977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.4047571569
Short name T355
Test name
Test status
Simulation time 1850621021 ps
CPU time 8.12 seconds
Started Aug 28 10:22:57 PM UTC 24
Finished Aug 28 10:23:06 PM UTC 24
Peak memory 226744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047571
569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.4047571569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.2710311286
Short name T357
Test name
Test status
Simulation time 242022491 ps
CPU time 5.13 seconds
Started Aug 28 10:23:00 PM UTC 24
Finished Aug 28 10:23:07 PM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710311
286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2710311286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_alert_test.2307868538
Short name T377
Test name
Test status
Simulation time 32778208 ps
CPU time 0.79 seconds
Started Aug 28 10:23:27 PM UTC 24
Finished Aug 28 10:23:29 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307868538 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2307868538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.535135882
Short name T20
Test name
Test status
Simulation time 171314101 ps
CPU time 3.83 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:23:12 PM UTC 24
Peak memory 233552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535135882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.535135882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.304211244
Short name T364
Test name
Test status
Simulation time 232049698 ps
CPU time 3.88 seconds
Started Aug 28 10:23:06 PM UTC 24
Finished Aug 28 10:23:11 PM UTC 24
Peak memory 250136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304211244 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.304211244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.229660889
Short name T478
Test name
Test status
Simulation time 40910299438 ps
CPU time 156.16 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:25:46 PM UTC 24
Peak memory 737808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229660889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.229660889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.2518147450
Short name T503
Test name
Test status
Simulation time 2577549617 ps
CPU time 180.32 seconds
Started Aug 28 10:23:06 PM UTC 24
Finished Aug 28 10:26:09 PM UTC 24
Peak memory 811424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518147450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2518147450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.2369899485
Short name T361
Test name
Test status
Simulation time 624602582 ps
CPU time 1.95 seconds
Started Aug 28 10:23:06 PM UTC 24
Finished Aug 28 10:23:09 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369899485 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.2369899485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.1051486061
Short name T186
Test name
Test status
Simulation time 611915581 ps
CPU time 5.48 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:23:14 PM UTC 24
Peak memory 216748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051486061 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.1051486061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.3794132743
Short name T586
Test name
Test status
Simulation time 23774527769 ps
CPU time 256.19 seconds
Started Aug 28 10:23:06 PM UTC 24
Finished Aug 28 10:27:26 PM UTC 24
Peak memory 1312920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794132743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3794132743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.1329206237
Short name T278
Test name
Test status
Simulation time 1310530969 ps
CPU time 16.46 seconds
Started Aug 28 10:23:20 PM UTC 24
Finished Aug 28 10:23:38 PM UTC 24
Peak memory 216504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329206237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1329206237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_mode_toggle.3134686291
Short name T32
Test name
Test status
Simulation time 729793848 ps
CPU time 2.89 seconds
Started Aug 28 10:23:20 PM UTC 24
Finished Aug 28 10:23:24 PM UTC 24
Peak memory 216640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134686291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3134686291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_override.1796743647
Short name T358
Test name
Test status
Simulation time 108654275 ps
CPU time 0.95 seconds
Started Aug 28 10:23:05 PM UTC 24
Finished Aug 28 10:23:07 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796743647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1796743647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_perf.783543043
Short name T369
Test name
Test status
Simulation time 1966638090 ps
CPU time 10.31 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:23:19 PM UTC 24
Peak memory 266316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783543043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.783543043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.857892456
Short name T365
Test name
Test status
Simulation time 254090070 ps
CPU time 4.77 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:23:13 PM UTC 24
Peak memory 216568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857892456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.857892456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.769382734
Short name T424
Test name
Test status
Simulation time 7041170126 ps
CPU time 97.5 seconds
Started Aug 28 10:23:05 PM UTC 24
Finished Aug 28 10:24:44 PM UTC 24
Peak memory 389320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769382734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.769382734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.4054961045
Short name T283
Test name
Test status
Simulation time 1842427054 ps
CPU time 20.15 seconds
Started Aug 28 10:23:07 PM UTC 24
Finished Aug 28 10:23:29 PM UTC 24
Peak memory 233356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054961045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.4054961045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.3668495481
Short name T308
Test name
Test status
Simulation time 1430778957 ps
CPU time 6.78 seconds
Started Aug 28 10:23:18 PM UTC 24
Finished Aug 28 10:23:26 PM UTC 24
Peak memory 226764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3668495481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3668495481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.542489712
Short name T367
Test name
Test status
Simulation time 128490106 ps
CPU time 1.72 seconds
Started Aug 28 10:23:14 PM UTC 24
Finished Aug 28 10:23:17 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5424897
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.542489712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.2583794486
Short name T176
Test name
Test status
Simulation time 214499949 ps
CPU time 1.72 seconds
Started Aug 28 10:23:14 PM UTC 24
Finished Aug 28 10:23:17 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583794
486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.2583794486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1776186353
Short name T374
Test name
Test status
Simulation time 3583799619 ps
CPU time 5.65 seconds
Started Aug 28 10:23:20 PM UTC 24
Finished Aug 28 10:23:27 PM UTC 24
Peak memory 216704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776186
353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark
s_acq.1776186353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.3431322264
Short name T371
Test name
Test status
Simulation time 470016020 ps
CPU time 1.72 seconds
Started Aug 28 10:23:21 PM UTC 24
Finished Aug 28 10:23:24 PM UTC 24
Peak memory 215240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431322
264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_tx.3431322264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.1057327865
Short name T370
Test name
Test status
Simulation time 2760239376 ps
CPU time 5.81 seconds
Started Aug 28 10:23:12 PM UTC 24
Finished Aug 28 10:23:19 PM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105732
7865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.1057327865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.4040993931
Short name T509
Test name
Test status
Simulation time 17407308499 ps
CPU time 178.93 seconds
Started Aug 28 10:23:12 PM UTC 24
Finished Aug 28 10:26:13 PM UTC 24
Peak memory 2820308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4040993931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress
_wr.4040993931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.3960709734
Short name T380
Test name
Test status
Simulation time 550632739 ps
CPU time 4.59 seconds
Started Aug 28 10:23:25 PM UTC 24
Finished Aug 28 10:23:31 PM UTC 24
Peak memory 226864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960709
734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.3960709734
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.3907355786
Short name T379
Test name
Test status
Simulation time 444987019 ps
CPU time 3.63 seconds
Started Aug 28 10:23:25 PM UTC 24
Finished Aug 28 10:23:30 PM UTC 24
Peak memory 216468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907355
786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.3907355786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.957894190
Short name T67
Test name
Test status
Simulation time 260444519 ps
CPU time 1.74 seconds
Started Aug 28 10:23:27 PM UTC 24
Finished Aug 28 10:23:30 PM UTC 24
Peak memory 232680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9578941
90 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.957894190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_perf.1267639468
Short name T373
Test name
Test status
Simulation time 1361505486 ps
CPU time 8.49 seconds
Started Aug 28 10:23:16 PM UTC 24
Finished Aug 28 10:23:26 PM UTC 24
Peak memory 233252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267639
468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.1267639468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2076971165
Short name T375
Test name
Test status
Simulation time 521376061 ps
CPU time 3.83 seconds
Started Aug 28 10:23:24 PM UTC 24
Finished Aug 28 10:23:29 PM UTC 24
Peak memory 216560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076971
165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.2076971165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.919488163
Short name T383
Test name
Test status
Simulation time 2900729309 ps
CPU time 27.39 seconds
Started Aug 28 10:23:09 PM UTC 24
Finished Aug 28 10:23:37 PM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919488163 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.919488163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.2655027867
Short name T388
Test name
Test status
Simulation time 1278163529 ps
CPU time 29.72 seconds
Started Aug 28 10:23:11 PM UTC 24
Finished Aug 28 10:23:42 PM UTC 24
Peak memory 243676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655027867 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.2655027867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.2576777738
Short name T517
Test name
Test status
Simulation time 54501540593 ps
CPU time 187.08 seconds
Started Aug 28 10:23:10 PM UTC 24
Finished Aug 28 10:26:20 PM UTC 24
Peak memory 2302036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576777738 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.2576777738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.3401412157
Short name T368
Test name
Test status
Simulation time 2692300035 ps
CPU time 55.95 seconds
Started Aug 28 10:23:11 PM UTC 24
Finished Aug 28 10:24:09 PM UTC 24
Peak memory 510052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401412157 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.3401412157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.2917458043
Short name T372
Test name
Test status
Simulation time 4421924399 ps
CPU time 10.08 seconds
Started Aug 28 10:23:13 PM UTC 24
Finished Aug 28 10:23:24 PM UTC 24
Peak memory 233896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917458
043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.2917458043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.389460096
Short name T381
Test name
Test status
Simulation time 344766136 ps
CPU time 7.41 seconds
Started Aug 28 10:23:23 PM UTC 24
Finished Aug 28 10:23:31 PM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894600
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.389460096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_alert_test.3030087408
Short name T399
Test name
Test status
Simulation time 35882215 ps
CPU time 0.91 seconds
Started Aug 28 10:23:56 PM UTC 24
Finished Aug 28 10:23:57 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030087408 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3030087408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.1348947282
Short name T21
Test name
Test status
Simulation time 356428084 ps
CPU time 2.48 seconds
Started Aug 28 10:23:32 PM UTC 24
Finished Aug 28 10:23:36 PM UTC 24
Peak memory 227096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348947282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.1348947282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.1377742229
Short name T386
Test name
Test status
Simulation time 599708937 ps
CPU time 9.38 seconds
Started Aug 28 10:23:30 PM UTC 24
Finished Aug 28 10:23:40 PM UTC 24
Peak memory 243852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377742229 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.1377742229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.3273101649
Short name T547
Test name
Test status
Simulation time 31966986617 ps
CPU time 201.53 seconds
Started Aug 28 10:23:31 PM UTC 24
Finished Aug 28 10:26:56 PM UTC 24
Peak memory 626936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273101649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3273101649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.2147718016
Short name T513
Test name
Test status
Simulation time 9614208375 ps
CPU time 163.48 seconds
Started Aug 28 10:23:30 PM UTC 24
Finished Aug 28 10:26:16 PM UTC 24
Peak memory 799000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147718016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2147718016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.3529019568
Short name T256
Test name
Test status
Simulation time 879831013 ps
CPU time 2.13 seconds
Started Aug 28 10:23:30 PM UTC 24
Finished Aug 28 10:23:33 PM UTC 24
Peak memory 216700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529019568 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.3529019568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.4034868874
Short name T387
Test name
Test status
Simulation time 549831722 ps
CPU time 9.95 seconds
Started Aug 28 10:23:31 PM UTC 24
Finished Aug 28 10:23:42 PM UTC 24
Peak memory 241736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034868874 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.4034868874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.3329149220
Short name T584
Test name
Test status
Simulation time 20624031683 ps
CPU time 231.65 seconds
Started Aug 28 10:23:28 PM UTC 24
Finished Aug 28 10:27:23 PM UTC 24
Peak memory 1272060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329149220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3329149220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.3806207102
Short name T36
Test name
Test status
Simulation time 1926282907 ps
CPU time 27.08 seconds
Started Aug 28 10:23:49 PM UTC 24
Finished Aug 28 10:24:17 PM UTC 24
Peak memory 216528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806207102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3806207102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_override.1939519605
Short name T150
Test name
Test status
Simulation time 30958531 ps
CPU time 1.08 seconds
Started Aug 28 10:23:28 PM UTC 24
Finished Aug 28 10:23:31 PM UTC 24
Peak memory 214328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939519605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1939519605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_perf.2867514344
Short name T426
Test name
Test status
Simulation time 2923137426 ps
CPU time 71.62 seconds
Started Aug 28 10:23:31 PM UTC 24
Finished Aug 28 10:24:45 PM UTC 24
Peak memory 512252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867514344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2867514344
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.2634668564
Short name T382
Test name
Test status
Simulation time 87325686 ps
CPU time 1.92 seconds
Started Aug 28 10:23:31 PM UTC 24
Finished Aug 28 10:23:34 PM UTC 24
Peak memory 216624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634668564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2634668564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.1678817111
Short name T393
Test name
Test status
Simulation time 8569465159 ps
CPU time 24.91 seconds
Started Aug 28 10:23:27 PM UTC 24
Finished Aug 28 10:23:54 PM UTC 24
Peak memory 338388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678817111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1678817111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.2906374572
Short name T119
Test name
Test status
Simulation time 47394480579 ps
CPU time 269.26 seconds
Started Aug 28 10:23:32 PM UTC 24
Finished Aug 28 10:28:05 PM UTC 24
Peak memory 2071120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906374572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2906374572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.1000482225
Short name T411
Test name
Test status
Simulation time 4138931492 ps
CPU time 53.63 seconds
Started Aug 28 10:23:32 PM UTC 24
Finished Aug 28 10:24:27 PM UTC 24
Peak memory 227192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000482225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1000482225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1459902679
Short name T392
Test name
Test status
Simulation time 2802649532 ps
CPU time 7.12 seconds
Started Aug 28 10:23:45 PM UTC 24
Finished Aug 28 10:23:53 PM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1459902679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1459902679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.2125311151
Short name T390
Test name
Test status
Simulation time 543353868 ps
CPU time 1.09 seconds
Started Aug 28 10:23:44 PM UTC 24
Finished Aug 28 10:23:47 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125311
151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.2125311151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.3273044465
Short name T177
Test name
Test status
Simulation time 649713298 ps
CPU time 2.95 seconds
Started Aug 28 10:23:44 PM UTC 24
Finished Aug 28 10:23:48 PM UTC 24
Peak memory 228796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273044
465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.3273044465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.2902025464
Short name T398
Test name
Test status
Simulation time 795874748 ps
CPU time 5.22 seconds
Started Aug 28 10:23:51 PM UTC 24
Finished Aug 28 10:23:57 PM UTC 24
Peak memory 216308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902025
464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark
s_acq.2902025464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.664584751
Short name T394
Test name
Test status
Simulation time 370953790 ps
CPU time 1.7 seconds
Started Aug 28 10:23:51 PM UTC 24
Finished Aug 28 10:23:54 PM UTC 24
Peak memory 216572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6645847
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.664584751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.3701253503
Short name T391
Test name
Test status
Simulation time 617090640 ps
CPU time 6.01 seconds
Started Aug 28 10:23:44 PM UTC 24
Finished Aug 28 10:23:51 PM UTC 24
Peak memory 233484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370125
3503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.3701253503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.3003776028
Short name T643
Test name
Test status
Simulation time 18263640090 ps
CPU time 275.7 seconds
Started Aug 28 10:23:44 PM UTC 24
Finished Aug 28 10:28:24 PM UTC 24
Peak memory 4630932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3003776028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress
_wr.3003776028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.1655991685
Short name T403
Test name
Test status
Simulation time 5586639393 ps
CPU time 4.28 seconds
Started Aug 28 10:23:54 PM UTC 24
Finished Aug 28 10:24:00 PM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655991
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.1655991685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.196330188
Short name T404
Test name
Test status
Simulation time 2046821003 ps
CPU time 4.63 seconds
Started Aug 28 10:23:54 PM UTC 24
Finished Aug 28 10:24:00 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963301
88 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.196330188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_perf.2105747922
Short name T395
Test name
Test status
Simulation time 878242433 ps
CPU time 8.75 seconds
Started Aug 28 10:23:45 PM UTC 24
Finished Aug 28 10:23:54 PM UTC 24
Peak memory 233624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105747
922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.2105747922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.120617317
Short name T401
Test name
Test status
Simulation time 546834199 ps
CPU time 4.72 seconds
Started Aug 28 10:23:53 PM UTC 24
Finished Aug 28 10:23:59 PM UTC 24
Peak memory 216632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206173
17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.120617317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.891295268
Short name T396
Test name
Test status
Simulation time 1213613540 ps
CPU time 20.6 seconds
Started Aug 28 10:23:34 PM UTC 24
Finished Aug 28 10:23:56 PM UTC 24
Peak memory 233776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891295268 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.891295268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.4131423944
Short name T712
Test name
Test status
Simulation time 27708541783 ps
CPU time 339.91 seconds
Started Aug 28 10:23:45 PM UTC 24
Finished Aug 28 10:29:28 PM UTC 24
Peak memory 5134560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413142
3944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.4131423944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.2286634546
Short name T406
Test name
Test status
Simulation time 4054561340 ps
CPU time 34.63 seconds
Started Aug 28 10:23:36 PM UTC 24
Finished Aug 28 10:24:12 PM UTC 24
Peak memory 248016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286634546 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.2286634546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.3914335700
Short name T600
Test name
Test status
Simulation time 67897863769 ps
CPU time 254.23 seconds
Started Aug 28 10:23:35 PM UTC 24
Finished Aug 28 10:27:53 PM UTC 24
Peak memory 2910428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914335700 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.3914335700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.4197415926
Short name T389
Test name
Test status
Simulation time 218954066 ps
CPU time 1.8 seconds
Started Aug 28 10:23:43 PM UTC 24
Finished Aug 28 10:23:46 PM UTC 24
Peak memory 215228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197415926 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.4197415926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.3473767462
Short name T400
Test name
Test status
Simulation time 5106872124 ps
CPU time 12.7 seconds
Started Aug 28 10:23:44 PM UTC 24
Finished Aug 28 10:23:58 PM UTC 24
Peak memory 233576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473767
462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.3473767462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.2778482527
Short name T397
Test name
Test status
Simulation time 138052950 ps
CPU time 3.97 seconds
Started Aug 28 10:23:52 PM UTC 24
Finished Aug 28 10:23:57 PM UTC 24
Peak memory 216452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778482
527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.2778482527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_alert_test.1602314668
Short name T419
Test name
Test status
Simulation time 38687494 ps
CPU time 1 seconds
Started Aug 28 10:24:36 PM UTC 24
Finished Aug 28 10:24:37 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602314668 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1602314668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.1725906203
Short name T384
Test name
Test status
Simulation time 296963498 ps
CPU time 3.5 seconds
Started Aug 28 10:24:02 PM UTC 24
Finished Aug 28 10:24:07 PM UTC 24
Peak memory 226824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725906203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1725906203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.2359519592
Short name T407
Test name
Test status
Simulation time 302719329 ps
CPU time 18.65 seconds
Started Aug 28 10:23:59 PM UTC 24
Finished Aug 28 10:24:19 PM UTC 24
Peak memory 270408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359519592 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.2359519592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.1385954885
Short name T455
Test name
Test status
Simulation time 8041448430 ps
CPU time 74.05 seconds
Started Aug 28 10:24:00 PM UTC 24
Finished Aug 28 10:25:16 PM UTC 24
Peak memory 715220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385954885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1385954885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.4150258140
Short name T491
Test name
Test status
Simulation time 5023223702 ps
CPU time 159.1 seconds
Started Aug 28 10:23:58 PM UTC 24
Finished Aug 28 10:26:40 PM UTC 24
Peak memory 733324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150258140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4150258140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.3062480459
Short name T405
Test name
Test status
Simulation time 334834665 ps
CPU time 1.18 seconds
Started Aug 28 10:23:59 PM UTC 24
Finished Aug 28 10:24:01 PM UTC 24
Peak memory 215224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062480459 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.3062480459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.441659643
Short name T187
Test name
Test status
Simulation time 661516246 ps
CPU time 11.93 seconds
Started Aug 28 10:24:00 PM UTC 24
Finished Aug 28 10:24:13 PM UTC 24
Peak memory 245856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441659643 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.441659643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.4078723028
Short name T717
Test name
Test status
Simulation time 19678434953 ps
CPU time 330.07 seconds
Started Aug 28 10:23:58 PM UTC 24
Finished Aug 28 10:29:32 PM UTC 24
Peak memory 1554560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078723028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.4078723028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.794474348
Short name T284
Test name
Test status
Simulation time 406433846 ps
CPU time 7.35 seconds
Started Aug 28 10:24:29 PM UTC 24
Finished Aug 28 10:24:38 PM UTC 24
Peak memory 216644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794474348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.794474348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_override.4113559108
Short name T402
Test name
Test status
Simulation time 212711894 ps
CPU time 0.96 seconds
Started Aug 28 10:23:58 PM UTC 24
Finished Aug 28 10:24:00 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113559108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4113559108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_perf.886496784
Short name T351
Test name
Test status
Simulation time 387179722 ps
CPU time 7.49 seconds
Started Aug 28 10:24:00 PM UTC 24
Finished Aug 28 10:24:09 PM UTC 24
Peak memory 280876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886496784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.886496784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.4068747237
Short name T250
Test name
Test status
Simulation time 1595634352 ps
CPU time 31.53 seconds
Started Aug 28 10:24:00 PM UTC 24
Finished Aug 28 10:24:33 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068747237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.4068747237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3897346664
Short name T458
Test name
Test status
Simulation time 1809652236 ps
CPU time 80.97 seconds
Started Aug 28 10:23:57 PM UTC 24
Finished Aug 28 10:25:19 PM UTC 24
Peak memory 333984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897346664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3897346664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.1576066127
Short name T425
Test name
Test status
Simulation time 3151262747 ps
CPU time 41.78 seconds
Started Aug 28 10:24:01 PM UTC 24
Finished Aug 28 10:24:44 PM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576066127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1576066127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.2451272330
Short name T416
Test name
Test status
Simulation time 886205016 ps
CPU time 7.24 seconds
Started Aug 28 10:24:25 PM UTC 24
Finished Aug 28 10:24:33 PM UTC 24
Peak memory 226872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2451272330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2451272330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.4054857403
Short name T198
Test name
Test status
Simulation time 542401479 ps
CPU time 2.07 seconds
Started Aug 28 10:24:20 PM UTC 24
Finished Aug 28 10:24:23 PM UTC 24
Peak memory 216436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054857
403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.4054857403
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.63448725
Short name T178
Test name
Test status
Simulation time 1883455335 ps
CPU time 2.47 seconds
Started Aug 28 10:24:22 PM UTC 24
Finished Aug 28 10:24:26 PM UTC 24
Peak memory 216592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6344872
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.63448725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.2695080103
Short name T415
Test name
Test status
Simulation time 525438982 ps
CPU time 2.07 seconds
Started Aug 28 10:24:29 PM UTC 24
Finished Aug 28 10:24:32 PM UTC 24
Peak memory 216324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695080
103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_tx.2695080103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.2529110614
Short name T410
Test name
Test status
Simulation time 4407060727 ps
CPU time 9.16 seconds
Started Aug 28 10:24:13 PM UTC 24
Finished Aug 28 10:24:23 PM UTC 24
Peak memory 233632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252911
0614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.2529110614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.3181839502
Short name T449
Test name
Test status
Simulation time 21557778942 ps
CPU time 53.64 seconds
Started Aug 28 10:24:14 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 1069208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3181839502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.3181839502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.2441704056
Short name T420
Test name
Test status
Simulation time 1680866796 ps
CPU time 3.48 seconds
Started Aug 28 10:24:33 PM UTC 24
Finished Aug 28 10:24:38 PM UTC 24
Peak memory 226936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441704
056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.2441704056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.1935614931
Short name T422
Test name
Test status
Simulation time 864873614 ps
CPU time 3.75 seconds
Started Aug 28 10:24:34 PM UTC 24
Finished Aug 28 10:24:39 PM UTC 24
Peak memory 216532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935614
931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.1935614931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.21027091
Short name T179
Test name
Test status
Simulation time 140942049 ps
CPU time 2.31 seconds
Started Aug 28 10:24:34 PM UTC 24
Finished Aug 28 10:24:38 PM UTC 24
Peak memory 233492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102709
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.21027091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_perf.3398076141
Short name T376
Test name
Test status
Simulation time 3756468597 ps
CPU time 9.09 seconds
Started Aug 28 10:24:23 PM UTC 24
Finished Aug 28 10:24:34 PM UTC 24
Peak memory 233220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398076
141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.3398076141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.2663857712
Short name T421
Test name
Test status
Simulation time 1145064803 ps
CPU time 3.9 seconds
Started Aug 28 10:24:33 PM UTC 24
Finished Aug 28 10:24:38 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663857
712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.2663857712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.3113200755
Short name T414
Test name
Test status
Simulation time 3078692985 ps
CPU time 16.06 seconds
Started Aug 28 10:24:11 PM UTC 24
Finished Aug 28 10:24:28 PM UTC 24
Peak memory 234004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113200755 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.3113200755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.3781243249
Short name T1125
Test name
Test status
Simulation time 40457389453 ps
CPU time 778.72 seconds
Started Aug 28 10:24:25 PM UTC 24
Finished Aug 28 10:37:31 PM UTC 24
Peak memory 7082024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378124
3249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.3781243249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1278098894
Short name T438
Test name
Test status
Simulation time 999117561 ps
CPU time 50.6 seconds
Started Aug 28 10:24:11 PM UTC 24
Finished Aug 28 10:25:03 PM UTC 24
Peak memory 226804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278098894 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.1278098894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.2187279276
Short name T423
Test name
Test status
Simulation time 16633661251 ps
CPU time 31.91 seconds
Started Aug 28 10:24:11 PM UTC 24
Finished Aug 28 10:24:44 PM UTC 24
Peak memory 216908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187279276 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.2187279276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.2393964897
Short name T432
Test name
Test status
Simulation time 4982104802 ps
CPU time 41.96 seconds
Started Aug 28 10:24:13 PM UTC 24
Finished Aug 28 10:24:57 PM UTC 24
Peak memory 397528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393964897 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.2393964897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.3520523609
Short name T413
Test name
Test status
Simulation time 1188961636 ps
CPU time 8.66 seconds
Started Aug 28 10:24:18 PM UTC 24
Finished Aug 28 10:24:28 PM UTC 24
Peak memory 230924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520523
609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.3520523609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.1970404617
Short name T418
Test name
Test status
Simulation time 70683682 ps
CPU time 2.75 seconds
Started Aug 28 10:24:31 PM UTC 24
Finished Aug 28 10:24:35 PM UTC 24
Peak memory 216584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970404
617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.1970404617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_alert_test.4065093594
Short name T443
Test name
Test status
Simulation time 18142388 ps
CPU time 0.98 seconds
Started Aug 28 10:25:05 PM UTC 24
Finished Aug 28 10:25:07 PM UTC 24
Peak memory 215400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065093594 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.4065093594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.1853229966
Short name T427
Test name
Test status
Simulation time 253131775 ps
CPU time 3.2 seconds
Started Aug 28 10:24:42 PM UTC 24
Finished Aug 28 10:24:46 PM UTC 24
Peak memory 228884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853229966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1853229966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.3299754411
Short name T307
Test name
Test status
Simulation time 412107688 ps
CPU time 5.43 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:24:45 PM UTC 24
Peak memory 260224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299754411 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.3299754411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.564885253
Short name T512
Test name
Test status
Simulation time 9147872293 ps
CPU time 94.28 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:26:15 PM UTC 24
Peak memory 581796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564885253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.564885253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.1467977634
Short name T474
Test name
Test status
Simulation time 3389057520 ps
CPU time 58.57 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:25:39 PM UTC 24
Peak memory 647436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467977634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1467977634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.1702189957
Short name T428
Test name
Test status
Simulation time 3258623329 ps
CPU time 6.43 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:24:47 PM UTC 24
Peak memory 245988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702189957 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.1702189957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.1288353468
Short name T488
Test name
Test status
Simulation time 6362447961 ps
CPU time 80.06 seconds
Started Aug 28 10:24:38 PM UTC 24
Finished Aug 28 10:26:00 PM UTC 24
Peak memory 1012168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288353468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1288353468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.2397154273
Short name T273
Test name
Test status
Simulation time 2568395627 ps
CPU time 29.79 seconds
Started Aug 28 10:24:59 PM UTC 24
Finished Aug 28 10:25:30 PM UTC 24
Peak memory 216764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397154273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2397154273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_mode_toggle.223404806
Short name T33
Test name
Test status
Simulation time 1031567825 ps
CPU time 3.87 seconds
Started Aug 28 10:24:59 PM UTC 24
Finished Aug 28 10:25:04 PM UTC 24
Peak memory 243852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223404806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.223404806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_override.4033784064
Short name T151
Test name
Test status
Simulation time 29798528 ps
CPU time 1.09 seconds
Started Aug 28 10:24:36 PM UTC 24
Finished Aug 28 10:24:38 PM UTC 24
Peak memory 215232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033784064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.4033784064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_perf.1854692699
Short name T430
Test name
Test status
Simulation time 3279802118 ps
CPU time 12.15 seconds
Started Aug 28 10:24:39 PM UTC 24
Finished Aug 28 10:24:52 PM UTC 24
Peak memory 325784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854692699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1854692699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.3411661112
Short name T436
Test name
Test status
Simulation time 400868454 ps
CPU time 19.24 seconds
Started Aug 28 10:24:40 PM UTC 24
Finished Aug 28 10:25:01 PM UTC 24
Peak memory 216492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411661112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.3411661112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.4219782740
Short name T439
Test name
Test status
Simulation time 1652791031 ps
CPU time 27.8 seconds
Started Aug 28 10:24:36 PM UTC 24
Finished Aug 28 10:25:05 PM UTC 24
Peak memory 358428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219782740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4219782740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.382135654
Short name T429
Test name
Test status
Simulation time 1860168158 ps
CPU time 9.63 seconds
Started Aug 28 10:24:40 PM UTC 24
Finished Aug 28 10:24:51 PM UTC 24
Peak memory 227116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382135654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.382135654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.2307973195
Short name T440
Test name
Test status
Simulation time 1753873341 ps
CPU time 9.2 seconds
Started Aug 28 10:24:54 PM UTC 24
Finished Aug 28 10:25:05 PM UTC 24
Peak memory 230860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2307973195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2307973195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.652207265
Short name T431
Test name
Test status
Simulation time 522018419 ps
CPU time 1.81 seconds
Started Aug 28 10:24:51 PM UTC 24
Finished Aug 28 10:24:54 PM UTC 24
Peak memory 226424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6522072
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.652207265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.2638196706
Short name T180
Test name
Test status
Simulation time 772787590 ps
CPU time 2.84 seconds
Started Aug 28 10:24:52 PM UTC 24
Finished Aug 28 10:24:56 PM UTC 24
Peak memory 216840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638196
706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.2638196706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.2833102537
Short name T442
Test name
Test status
Simulation time 602021007 ps
CPU time 3.04 seconds
Started Aug 28 10:25:02 PM UTC 24
Finished Aug 28 10:25:06 PM UTC 24
Peak memory 216376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833102
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermark
s_acq.2833102537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.1942754967
Short name T441
Test name
Test status
Simulation time 109313692 ps
CPU time 1.89 seconds
Started Aug 28 10:25:02 PM UTC 24
Finished Aug 28 10:25:05 PM UTC 24
Peak memory 216452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942754
967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_tx.1942754967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_hrst.662455262
Short name T201
Test name
Test status
Simulation time 1200557997 ps
CPU time 3.83 seconds
Started Aug 28 10:24:56 PM UTC 24
Finished Aug 28 10:25:01 PM UTC 24
Peak memory 227020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6624552
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_hrst.662455262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.2891069260
Short name T433
Test name
Test status
Simulation time 9704132840 ps
CPU time 8.5 seconds
Started Aug 28 10:24:47 PM UTC 24
Finished Aug 28 10:24:57 PM UTC 24
Peak memory 233744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289106
9260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.2891069260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.804236339
Short name T230
Test name
Test status
Simulation time 18817861572 ps
CPU time 49.19 seconds
Started Aug 28 10:24:48 PM UTC 24
Finished Aug 28 10:25:39 PM UTC 24
Peak memory 840088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=804236339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.804236339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.2419479599
Short name T447
Test name
Test status
Simulation time 533224328 ps
CPU time 3.7 seconds
Started Aug 28 10:25:04 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 226892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419479
599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.2419479599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.346066349
Short name T181
Test name
Test status
Simulation time 136744736 ps
CPU time 2.59 seconds
Started Aug 28 10:25:04 PM UTC 24
Finished Aug 28 10:25:08 PM UTC 24
Peak memory 233556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460663
49 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.346066349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_perf.2609768868
Short name T285
Test name
Test status
Simulation time 1066029969 ps
CPU time 8.21 seconds
Started Aug 28 10:24:53 PM UTC 24
Finished Aug 28 10:25:02 PM UTC 24
Peak memory 230892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609768
868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.2609768868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.2079756704
Short name T446
Test name
Test status
Simulation time 1897753042 ps
CPU time 4.68 seconds
Started Aug 28 10:25:03 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 216368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079756
704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.2079756704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.1490167573
Short name T450
Test name
Test status
Simulation time 4766509571 ps
CPU time 23.31 seconds
Started Aug 28 10:24:45 PM UTC 24
Finished Aug 28 10:25:11 PM UTC 24
Peak memory 227008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490167573 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.1490167573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.2182900478
Short name T550
Test name
Test status
Simulation time 30086922196 ps
CPU time 122.75 seconds
Started Aug 28 10:24:53 PM UTC 24
Finished Aug 28 10:26:58 PM UTC 24
Peak memory 1620180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218290
0478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.2182900478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.3487446101
Short name T461
Test name
Test status
Simulation time 1558835364 ps
CPU time 34.23 seconds
Started Aug 28 10:24:46 PM UTC 24
Finished Aug 28 10:25:22 PM UTC 24
Peak memory 243984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487446101 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.3487446101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.1620638500
Short name T448
Test name
Test status
Simulation time 19546701241 ps
CPU time 21.98 seconds
Started Aug 28 10:24:46 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 216628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620638500 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.1620638500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.709466939
Short name T434
Test name
Test status
Simulation time 1639465064 ps
CPU time 10.08 seconds
Started Aug 28 10:24:46 PM UTC 24
Finished Aug 28 10:24:57 PM UTC 24
Peak memory 360724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709466939 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.709466939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.1155622668
Short name T435
Test name
Test status
Simulation time 2027997580 ps
CPU time 11.92 seconds
Started Aug 28 10:24:48 PM UTC 24
Finished Aug 28 10:25:01 PM UTC 24
Peak memory 227060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155622
668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.1155622668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.3796289512
Short name T445
Test name
Test status
Simulation time 191427599 ps
CPU time 5.73 seconds
Started Aug 28 10:25:02 PM UTC 24
Finished Aug 28 10:25:09 PM UTC 24
Peak memory 216516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796289
512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3796289512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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