KEYMGR Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	22.850s	3.652ms	48	50	96.00
V1	random	keymgr_random	1.006m	2.707ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.360s	48.589us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.680s	383.993us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.410s	1.281ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.980s	640.578us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.420s	161.399us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.680s	383.993us	20	20	100.00
		keymgr_csr_aliasing	8.980s	640.578us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	cfgen_during_op	keymgr_cfg_regwen	2.133m	4.959ms	50	50	100.00
V2	sideload	keymgr_sideload	46.800s	8.026ms	50	50	100.00
		keymgr_sideload_kmac	58.440s	5.584ms	50	50	100.00
		keymgr_sideload_aes	32.950s	5.331ms	50	50	100.00
		keymgr_sideload_otbn	1.152m	6.886ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	28.030s	5.525ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.000s	187.183us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.871m	14.659ms	43	50	86.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.540m	8.711ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.409m	8.843ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	25.870s	2.698ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.472m	19.400ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.040s	15.752us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.050s	34.952us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.680s	153.431us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.680s	153.431us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.360s	48.589us	5	5	100.00
		keymgr_csr_rw	1.680s	383.993us	20	20	100.00
		keymgr_csr_aliasing	8.980s	640.578us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	259.811us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.360s	48.589us	5	5	100.00
		keymgr_csr_rw	1.680s	383.993us	20	20	100.00
		keymgr_csr_aliasing	8.980s	640.578us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	259.811us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
		keymgr_tl_intg_err	1.134m	4.226ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.240s	1.643ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.240s	1.643ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.240s	1.643ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.240s	1.643ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.770s	399.214us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	1.134m	4.226ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.240s	1.643ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.133m	4.959ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.006m	2.707ms	50	50	100.00
		keymgr_csr_rw	1.680s	383.993us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.006m	2.707ms	50	50	100.00
		keymgr_csr_rw	1.680s	383.993us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.006m	2.707ms	50	50	100.00
		keymgr_csr_rw	1.680s	383.993us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.000s	187.183us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.409m	8.843ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.409m	8.843ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.006m	2.707ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	12.210s	959.802us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	50.380s	2.693ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.000s	187.183us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	50.380s	2.693ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	50.380s	2.693ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	50.380s	2.693ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	29.800s	2.100ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	50.380s	2.693ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.040s	1.030ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1073	1110	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.07	98.10	98.63	100.00	99.11	98.41	91.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 1.keymgr_stress_all_with_rand_reset.112861909927239288684440879083725132784736254592154136399988348043059342304345
    Line 431, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 333780362 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 333780362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.15858262131881003199669628240360141224854198582408183181514032733046407226069
    Line 270, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 453040057 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 453040057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 7 failures:

Test keymgr_kmac_rsp_err has 7 failures.

2.keymgr_kmac_rsp_err.79571972456996289909903561655011341395619657663259136593418969283905943811874
Line 372, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  80161421 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (2928272438535593527928642147103335445525236706616349332620863041291900897467694902529612197785004987824474070413766971971669302446571346528320817210156301639327450066802505078166933758886974282255226722473869060326604128638445241067410135390321289747748134542315545060340012389805103218978393215297600240048529668298617868265658285550003971945645152747892179544962864427290379255090739179804046852571534346793873050076572536 [0x69d506af5ba22b53e6f1d9e64802f2202ba40c2d781804e87f2fc1022f6267933a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 2928272438535593527928642147103335445525236706616349332620863041291900897467694902529612197785004987824474070413766971971669302446571346528320817210156301639327450066802505078166933758886974282255226722473869060326604128638445241067410135390321289747748134542315545060340012389805103218978393215297600240048529668298617868265658285550003971945645152747892179544962864427290379255090739179804046852571534346793873050076572536 [0x69d506af5ba22b53e6f1d9e64802f2202ba40c2d781804e87f2fc1022f6267933a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

3.keymgr_kmac_rsp_err.102145598966891889666434054754936869792770737094376949279632182528945358418096
Line 328, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  47676717 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (4920690431960731758911953154769012245018452294984201130377170903331913137402314799967759819005075602650254604671765003358145020302859189697817779486681258241999054169263175435406863251814800496606334801772031358479519752198813139055240817258802019330918786547004366317892047224074136794292220541185941503004270853731239657345295672230026656338765996072685330632787167886883908886118713281180536414345777103774133385324449884 [0xb1d751bf06c05c212927715fa565d08d1714644287e8d788bdbe81834a11d5cb3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f919746e09519510a975f7225ab86590df8805eb52b3f70d6f2e139862b8f57f387a203e7414551d50fab2e87fd72ace819475c9ef95d83b3e221dad7985fa4feadbcaf6f7c8f4c76df34aba3061ccc8615a64063ae5378a6a5c66dfa428442ea5b7bcfefb29c4c4cd53b8455a96e4d05c] vs 4920690431960731758911953154769012245018452294984201130377170903331913137402314799967759819005075602650254604671765003358145020302859189697817779486681258241999054169263175435406863251814800496606334801772031358479519752198813139055240817258802019330918786547004366317892047224074136794292220541185941503004270853731239657345295672230026656338765996072685330632787167886883908886118713281180536414345777103774133385324449884 [0xb1d751bf06c05c212927715fa565d08d1714644287e8d788bdbe81834a11d5cb3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f919746e09519510a975f7225ab86590df8805eb52b3f70d6f2e139862b8f57f387a203e7414551d50fab2e87fd72ace819475c9ef95d83b3e221dad7985fa4feadbcaf6f7c8f4c76df34aba3061ccc8615a64063ae5378a6a5c66dfa428442ea5b7bcfefb29c4c4cd53b8455a96e4d05c]) cdi_type: Attestation
  
   DiversificationKey act: 0x5a64063ae5378a6a5c66dfa428442ea5b7bcfefb29c4c4cd53b8455a96e4d05c, exp: 0x5a64063ae5378a6a5c66dfa428442ea5b7bcfefb29c4c4cd53b8455a96e4d05c
   RomDigest act: 0x9475c9ef95d83b3e221dad7985fa4feadbcaf6f7c8f4c76df34aba3061ccc861, exp: 0x9475c9ef95d83b3e221dad7985fa4feadbcaf6f7c8f4c76df34aba3061ccc861
   HealthMeasurement act: 0x7a203e7414551d50fab2e87fd72ace81, exp: 0x7a203e7414551d50fab2e87fd72ace81

... and 5 more failures.

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 5 failures:
- Test keymgr_stress_all_with_rand_reset has 5 failures.
  - 4.keymgr_stress_all_with_rand_reset.112971929413935435710552690361839254982536946145961759131322710155678399963441
    Line 1639, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1687111333 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3021757171 [0xb41c5af3] vs 3021757171 [0xb41c5af3])
  UVM_INFO @ 1687111333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.keymgr_stress_all_with_rand_reset.39354131014735568225950969209926443448628706581198896099008931147203985823100
    Line 1076, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 308899560 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3497114240 [0xd071ba80] vs 3497114240 [0xd071ba80])
  UVM_INFO @ 308899560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_stress_all has 1 failures.

5.keymgr_stress_all.63426804624622595890978879430535113898179204523448985752604635243244758783674
Line 1188, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log

  UVM_ERROR @  97549899 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  97549899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 2 failures.

11.keymgr_smoke.18169338436272120449545924710635148969754931212356489286260708567760059319538
Line 263, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_smoke/latest/run.log

  UVM_ERROR @   5168221 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   5168221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.keymgr_smoke.102666263999122487399074880442564744924074922937029389185154363131750188698117
Line 339, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_smoke/latest/run.log

  UVM_ERROR @  91136056 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  91136056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

39.keymgr_sideload_otbn.13651404439649222809314973707124074621796608956316156787022134123463219499999
Line 260, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @   2689568 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2689568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 5.keymgr_stress_all_with_rand_reset.35162814579295561624047667266046167186436851163896981317623678089074851475890
    Line 591, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  38860537 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2427577966 [0x90b1e66e] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
  UVM_INFO @  38860537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 34.keymgr_lc_disable.23393865288412320781430447173860285265611534034282229756305331580179871790865
    Line 296, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  63383306 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1988061622 [0x767f69b6] vs 3929713566 [0xea3aab9e]) reg name: keymgr_reg_block.sw_share0_output_5
  UVM_INFO @  63383306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```