2723ca659d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 1.173m | 8.452ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.065m | 2.718ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.130s | 16.974us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 11.700s | 505.343us | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.810s | 5.073ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.220s | 61.610us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.810s | 5.073ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.540m | 4.656ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 56.690s | 21.508ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.283m | 4.181ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 20.880s | 1.128ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.339m | 7.504ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 27.400s | 955.431us | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 24.000s | 484.460us | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 1.779m | 8.926ms | 46 | 50 | 92.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 49.030s | 2.259ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.093m | 9.446ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 14.160s | 960.163us | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 9.338m | 19.261ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.900s | 14.878us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.080s | 29.727us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.460s | 887.027us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.460s | 887.027us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.130s | 16.974us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.810s | 5.073ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.960s | 2.178ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.130s | 16.974us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.810s | 5.073ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.960s | 2.178ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 733 | 740 | 99.05 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 50.290s | 5.261ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 19.460s | 2.242ms | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 19.460s | 2.242ms | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 19.460s | 2.242ms | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 19.460s | 2.242ms | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 16.220s | 497.598us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 50.290s | 5.261ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 19.460s | 2.242ms | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.540m | 4.656ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.065m | 2.718ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.065m | 2.718ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.065m | 2.718ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 136.441us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 24.000s | 484.460us | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.093m | 9.446ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.093m | 9.446ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.065m | 2.718ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 27.310s | 7.971ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 1.119m | 9.985ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 24.000s | 484.460us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 1.119m | 9.985ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 1.119m | 9.985ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 1.119m | 9.985ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 9.031m | 17.385ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 1.119m | 9.985ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 22.880s | 1.524ms | 25 | 50 | 50.00 |
V3 | TOTAL | 25 | 50 | 50.00 | |||
TOTAL | 1078 | 1110 | 97.12 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.81 | 99.07 | 98.03 | 98.61 | 100.00 | 99.11 | 98.41 | 91.49 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 18 failures:
0.keymgr_stress_all_with_rand_reset.95509248917532194515291435784533763015920562784312106158743755343459516169946
Line 326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 431672010 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 431672010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_stress_all_with_rand_reset.17869585792381286639962753192863119630101139627824421883686054722689018583908
Line 327, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111787657 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10005 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111787657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * [])` has 5 failures:
1.keymgr_stress_all_with_rand_reset.93783546286625810684530188273504883281354600968394997873741463523755999240666
Line 1793, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3108694891 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (4034045817 [0xf072a779] vs 4034045817 [0xf072a779])
UVM_INFO @ 3108694891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.keymgr_stress_all_with_rand_reset.83164145619169990202385114269243538903006340700721582081661629676433696449427
Line 1997, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1902798101 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (4145235604 [0xf7134694] vs 4145235604 [0xf7134694])
UVM_INFO @ 1902798101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation
has 3 failures:
11.keymgr_kmac_rsp_err.25850613370211665963035031988255132167648240803134267504589995324811031827595
Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 279423504 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (1546733972761274158979308204690049165405400564820544903273055655751140655718507006115949933811156480792623583820943280368275529724878732617253609685045438737609768596047717225428649577076825206903817070329809649993648005775828860567898335678928946003548405650734926228556714358236445736997095317166798774244208057126647979746796169248605767540890865731204087724891532116062128014357441211510149197487188308146836582340855186 [0x37e6b9cd8d4a020b5fb2ebf459f31406f617a77f16666aef9f494f93342ebcee3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9a3b9cb84cdacef93a0118e9906f3ab100b2458f93c210049fb452729a70cb8ad8b390566588dbede1541cc90b07650f80a2950d9aef1b34741396d624d0df828130a9f2eb2a7882d3f73bb8fab9e10de3a9c56c65f9e4947a88b1ee797134ce7e300804db66f4aca0cf3476beb458592] vs 1546733972761274158979308204690049165405400564820544903273055655751140655718507006115949933811156480792623583820943280368275529724878732617253609685045438737609768596047717225428649577076825206903817070329809649993648005775828860567898335678928946003548405650734926228556714358236445736997095317166798774244208057126647979746796169248605767540890865731204087724891532116062128014357441211510149197487188308146836582340855186 [0x37e6b9cd8d4a020b5fb2ebf459f31406f617a77f16666aef9f494f93342ebcee3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9a3b9cb84cdacef93a0118e9906f3ab100b2458f93c210049fb452729a70cb8ad8b390566588dbede1541cc90b07650f80a2950d9aef1b34741396d624d0df828130a9f2eb2a7882d3f73bb8fab9e10de3a9c56c65f9e4947a88b1ee797134ce7e300804db66f4aca0cf3476beb458592]) cdi_type: Attestation
DiversificationKey act: 0x3a9c56c65f9e4947a88b1ee797134ce7e300804db66f4aca0cf3476beb458592, exp: 0x3a9c56c65f9e4947a88b1ee797134ce7e300804db66f4aca0cf3476beb458592
RomDigest act: 0xa2950d9aef1b34741396d624d0df828130a9f2eb2a7882d3f73bb8fab9e10de, exp: 0xa2950d9aef1b34741396d624d0df828130a9f2eb2a7882d3f73bb8fab9e10de
HealthMeasurement act: 0x8b390566588dbede1541cc90b07650f8, exp: 0x8b390566588dbede1541cc90b07650f8
12.keymgr_kmac_rsp_err.96774249223360338040253622468310259048557581799259851784324270266019611746635
Line 438, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 84455340 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (3662323082262131149077286382423975416679241160686554133979585665267604073944537708166702560048344038599840793589767892539251784478938540019442943746189089679169081629529627760443828127633685432553550986574333027253639664079671927895162537387858442114920789992881362365126582113778017725422034801266679708446357601962288540143191816592398097873668895347234428958828779412697922739707066357804217460566476359912259992110285184 [0x845ca01fe5efddef7029c13b6824ad769dd16bf400000000e15e809ddb30c1473a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9521048a54d6a032366543adb78673f7328fa0cee67e841bf54a514359399add219f300cc7816af473355989fd76f375b0a8b82d27334601c83c3ffa2b3c83b609aa983b71c40d624341e80569d7d5b64101cc01ad861e8a491c6d2032eab3f6b96901572be4010b7ae131595e944c180] vs 3662323082262131149077286382423975416679241160686554133979585665267604073944537708166702560048344038599840793589767892539251784478938540019442943746189089679169081629529627760443828127633685432553550986574333027253639664079671927895162537387858442114920789992881362365126582113778017725422034801266679708446357601962288540143191816592398097873668895347234428958828779412697922739707066357804217460566476359912259992110285184 [0x845ca01fe5efddef7029c13b6824ad769dd16bf400000000e15e809ddb30c1473a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9521048a54d6a032366543adb78673f7328fa0cee67e841bf54a514359399add219f300cc7816af473355989fd76f375b0a8b82d27334601c83c3ffa2b3c83b609aa983b71c40d624341e80569d7d5b64101cc01ad861e8a491c6d2032eab3f6b96901572be4010b7ae131595e944c180]) cdi_type: Attestation
DiversificationKey act: 0x101cc01ad861e8a491c6d2032eab3f6b96901572be4010b7ae131595e944c180, exp: 0x101cc01ad861e8a491c6d2032eab3f6b96901572be4010b7ae131595e944c180
RomDigest act: 0xa8b82d27334601c83c3ffa2b3c83b609aa983b71c40d624341e80569d7d5b64, exp: 0xa8b82d27334601c83c3ffa2b3c83b609aa983b71c40d624341e80569d7d5b64
HealthMeasurement act: 0x19f300cc7816af473355989fd76f375b, exp: 0x19f300cc7816af473355989fd76f375b
... and 1 more failures.
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:
Test keymgr_stress_all_with_rand_reset has 1 failures.
2.keymgr_stress_all_with_rand_reset.41775438589414311291119719459193995181248803653356934431955357589972113356717
Line 1151, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 260823574 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2316783489 [0x8a174f81] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
UVM_INFO @ 260823574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
38.keymgr_stress_all.49887265219026966168245405344829643461461877518647555109100419962904934998951
Line 395, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log
UVM_ERROR @ 43002244 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2569183421 [0x9922a0bd] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_7
UVM_INFO @ 43002244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
3.keymgr_kmac_rsp_err.26885002913259100861507544972371455149481649504567075431686298905494989095272
Line 592, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 44167490 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 44167490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
9.keymgr_stress_all_with_rand_reset.83073075386248919427348065778718580167315968706797552107559923018861504556154
Line 446, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 221416935 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 221416935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received!
has 1 failures:
29.keymgr_sync_async_fault_cross.106238568025072571217516064109723537496964141872499183765932160912404066582700
Line 346, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 483070769 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 483070769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:671) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*])
has 1 failures:
39.keymgr_stress_all.104524912111104193441296978853500826353969595721048908817919558004080894205497
Line 355, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log
UVM_ERROR @ 39397086 ps: (keymgr_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
UVM_INFO @ 39397086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---