KEYMGR Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.360s	1.351ms	50	50	100.00
V1	random	keymgr_random	57.460s	2.173ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.500s	59.231us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.610s	30.264us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.200s	1.748ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.910s	715.632us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.320s	276.494us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.610s	30.264us	20	20	100.00
		keymgr_csr_aliasing	9.910s	715.632us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.834m	16.062ms	50	50	100.00
V2	sideload	keymgr_sideload	46.420s	8.840ms	50	50	100.00
		keymgr_sideload_kmac	1.024m	7.349ms	49	50	98.00
		keymgr_sideload_aes	1.173m	17.487ms	50	50	100.00
		keymgr_sideload_otbn	43.300s	6.594ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	44.770s	2.609ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.400s	1.956ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	26.660s	2.216ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.114m	7.012ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	46.230s	6.900ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.830s	1.232ms	50	50	100.00
V2	stress_all	keymgr_stress_all	11.260m	68.852ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.900s	9.308us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.050s	20.057us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.850s	593.834us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.850s	593.834us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.500s	59.231us	5	5	100.00
		keymgr_csr_rw	1.610s	30.264us	20	20	100.00
		keymgr_csr_aliasing	9.910s	715.632us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	91.295us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.500s	59.231us	5	5	100.00
		keymgr_csr_rw	1.610s	30.264us	20	20	100.00
		keymgr_csr_aliasing	9.910s	715.632us	5	5	100.00
		keymgr_same_csr_outstanding	4.050s	91.295us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
		keymgr_tl_intg_err	10.180s	269.574us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.750s	443.308us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.750s	443.308us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.750s	443.308us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.750s	443.308us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.840s	437.708us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.180s	269.574us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.750s	443.308us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.834m	16.062ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	57.460s	2.173ms	50	50	100.00
		keymgr_csr_rw	1.610s	30.264us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	57.460s	2.173ms	50	50	100.00
		keymgr_csr_rw	1.610s	30.264us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	57.460s	2.173ms	50	50	100.00
		keymgr_csr_rw	1.610s	30.264us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.400s	1.956ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	46.230s	6.900ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	46.230s	6.900ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	57.460s	2.173ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.600s	881.387us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	40.100s	10.188ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.400s	1.956ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	40.100s	10.188ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	40.100s	10.188ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	40.100s	10.188ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.540s	1.044ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	40.100s	10.188ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.620s	5.517ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.03	98.15	98.26	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 0.keymgr_stress_all_with_rand_reset.2553449502960152291547301442118907394655659630711499622021827353857614584999
    Line 657, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202342591 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 202342591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.24392721100578791699904319879034080052854251323892935326193304611948218948144
    Line 296, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 216579257 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 216579257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 18.keymgr_lc_disable.86067324455659400804237096328969878035339307653575661059068271194736933349539
    Line 351, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/18.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  25083773 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @  25083773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

21.keymgr_stress_all.94582927184575308476492685182974497816965509468435513657584938995493402543267
Line 425, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log

  UVM_ERROR @  79198993 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2374220788482810260261486914513732866714227466420572943831836543961651591059739482770041612669077229101653570876953582227029078553968844089795719669725336 [0x2d54f310c6cf0495b7a74699ab563cb9ef0d9b22d27514c52c2bf8a54cc67b382b3d8aba9b8e9a39593895f4e7bfea061a5a443f0f0d42b09014ef5f98f3b898] vs 2374220788482810260261486914513732866714227466420572943831836543961651591059739482770041612669077229101653570876953582227029078553968844089795719669725336 [0x2d54f310c6cf0495b7a74699ab563cb9ef0d9b22d27514c52c2bf8a54cc67b382b3d8aba9b8e9a39593895f4e7bfea061a5a443f0f0d42b09014ef5f98f3b898]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @  79198993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 37.keymgr_custom_cm.115682409498684122219708535660361993627229634635637782761062537569511640118118
    Line 337, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10188395361 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10188395361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_sideload_kmac has 1 failures.
  - 45.keymgr_sideload_kmac.38621744457665127028374104106800626983319851932877373108370055731228418178883
    Line 286, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest/run.log
```
  UVM_ERROR @  15322520 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  15322520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```