KEYMGR Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.169m	7.413ms	50	50	100.00
V1	random	keymgr_random	1.121m	3.829ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.630s	126.630us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.550s	28.290us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.110s	676.926us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.500s	1.559ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.800s	138.505us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.550s	28.290us	20	20	100.00
		keymgr_csr_aliasing	7.500s	1.559ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	2.288m	22.452ms	50	50	100.00
V2	sideload	keymgr_sideload	54.990s	7.244ms	50	50	100.00
		keymgr_sideload_kmac	1.310m	4.497ms	50	50	100.00
		keymgr_sideload_aes	35.610s	910.524us	50	50	100.00
		keymgr_sideload_otbn	1.046m	10.401ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	35.140s	4.715ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	19.770s	2.229ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.280s	1.000ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.505m	4.859ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.488m	9.933ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.600s	614.643us	50	50	100.00
V2	stress_all	keymgr_stress_all	11.081m	21.262ms	47	50	94.00
V2	intr_test	keymgr_intr_test	1.040s	25.000us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.220s	419.596us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.290s	273.319us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.290s	273.319us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.630s	126.630us	5	5	100.00
		keymgr_csr_rw	1.550s	28.290us	20	20	100.00
		keymgr_csr_aliasing	7.500s	1.559ms	5	5	100.00
		keymgr_same_csr_outstanding	4.860s	220.183us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.630s	126.630us	5	5	100.00
		keymgr_csr_rw	1.550s	28.290us	20	20	100.00
		keymgr_csr_aliasing	7.500s	1.559ms	5	5	100.00
		keymgr_same_csr_outstanding	4.860s	220.183us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
		keymgr_tl_intg_err	8.290s	733.773us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.630s	315.905us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.630s	315.905us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.630s	315.905us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.630s	315.905us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.390s	1.503ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.290s	733.773us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.630s	315.905us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.288m	22.452ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.121m	3.829ms	49	50	98.00
		keymgr_csr_rw	1.550s	28.290us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.121m	3.829ms	49	50	98.00
		keymgr_csr_rw	1.550s	28.290us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.121m	3.829ms	49	50	98.00
		keymgr_csr_rw	1.550s	28.290us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	19.770s	2.229ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.488m	9.933ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.488m	9.933ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.121m	3.829ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.430s	1.557ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.330s	1.074ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	19.770s	2.229ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.330s	1.074ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.330s	1.074ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.330s	1.074ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.020s	1.137ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.330s	1.074ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.330s	2.607ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1086	1110	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	15	93.75
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.03	97.99	98.57	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 0.keymgr_stress_all_with_rand_reset.98018724464864718833206901874070937156062145981585789830639544402061934274720
    Line 786, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 547043902 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 547043902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.23548610954882154044061556982547705355041062677516768479099311316106127391109
    Line 610, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 417648796 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 417648796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_stress_all has 3 failures.

2.keymgr_stress_all.79637434586102252138068709409524671546952682392114619783653876042569465960792
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log

  UVM_ERROR @  38415536 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  38415536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.keymgr_stress_all.62532572529026882297897398215267497755499534185248371801502739199503401349709
Line 2865, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 431949499 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 431949499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_random has 1 failures.

44.keymgr_random.73489935120525727168789193164093201217407227198082743554384172082988615513417
Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_random/latest/run.log

  UVM_ERROR @   7590434 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   7590434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_if.sv:380) [keymgr_if] timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 47.keymgr_custom_cm.21470376851648457874628511444346202995467020407150988956304122576540345870477
    Line 323, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 1653632065 ps: (keymgr_if.sv:380) [keymgr_if] timeout occurred!
  UVM_INFO @ 1653632065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```