KEYMGR Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.010s	1.358ms	50	50	100.00
V1	random	keymgr_random	40.480s	3.964ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.590s	260.744us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.660s	134.797us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.330s	3.580ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	17.870s	1.028ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.840s	49.914us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.660s	134.797us	20	20	100.00
		keymgr_csr_aliasing	17.870s	1.028ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.899m	8.748ms	50	50	100.00
V2	sideload	keymgr_sideload	45.380s	6.398ms	49	50	98.00
		keymgr_sideload_kmac	54.660s	3.235ms	50	50	100.00
		keymgr_sideload_aes	1.206m	7.129ms	50	50	100.00
		keymgr_sideload_otbn	36.620s	1.021ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.170s	841.879us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	16.630s	686.487us	47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.500s	601.542us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	59.660s	10.290ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	27.360s	3.781ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.590s	1.302ms	49	50	98.00
V2	stress_all	keymgr_stress_all	7.424m	16.973ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.970s	122.983us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.090s	26.866us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.620s	1.306ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.620s	1.306ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.590s	260.744us	5	5	100.00
		keymgr_csr_rw	1.660s	134.797us	20	20	100.00
		keymgr_csr_aliasing	17.870s	1.028ms	5	5	100.00
		keymgr_same_csr_outstanding	4.230s	131.931us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.590s	260.744us	5	5	100.00
		keymgr_csr_rw	1.660s	134.797us	20	20	100.00
		keymgr_csr_aliasing	17.870s	1.028ms	5	5	100.00
		keymgr_same_csr_outstanding	4.230s	131.931us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
		keymgr_tl_intg_err	11.060s	1.140ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.750s	332.620us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.750s	332.620us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.750s	332.620us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.750s	332.620us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.990s	383.913us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.060s	1.140ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.750s	332.620us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.899m	8.748ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	40.480s	3.964ms	49	50	98.00
		keymgr_csr_rw	1.660s	134.797us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	40.480s	3.964ms	49	50	98.00
		keymgr_csr_rw	1.660s	134.797us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	40.480s	3.964ms	49	50	98.00
		keymgr_csr_rw	1.660s	134.797us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.630s	686.487us	47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	27.360s	3.781ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	27.360s	3.781ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	40.480s	3.964ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.060s	1.596ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	55.600s	3.111ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.630s	686.487us	47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	55.600s	3.111ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	55.600s	3.111ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	55.600s	3.111ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.250s	1.979ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	55.600s	3.111ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.650s	2.907ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1075	1110	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	11	68.75
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	98.19	98.23	100.00	99.11	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test keymgr_stress_all_with_rand_reset has 25 failures.
  - 1.keymgr_stress_all_with_rand_reset.48693141930632305525954852242673586167127224837009626792773156126627906142884
    Line 528, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157528908 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 157528908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.101184649064860957150132801682817818660737790871044991286044438920180235407552
    Line 669, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 164316577 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 164316577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 7 failures:

Test keymgr_sideload has 1 failures.

1.keymgr_sideload.65591511214922079903153167115769597669794482233734978223789911208595125824594
Line 262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sideload/latest/run.log

  UVM_ERROR @   3880489 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3880489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

13.keymgr_stress_all.85561429219065871844029801787560120696398054497344203538089964452876659864541
Line 2727, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 309096204 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 309096204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.keymgr_stress_all.106010593847549778119799425403806605219536181878917502957191319277796809155332
Line 702, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 833351099 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 833351099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_custom_cm has 1 failures.

23.keymgr_custom_cm.15685646178242764460489552988532205761368402531167818446885171861752378584862
Line 385, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_custom_cm/latest/run.log

  UVM_ERROR @ 121175523 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 121175523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

31.keymgr_lc_disable.49331069479234325589734840625078343548888443385390387495505208713557785691664
Line 366, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  17568865 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  17568865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_random has 1 failures.

37.keymgr_random.45822457702653508994463485519708947997319117717877864921939819770550019580917
Line 403, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_random/latest/run.log

  UVM_ERROR @  21141951 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  21141951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 9.keymgr_lc_disable.54031754895769703502251481799467586239284234577553875325707172788538459719415
    Line 430, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  51852421 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (980825371 [0x3a76351b] vs 980825371 [0x3a76351b]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @  51852421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 19.keymgr_sync_async_fault_cross.110456830728025089651967156678996021789374000368425839123852424115439759519048
    Line 334, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 2981584184 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2981584184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

27.keymgr_lc_disable.95994842015333601875594429844215734843545765585501453539156276788660595242335
Line 572, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  84811426 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (11811405484852264541159835337625812812896693572339395284880232688087403908301797540428061117494675806398509135592966618203823488884147290658283663888449948 [0xe184f288408a2add054ef03740c774310df41a0501fb2d41b6871653d3c7f0ee228286213c3dc1e319f63e7229b3e71b915bba4e818b4bc96dcd9aef94ab819c] vs 11811405484852264541159835337625812812896693572339395284880232688087403908301797540428061117494675806398509135592966618203823488884147290658283663888449948 [0xe184f288408a2add054ef03740c774310df41a0501fb2d41b6871653d3c7f0ee228286213c3dc1e319f63e7229b3e71b915bba4e818b4bc96dcd9aef94ab819c]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @  84811426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---