0e5093d709
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 36.540s | 3.815ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 42.030s | 1.596ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.450s | 34.454us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 28.880s | 1.116ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 7.100s | 133.924us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.620s | 660.702us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 7.100s | 133.924us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.257m | 10.422ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 1.228m | 7.435ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 47.680s | 3.464ms | 49 | 50 | 98.00 | ||
keymgr_sideload_aes | 45.040s | 1.932ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.125m | 13.731ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 22.720s | 757.335us | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 27.320s | 1.766ms | 47 | 50 | 94.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 1.551m | 23.577ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.308m | 4.475ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.556m | 13.236ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 27.320s | 4.497ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 3.715m | 23.465ms | 50 | 50 | 100.00 |
V2 | intr_test | keymgr_intr_test | 0.900s | 172.982us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.110s | 53.503us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.350s | 226.676us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.350s | 226.676us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.450s | 34.454us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 7.100s | 133.924us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.260s | 129.828us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.450s | 34.454us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 7.100s | 133.924us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.260s | 129.828us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.000s | 1.889ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 3.800s | 381.819us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 3.800s | 381.819us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 3.800s | 381.819us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 3.800s | 381.819us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 16.300s | 542.352us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.000s | 1.889ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 3.800s | 381.819us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.257m | 10.422ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 42.030s | 1.596ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 42.030s | 1.596ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 42.030s | 1.596ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.560s | 107.312us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 27.320s | 1.766ms | 47 | 50 | 94.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.556m | 13.236ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.556m | 13.236ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 42.030s | 1.596ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 19.430s | 886.139us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 22.310s | 781.963us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 27.320s | 1.766ms | 47 | 50 | 94.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 22.310s | 781.963us | 49 | 50 | 98.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 22.310s | 781.963us | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 22.310s | 781.963us | 49 | 50 | 98.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 15.600s | 1.876ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 22.310s | 781.963us | 49 | 50 | 98.00 |
V2S | TOTAL | 164 | 165 | 99.39 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 25.640s | 5.101ms | 22 | 50 | 44.00 |
V3 | TOTAL | 22 | 50 | 44.00 | |||
TOTAL | 1077 | 1110 | 97.03 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 14 | 87.50 |
V2S | 6 | 6 | 5 | 83.33 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.42 | 99.00 | 98.07 | 98.57 | 97.67 | 98.93 | 98.41 | 91.27 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 25 failures:
0.keymgr_stress_all_with_rand_reset.650680253155389495380349516970801634638957725913830868284235938887102738224
Line 331, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1008572846 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1008572846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.84348867602843908359125777035557913359125118569818809244854711756127648746444
Line 666, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 204703942 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 204703942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 4 failures:
Test keymgr_sideload_kmac has 1 failures.
2.keymgr_sideload_kmac.38430708422950361778434973447229769561042408451863344300415659513113863150008
Line 300, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest/run.log
UVM_ERROR @ 25822515 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 25822515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
2.keymgr_stress_all_with_rand_reset.75076319665295502822658309129847998992533969831155054621986468183153315443640
Line 547, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 42189507 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 42189507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_custom_cm has 1 failures.
13.keymgr_custom_cm.32158296898463626955151278796534919084288235871180065362356258554162478519939
Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_custom_cm/latest/run.log
UVM_ERROR @ 119764573 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 119764573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
43.keymgr_lc_disable.112753493570518564831554541856608883504662863984988825612268594487661006583194
Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/43.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 63776028 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 63776028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 2 failures:
36.keymgr_lc_disable.108568973326142805895127583675376750173197158733813696067926466377321185646956
Line 337, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 20304204 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_2
UVM_INFO @ 20304204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.keymgr_lc_disable.87524460504117274020148633218536588299797168563965894446204007703818330118351
Line 422, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 48129094 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
UVM_INFO @ 48129094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
13.keymgr_stress_all_with_rand_reset.95268892311073060685284474791153487784890783088187461767902152129991245567719
Line 296, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 422901328 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 422901328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:546) [scoreboard] Check failed item.d_data == addr_phase_cfg_regwen (* [*] vs * [*])
has 1 failures:
15.keymgr_stress_all_with_rand_reset.86910393852926644561844893448719204970894406279956536830111524586630337727341
Line 910, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 178958211 ps: (keymgr_scoreboard.sv:546) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_cfg_regwen (0 [0x0] vs 1 [0x1])
UVM_INFO @ 178958211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---