KEYMGR Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.050s	1.765ms	49	50	98.00
V1	random	keymgr_random	2.018m	11.032ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.120s	32.235us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.630s	33.040us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	15.540s	1.273ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.970s	1.388ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.400s	79.018us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.630s	33.040us	20	20	100.00
		keymgr_csr_aliasing	14.970s	1.388ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	2.062m	26.954ms	49	50	98.00
V2	sideload	keymgr_sideload	40.720s	3.143ms	50	50	100.00
		keymgr_sideload_kmac	40.340s	4.557ms	50	50	100.00
		keymgr_sideload_aes	58.590s	1.806ms	50	50	100.00
		keymgr_sideload_otbn	1.100m	13.496ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.310s	3.956ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	31.320s	4.266ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.060s	201.473us	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.000s	2.130ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	27.130s	1.382ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.060s	841.809us	50	50	100.00
V2	stress_all	keymgr_stress_all	8.676m	44.298ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.920s	35.537us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.120s	29.627us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.140s	465.442us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.140s	465.442us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.120s	32.235us	5	5	100.00
		keymgr_csr_rw	1.630s	33.040us	20	20	100.00
		keymgr_csr_aliasing	14.970s	1.388ms	5	5	100.00
		keymgr_same_csr_outstanding	4.430s	122.188us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.120s	32.235us	5	5	100.00
		keymgr_csr_rw	1.630s	33.040us	20	20	100.00
		keymgr_csr_aliasing	14.970s	1.388ms	5	5	100.00
		keymgr_same_csr_outstanding	4.430s	122.188us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
		keymgr_tl_intg_err	11.740s	750.955us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.750s	367.586us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.750s	367.586us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.750s	367.586us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.750s	367.586us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.080s	1.574ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.740s	750.955us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.750s	367.586us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.062m	26.954ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.018m	11.032ms	50	50	100.00
		keymgr_csr_rw	1.630s	33.040us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.018m	11.032ms	50	50	100.00
		keymgr_csr_rw	1.630s	33.040us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.018m	11.032ms	50	50	100.00
		keymgr_csr_rw	1.630s	33.040us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	31.320s	4.266ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	27.130s	1.382ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	27.130s	1.382ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.018m	11.032ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.490s	1.704ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	17.130s	7.645ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	31.320s	4.266ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	17.130s	7.645ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	17.130s	7.645ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	17.130s	7.645ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.040s	1.595ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	17.130s	7.645ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.050s	4.318ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			1090	1110	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.15	98.37	100.00	99.02	98.41	91.17

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test keymgr_stress_all_with_rand_reset has 15 failures.

    • 1.keymgr_stress_all_with_rand_reset.3263338832373790642082540220430143725853185369280489009251513889526187595374
      Line 740, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 860352813 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 860352813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.71653929846091738856137485740135740570858821828273503763769701666379032086813
      Line 1205, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2822496994 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2822496994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_smoke has 1 failures.

    • 12.keymgr_smoke.58247845604110539067725092779107134134755372206310097297604053830320145409282
      Line 385, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_smoke/latest/run.log

        UVM_ERROR @ 281650851 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 281650851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 30.keymgr_kmac_rsp_err.106389083098645550048686703005960124915685091864584858233582531912363984383329
      Line 361, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @   7653885 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   7653885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 41.keymgr_stress_all.45672467588042545929633523435581966029496879532394499275884563939226949917913
      Line 1864, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 527560472 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 527560472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 36.keymgr_cfg_regwen.36903068893411352545763940311924225796866786239571225708478278501644886440833
      Line 346, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  17040861 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
        UVM_INFO @  17040861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 46.keymgr_kmac_rsp_err.54337331812666997065350942627730624958929768539907261775050796228016682070727
      Line 547, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  23284809 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  23284809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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