KEYMGR Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.690s	14.368ms	50	50	100.00
V1	random	keymgr_random	1.360m	4.852ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.500s	60.245us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.720s	28.450us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.130s	3.589ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.730s	252.027us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.330s	50.597us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.720s	28.450us	20	20	100.00
		keymgr_csr_aliasing	8.730s	252.027us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.251m	5.399ms	50	50	100.00
V2	sideload	keymgr_sideload	1.028m	6.122ms	50	50	100.00
		keymgr_sideload_kmac	38.260s	2.405ms	50	50	100.00
		keymgr_sideload_aes	58.040s	3.413ms	50	50	100.00
		keymgr_sideload_otbn	49.200s	8.508ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.170s	598.910us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.910s	2.390ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.210s	1.064ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	46.980s	4.348ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	50.120s	1.757ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.720s	944.797us	50	50	100.00
V2	stress_all	keymgr_stress_all	3.664m	7.630ms	46	50	92.00
V2	intr_test	keymgr_intr_test	0.940s	16.625us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.350s	159.212us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.480s	278.124us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.480s	278.124us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.500s	60.245us	5	5	100.00
		keymgr_csr_rw	1.720s	28.450us	20	20	100.00
		keymgr_csr_aliasing	8.730s	252.027us	5	5	100.00
		keymgr_same_csr_outstanding	4.560s	488.580us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.500s	60.245us	5	5	100.00
		keymgr_csr_rw	1.720s	28.450us	20	20	100.00
		keymgr_csr_aliasing	8.730s	252.027us	5	5	100.00
		keymgr_same_csr_outstanding	4.560s	488.580us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
		keymgr_tl_intg_err	10.550s	297.961us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.840s	228.262us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.840s	228.262us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.840s	228.262us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.840s	228.262us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.280s	1.966ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.550s	297.961us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.840s	228.262us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.251m	5.399ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.360m	4.852ms	50	50	100.00
		keymgr_csr_rw	1.720s	28.450us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.360m	4.852ms	50	50	100.00
		keymgr_csr_rw	1.720s	28.450us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.360m	4.852ms	50	50	100.00
		keymgr_csr_rw	1.720s	28.450us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.910s	2.390ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	50.120s	1.757ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	50.120s	1.757ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.360m	4.852ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.290s	1.621ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.340s	10.743ms	48	50	96.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.910s	2.390ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.340s	10.743ms	48	50	96.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.340s	10.743ms	48	50	96.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.340s	10.743ms	48	50	96.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.670s	1.605ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.340s	10.743ms	48	50	96.00
V2S		TOTAL			163	165	98.79
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.950s	3.247ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	98.11	98.46	100.00	99.02	98.41	91.17

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test keymgr_stress_all_with_rand_reset has 21 failures.

    • 0.keymgr_stress_all_with_rand_reset.24908899160014655138813173296540467945109179978890182968940096866473096638257
      Line 277, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 128424323 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 128424323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.keymgr_stress_all_with_rand_reset.38254854087729448033761465923582644291163559038931659296647852696464012781031
      Line 479, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 124835488 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 124835488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 2 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 16.keymgr_lc_disable.15266721509781684658593457956643730181849531386179919632679804828895539374077
      Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_lc_disable/latest/run.log

        UVM_ERROR @ 224362289 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3280731908 [0xc38bff04] vs 3280731908 [0xc38bff04]) reg name: keymgr_reg_block.sw_share0_output_1
        UVM_INFO @ 224362289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 29.keymgr_stress_all.44248516864311207558760175646674005363897061575667502800203988407422834891353
      Line 1748, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 3828917551 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_6
        UVM_INFO @ 3828917551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all has 2 failures.

    • 39.keymgr_stress_all.73230638451928330915900185880356393553711578893612887575762316569027256357813
      Line 820, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log

        UVM_ERROR @  70015989 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  70015989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.keymgr_stress_all.38947826011548734261498326488266108608195616405277570442905607409438743130067
      Line 743, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log

        UVM_ERROR @  53770299 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  53770299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_reg_block.fault_status.cmd reset value: * has 1 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 19.keymgr_custom_cm.104266844254411759129735152518564819394850367549823632195056406505129112138270
      Line 403, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_custom_cm/latest/run.log

        UVM_ERROR @  49786327 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: keymgr_reg_block.fault_status.cmd reset value: 0x0
        UVM_INFO @  49786327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 34.keymgr_kmac_rsp_err.52401893028118145147485597249839056693726923518057880234596057160765492952015
      Line 428, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  77745798 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  77745798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 35.keymgr_stress_all.74776833150239352801388067975383029327925178990271839498850763253585730175673
      Line 2152, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 1834857466 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
        UVM_INFO @ 1834857466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 36.keymgr_custom_cm.72154631110068047726416661585104236365627411264848025210713407673472362775352
      Line 374, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_custom_cm/latest/run.log

        UVM_FATAL @ 10742908184 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
        UVM_INFO @ 10742908184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.05.20_03.54.36
• 2024.05.17_06.22.46
• 2024.05.15_02.51.30
• 2024.05.13_03.39.55
• 2024.05.10_04.26.46
• 2024.05.08_03.36.08