8cb25a6867
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 50.550s | 6.376ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.440m | 8.948ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.520s | 35.947us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 30.250s | 5.116ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 18.220s | 2.154ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.200s | 53.942us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 18.220s | 2.154ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.758m | 2.019ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 57.820s | 6.678ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 37.240s | 3.849ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.097m | 4.194ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 34.080s | 1.359ms | 49 | 50 | 98.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 17.060s | 1.808ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 7.370s | 904.388us | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 7.480s | 1.672ms | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 56.430s | 5.747ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.287m | 11.283ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 10.330s | 310.445us | 49 | 50 | 98.00 |
V2 | stress_all | keymgr_stress_all | 3.649m | 7.791ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.920s | 15.173us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.570s | 97.060us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.610s | 119.904us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.610s | 119.904us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.520s | 35.947us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 18.220s | 2.154ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.930s | 280.354us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.520s | 35.947us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 18.220s | 2.154ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.930s | 280.354us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.670s | 1.560ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.780s | 480.251us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.780s | 480.251us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.780s | 480.251us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.780s | 480.251us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 14.670s | 2.544ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.670s | 1.560ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.780s | 480.251us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.758m | 2.019ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.440m | 8.948ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.440m | 8.948ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.440m | 8.948ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.440s | 28.699us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 7.370s | 904.388us | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.287m | 11.283ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.287m | 11.283ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.440m | 8.948ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 30.990s | 7.542ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 18.460s | 396.242us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 7.370s | 904.388us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 18.460s | 396.242us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 18.460s | 396.242us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 18.460s | 396.242us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 20.040s | 2.781ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 18.460s | 396.242us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 38.440s | 3.273ms | 25 | 50 | 50.00 |
V3 | TOTAL | 25 | 50 | 50.00 | |||
TOTAL | 1081 | 1110 | 97.39 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.37 | 99.00 | 98.03 | 98.39 | 97.67 | 98.93 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 22 failures:
3.keymgr_stress_all_with_rand_reset.22199029759360749040863436136177065382425058036579902075235396973763942380239
Line 421, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 236817589 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 236817589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_stress_all_with_rand_reset.50947823228767227042071144961237652588973284768442532172296630633389874519214
Line 385, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 943178054 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 943178054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_sideload_otbn has 1 failures.
30.keymgr_sideload_otbn.49292256272193851718840803473741565225269164087837011883329198367981103591450
Line 276, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest/run.log
UVM_ERROR @ 54177176 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 54177176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all_with_rand_reset has 1 failures.
32.keymgr_stress_all_with_rand_reset.27754493680580701352401291588991793341258943454467222190117862283216238113546
Line 2467, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 655459248 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 655459248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
8.keymgr_stress_all_with_rand_reset.670651400691101906029609379453346472347280078212177669439569917084474576910
Line 858, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1069562944 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (9777732532724985572894451224968929080697245658527558756843058772416420448991170142016534205416299176282311418804299753967477572880334591990434225772709599957531812267578380296522445584474272446247904676273273574946769531215527473540064652026998437442501315824559548271129734937916967237121140030311355811935020906585451178946329933655249254527737 [0x28eb37dd000000009c1bcce0000000000000000064020721b97c82e8000000005827d19107e50b5793c7caff58d3996a0a6cd88afc020a2b9be51303c22ac465c844fe5b6b71422536a31eaf15cce9dfc75fc817ea78f2948832b721c2b5a02a67682b83225fdcf27f27adf7fcf71f1d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 11863923388419195690747878251194181372945457345744841219858196974965065236348232799810720069131225551715785164990200814805690352402272738400864350244856842706019451587944771190452632580075731168701962936914042654549797549220030351551124076140923423076607259340875131235581476174701301216523467935547696278473702278921019116106889073701625 [0xd53e00d8000000008f786f6762d45b4c00000000a4a8e9cf385283755827d19107e50b5793c7caff58d3996a0a6cd88afc020a2b9be51303c22ac465c844fe5b6b71422536a31eaf15cce9dfc75fc817ea78f2948832b721c2b5a02a67682b83225fdcf27f27adf7fcf71f1d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
RomDigest act: 0xc75fc817ea78f2948832b721c2b5a02a67682b83225fdcf27f27adf7fcf71f1d, exp: 0xc75fc817ea78f2948832b721c2b5a02a67682b83225fdcf27f27adf7fcf71f1d
HealthMeasurement act: 0xc844fe5b6b71422536a31eaf15cce9df, exp: 0xc844fe5b6b71422536a31eaf15cce9df
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received!
has 1 failures:
15.keymgr_sync_async_fault_cross.15680406277914149583540748776057116612561446022247237669311927210384883254183
Line 347, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 80471044 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
UVM_INFO @ 80471044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
17.keymgr_stress_all_with_rand_reset.81839716980128868407630623657730704101008623872815374609851399359302780257186
Line 562, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 508609131 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 508609131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes
has 1 failures:
19.keymgr_stress_all.110082296952785349739296508160968636045287326027310156795024970073197725973271
Line 1065, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all/latest/run.log
UVM_ERROR @ 117906664 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3262321353033093290324581117803784223144404404459305679831829990816398573173150304363304358368990175141010393456766790571854951789821736316548609442282802 [0x3e49e5051d2e3c1c8ce49482d3bd54628d3fa6e88b51418e97cf0ada51531f79378059f500fac0b545e36030a1d2aca9d48437b0a28428454f6b4f1f3f937d32] vs 3262321353033093290324581117803784223144404404459305679831829990816398573173150304363304358368990175141010393456766790571854951789821736316548609442282802 [0x3e49e5051d2e3c1c8ce49482d3bd54628d3fa6e88b51418e97cf0ada51531f79378059f500fac0b545e36030a1d2aca9d48437b0a28428454f6b4f1f3f937d32]) AES key at state StDisabled for Attestation Aes
UVM_INFO @ 117906664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*])
has 1 failures:
48.keymgr_lc_disable.52297041366225223723083467741414327116947995301974542318486975640072249311707
Line 359, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 25033835 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
UVM_INFO @ 25033835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---