KEYMGR Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	32.070s	2.120ms	50	50	100.00
V1	random	keymgr_random	1.087m	3.445ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.140s	68.293us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.580s	89.157us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	31.890s	2.624ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.510s	665.688us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.700s	38.220us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.580s	89.157us	20	20	100.00
		keymgr_csr_aliasing	14.510s	665.688us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.378m	1.453ms	49	50	98.00
V2	sideload	keymgr_sideload	43.370s	1.361ms	50	50	100.00
		keymgr_sideload_kmac	47.310s	12.379ms	50	50	100.00
		keymgr_sideload_aes	45.150s	20.727ms	50	50	100.00
		keymgr_sideload_otbn	41.100s	1.417ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	19.580s	760.163us	49	50	98.00
V2	lc_disable	keymgr_lc_disable	11.330s	410.017us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.550s	148.980us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.388m	8.747ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	41.870s	12.064ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	47.730s	8.932ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.980m	13.045ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.900s	13.384us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.080s	15.145us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.840s	99.138us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.840s	99.138us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.140s	68.293us	5	5	100.00
		keymgr_csr_rw	1.580s	89.157us	20	20	100.00
		keymgr_csr_aliasing	14.510s	665.688us	5	5	100.00
		keymgr_same_csr_outstanding	4.520s	113.447us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.140s	68.293us	5	5	100.00
		keymgr_csr_rw	1.580s	89.157us	20	20	100.00
		keymgr_csr_aliasing	14.510s	665.688us	5	5	100.00
		keymgr_same_csr_outstanding	4.520s	113.447us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
		keymgr_tl_intg_err	13.060s	5.192ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.290s	228.035us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.290s	228.035us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.290s	228.035us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.290s	228.035us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.900s	816.736us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	13.060s	5.192ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.290s	228.035us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.378m	1.453ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.087m	3.445ms	50	50	100.00
		keymgr_csr_rw	1.580s	89.157us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.087m	3.445ms	50	50	100.00
		keymgr_csr_rw	1.580s	89.157us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.087m	3.445ms	50	50	100.00
		keymgr_csr_rw	1.580s	89.157us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	11.330s	410.017us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	41.870s	12.064ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	41.870s	12.064ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.087m	3.445ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	26.990s	6.133ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	35.560s	4.720ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	11.330s	410.017us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	35.560s	4.720ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	35.560s	4.720ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	35.560s	4.720ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.890s	2.859ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	35.560s	4.720ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.770s	2.683ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	11	68.75
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	97.91	98.47	100.00	99.02	98.41	91.19

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test keymgr_stress_all_with_rand_reset has 18 failures.

    • 3.keymgr_stress_all_with_rand_reset.81085018841212624963901254875351849376555094781454158660673520679016606446645
      Line 413, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1396767180 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1396767180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.keymgr_stress_all_with_rand_reset.16287393536548542126951259927044474778670634509508409445030537177469107074396
      Line 326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 213030561 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 213030561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_direct_to_disabled has 1 failures.

    • 25.keymgr_direct_to_disabled.79275103977646434498262828245640553409574694598554312059251801377259132486101
      Line 302, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest/run.log

        UVM_ERROR @  10869228 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  10869228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_otbn has 1 failures.

    • 27.keymgr_sideload_otbn.48988545952362533921400514876963648857614858818815956353307317499499055196358
      Line 266, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest/run.log

        UVM_ERROR @  22390855 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  22390855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_cfg_regwen has 1 failures.

    • 34.keymgr_cfg_regwen.25190197250408921026351765390651639089519059532770809587421020257202399636191
      Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  10550794 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  10550794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 2 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 27.keymgr_stress_all_with_rand_reset.105210562255367644909515697792802627204387997547628304363889336402111890056651
      Line 2526, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 460968210 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
        UVM_INFO @ 460968210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 31.keymgr_stress_all.80423272052640399937259884383667751635758824400490897070256867903085845642904
      Line 1712, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 1369000051 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
        UVM_INFO @ 1369000051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 14.keymgr_custom_cm.89045798053677404687640864047403841354452637730262906975777627032612122697497
      Line 344, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_custom_cm/latest/run.log

        UVM_FATAL @ 10164288081 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
        UVM_INFO @ 10164288081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 41.keymgr_kmac_rsp_err.94213636757970055633881958551728120426972976197362914611764250694204675238161
      Line 451, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  24859979 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  24859979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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