KEYMGR Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	47.070s	1.574ms	50	50	100.00
V1	random	keymgr_random	1.281m	8.288ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.170s	23.433us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.660s	31.525us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.010s	1.529ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.650s	510.880us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.370s	194.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.660s	31.525us	20	20	100.00
		keymgr_csr_aliasing	8.650s	510.880us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.948m	4.228ms	50	50	100.00
V2	sideload	keymgr_sideload	37.000s	1.091ms	50	50	100.00
		keymgr_sideload_kmac	21.590s	847.792us	50	50	100.00
		keymgr_sideload_aes	40.850s	3.777ms	50	50	100.00
		keymgr_sideload_otbn	54.430s	1.707ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	14.630s	4.305ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	16.330s	1.209ms	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	14.890s	5.525ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	52.430s	3.902ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.140m	13.762ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	40.420s	5.591ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.870m	48.321ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.880s	30.472us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.060s	24.870us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.630s	317.069us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.630s	317.069us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.170s	23.433us	5	5	100.00
		keymgr_csr_rw	1.660s	31.525us	20	20	100.00
		keymgr_csr_aliasing	8.650s	510.880us	5	5	100.00
		keymgr_same_csr_outstanding	4.160s	1.442ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.170s	23.433us	5	5	100.00
		keymgr_csr_rw	1.660s	31.525us	20	20	100.00
		keymgr_csr_aliasing	8.650s	510.880us	5	5	100.00
		keymgr_same_csr_outstanding	4.160s	1.442ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
		keymgr_tl_intg_err	8.470s	216.625us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.630s	206.781us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.630s	206.781us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.630s	206.781us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.630s	206.781us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.850s	806.047us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.470s	216.625us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.630s	206.781us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.948m	4.228ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.281m	8.288ms	50	50	100.00
		keymgr_csr_rw	1.660s	31.525us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.281m	8.288ms	50	50	100.00
		keymgr_csr_rw	1.660s	31.525us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.281m	8.288ms	50	50	100.00
		keymgr_csr_rw	1.660s	31.525us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.330s	1.209ms	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.140m	13.762ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.140m	13.762ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.281m	8.288ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.630s	1.060ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.300m	5.076ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.330s	1.209ms	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.300m	5.076ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.300m	5.076ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.300m	5.076ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	21.200s	639.549us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.300m	5.076ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.670s	894.648us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	98.07	98.52	100.00	99.02	98.41	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 2.keymgr_stress_all_with_rand_reset.73740244272125477900934920526002365805631436979871759682440510319723579592882
    Line 561, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 439110253 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 439110253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.115417701938274912289838694391735142084348862948534266387296487303913199354010
    Line 371, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1108905771 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1108905771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_custom_cm has 1 failures.
  - 26.keymgr_custom_cm.14169103773966655182169682622563631682042481594930615712841335291308661925850
    Line 324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_custom_cm/latest/run.log
```
  UVM_ERROR @   5777737 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   5777737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_lc_disable has 1 failures.
  - 36.keymgr_lc_disable.8451026793931470763061265632255100760805431374955606580304650863201383593339
    Line 325, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  85966830 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  85966830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 1.keymgr_hwsw_invalid_input.5427163651648280700593050065384194953991999031719303128375116695745543684628
    Line 353, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  18897038 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  18897038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 9.keymgr_stress_all_with_rand_reset.41916037130323769090454920285118365634139680969159550627223101405659693032471
    Line 1246, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 280392429 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 280392429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 10.keymgr_stress_all.95830679279057071488156907257260562238627797902879167223921062651190698278172
    Line 743, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 386239874 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2758966170 [0xa4727b9a] vs 2758966170 [0xa4727b9a]) reg name: keymgr_reg_block.sw_share1_output_4
  UVM_INFO @ 386239874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

17.keymgr_lc_disable.108663711445403835712811299341298545457883194185920473238109337619262127849208
Line 381, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  59825572 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4564061562962707660179629297115213600494813912552851673933546308221188042013154788950248503719228326058948569881859557011004229696802601231838299589874812 [0x5724ab1017dcfe5157e4cb89fb549fd57fa1c2e590c5176d21a94f134eb1993f7bf4e4cf16d6de5a31cce8663530df8980d806f6a8205845d19f104c2f66947c] vs 4564061562962707660179629297115213600494813912552851673933546308221188042013154788950248503719228326058948569881859557011004229696802601231838299589874812 [0x5724ab1017dcfe5157e4cb89fb549fd57fa1c2e590c5176d21a94f134eb1993f7bf4e4cf16d6de5a31cce8663530df8980d806f6a8205845d19f104c2f66947c]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @  59825572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---