KEYMGR Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	44.270s	11.955ms	49	50	98.00
V1	random	keymgr_random	1.259m	7.641ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.230s	21.775us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.630s	55.731us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.170s	2.217ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.590s	765.172us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.470s	218.612us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.630s	55.731us	20	20	100.00
		keymgr_csr_aliasing	11.590s	765.172us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	2.199m	2.700ms	50	50	100.00
V2	sideload	keymgr_sideload	49.550s	2.868ms	49	50	98.00
		keymgr_sideload_kmac	54.520s	16.008ms	50	50	100.00
		keymgr_sideload_aes	47.570s	7.485ms	50	50	100.00
		keymgr_sideload_otbn	33.280s	1.447ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	54.450s	6.350ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.320s	322.325us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	18.350s	11.244ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.350m	9.747ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	23.730s	5.750ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	21.290s	2.176ms	49	50	98.00
V2	stress_all	keymgr_stress_all	6.072m	16.724ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.950s	16.369us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.300s	75.833us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.250s	584.699us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.250s	584.699us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.230s	21.775us	5	5	100.00
		keymgr_csr_rw	1.630s	55.731us	20	20	100.00
		keymgr_csr_aliasing	11.590s	765.172us	5	5	100.00
		keymgr_same_csr_outstanding	4.180s	447.531us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.230s	21.775us	5	5	100.00
		keymgr_csr_rw	1.630s	55.731us	20	20	100.00
		keymgr_csr_aliasing	11.590s	765.172us	5	5	100.00
		keymgr_same_csr_outstanding	4.180s	447.531us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
		keymgr_tl_intg_err	10.800s	633.955us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.960s	127.367us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.960s	127.367us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.960s	127.367us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.960s	127.367us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.250s	1.889ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.800s	633.955us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.960s	127.367us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.199m	2.700ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.259m	7.641ms	50	50	100.00
		keymgr_csr_rw	1.630s	55.731us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.259m	7.641ms	50	50	100.00
		keymgr_csr_rw	1.630s	55.731us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.259m	7.641ms	50	50	100.00
		keymgr_csr_rw	1.630s	55.731us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.320s	322.325us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	23.730s	5.750ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	23.730s	5.750ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.259m	7.641ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.670s	4.703ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	8.820s	1.386ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.320s	322.325us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	8.820s	1.386ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	8.820s	1.386ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	8.820s	1.386ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.240s	772.072us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	8.820s	1.386ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.760s	9.772ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			1075	1110	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.19	98.28	100.00	99.02	98.41	91.22

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test keymgr_stress_all_with_rand_reset has 28 failures.
  - 0.keymgr_stress_all_with_rand_reset.81334727889709921789760427471319642172634148591841027215075808954503715974866
    Line 380, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107951723 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107951723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.89099694499927126444900518066480888800389679005093485829544145987057743134325
    Line 1332, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 712351147 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 712351147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_smoke has 1 failures.
  - 21.keymgr_smoke.108099276227198263297478827850016846429096607794134009316948118418649543518036
    Line 279, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_smoke/latest/run.log
```
  UVM_ERROR @   3135955 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3135955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload has 1 failures.
  - 40.keymgr_sideload.83346452729215196931095063075755061051906935913290752990170690030889970298685
    Line 349, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_sideload/latest/run.log
```
  UVM_ERROR @  87880799 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  87880799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 43.keymgr_stress_all.18278845784615475899400123959991634925207311508611962505343536483225748164072
    Line 612, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/43.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  84476690 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  84476690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 7.keymgr_stress_all_with_rand_reset.26066790401393321759038749821930292092163741942106075740676325616817718047670
    Line 1501, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 627999177 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 627999177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 25.keymgr_sync_async_fault_cross.54399624638559991253253899354788811314915595162793475053019187608814331658165
    Line 317, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 138787539 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 138787539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

26.keymgr_lc_disable.78766155584245690479734958737381409500340066479568210983752460057030086879498
Line 572, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 157488518 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (1850582171936804035302136019458902399623212708823572498278600142698363126005694210018084722232181858922761409897576841746024382902283776998158591665114872 [0x2355750d3aa694dc8064b7ecfba28d2f8200155d615d25e726d6400272c82980730834e3d014feb2b6a5cfd97aaa036ff5ab415d7dc51c7bc1a8c71555b40ef8] vs 1850582171936804035302136019458902399623212708823572498278600142698363126005694210018084722232181858922761409897576841746024382902283776998158591665114872 [0x2355750d3aa694dc8064b7ecfba28d2f8200155d615d25e726d6400272c82980730834e3d014feb2b6a5cfd97aaa036ff5ab415d7dc51c7bc1a8c71555b40ef8]) AES key at state StOwnerKey for Sealing Aes
  UVM_INFO @ 157488518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 26.keymgr_stress_all.54858129936730171771181061735637483452568029609905615237216861906678396696735
    Line 1691, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 773987419 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3937630859 [0xeab37a8b] vs 3937630859 [0xeab37a8b]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 773987419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```