KEYMGR Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.540s	749.287us	50	50	100.00
V1	random	keymgr_random	47.860s	9.635ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.310s	25.059us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.600s	31.918us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.850s	3.457ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	13.700s	5.137ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.270s	77.447us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.600s	31.918us	20	20	100.00
		keymgr_csr_aliasing	13.700s	5.137ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.410m	7.916ms	49	50	98.00
V2	sideload	keymgr_sideload	45.770s	22.549ms	50	50	100.00
		keymgr_sideload_kmac	58.070s	6.443ms	50	50	100.00
		keymgr_sideload_aes	59.750s	5.496ms	50	50	100.00
		keymgr_sideload_otbn	55.300s	3.082ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.020s	2.775ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	18.420s	674.111us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.630s	284.765us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	50.460s	1.712ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.920s	1.267ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	8.330s	869.404us	50	50	100.00
V2	stress_all	keymgr_stress_all	6.942m	19.989ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.920s	48.052us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.150s	57.929us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.430s	633.647us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.430s	633.647us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.310s	25.059us	5	5	100.00
		keymgr_csr_rw	1.600s	31.918us	20	20	100.00
		keymgr_csr_aliasing	13.700s	5.137ms	5	5	100.00
		keymgr_same_csr_outstanding	3.360s	163.220us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.310s	25.059us	5	5	100.00
		keymgr_csr_rw	1.600s	31.918us	20	20	100.00
		keymgr_csr_aliasing	13.700s	5.137ms	5	5	100.00
		keymgr_same_csr_outstanding	3.360s	163.220us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
		keymgr_tl_intg_err	10.660s	314.021us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.920s	329.444us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.920s	329.444us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.920s	329.444us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.920s	329.444us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.270s	508.585us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.660s	314.021us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.920s	329.444us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.410m	7.916ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	47.860s	9.635ms	49	50	98.00
		keymgr_csr_rw	1.600s	31.918us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	47.860s	9.635ms	49	50	98.00
		keymgr_csr_rw	1.600s	31.918us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	47.860s	9.635ms	49	50	98.00
		keymgr_csr_rw	1.600s	31.918us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	18.420s	674.111us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.920s	1.267ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.920s	1.267ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	47.860s	9.635ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	15.580s	635.925us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.243m	10.064ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	18.420s	674.111us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.243m	10.064ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.243m	10.064ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.243m	10.064ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	40.580s	1.633ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.243m	10.064ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	36.940s	11.238ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	12	75.00
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.04	98.11	98.60	100.00	99.02	98.41	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 0.keymgr_stress_all_with_rand_reset.855742857707266451240069956566676823104305359612019786882298496856902808707
    Line 545, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2152426506 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2152426506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.6195904755920461059516725225196266970745622885295487662928955545147101103404
    Line 304, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 485411547 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 485411547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:

Test keymgr_lc_disable has 1 failures.

1.keymgr_lc_disable.6169522162753670261040812088028575624415226887507486556338103212840883147782
Line 344, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 201218356 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2921857540 [0xae280204] vs 2921857540 [0xae280204]) reg name: keymgr_reg_block.sw_share1_output_4
  UVM_INFO @ 201218356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

48.keymgr_stress_all.20090076248953473906678033011187320838662467365957412944347741866162322970663
Line 2063, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 265201843 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2445030260 [0x91bc3374] vs 2445030260 [0x91bc3374]) reg name: keymgr_reg_block.sw_share1_output_0
  UVM_INFO @ 265201843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_random has 1 failures.
  - 9.keymgr_random.64339812569058147424100596683813430510729296147999124565763147474086643973878
    Line 324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_random/latest/run.log
```
  UVM_ERROR @  26213634 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  26213634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 9.keymgr_cfg_regwen.51488242597153371245867329276538627998460518145445635581965600374883865307256
    Line 315, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   5624197 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   5624197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

15.keymgr_lc_disable.103222169120363967108930585211096150329522471254737325583117115670247719879920
Line 680, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 294550718 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2710121553108049172001824555795970384111932114917274808275691431036440156579768178819695362258412404698019729240412836333923365566148296628759050492593668 [0x33becc57943beba815ae44aa24ea9ae9dfa628aae7a9feaa7eecde7364303ac0211331366d1292731f62f4cbe5e776e8ea5cb0372b0cbbb4ed0bad342c0c4604] vs 2710121553108049172001824555795970384111932114917274808275691431036440156579768178819695362258412404698019729240412836333923365566148296628759050492593668 [0x33becc57943beba815ae44aa24ea9ae9dfa628aae7a9feaa7eecde7364303ac0211331366d1292731f62f4cbe5e776e8ea5cb0372b0cbbb4ed0bad342c0c4604]) KMAC key at state StDisabled for Sealing Kmac
  UVM_INFO @ 294550718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 21.keymgr_stress_all_with_rand_reset.77882163808694883577822112247690827459803179688862167230265211934994146166002
    Line 817, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 598320559 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 598320559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 24.keymgr_stress_all.2167651080626779063241651101126735264239823926993144910689197260162107238982
    Line 471, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 209412405 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_6
  UVM_INFO @ 209412405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 29.keymgr_custom_cm.30261072178671167398627965958104518244153679947467398690726763626551196687643
    Line 468, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10064424451 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10064424451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 42.keymgr_kmac_rsp_err.18471806094966116594582383894074232920476685587370645596953288062360200318584
    Line 611, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  18058837 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  18058837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```