KEYMGR Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.770s	6.316ms	50	50	100.00
V1	random	keymgr_random	1.480m	8.847ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.470s	58.931us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.430s	48.362us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.770s	883.067us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.580s	740.020us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.320s	725.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.430s	48.362us	20	20	100.00
		keymgr_csr_aliasing	9.580s	740.020us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.264m	5.427ms	50	50	100.00
V2	sideload	keymgr_sideload	46.360s	2.574ms	50	50	100.00
		keymgr_sideload_kmac	26.900s	1.411ms	50	50	100.00
		keymgr_sideload_aes	55.990s	3.153ms	50	50	100.00
		keymgr_sideload_otbn	48.750s	9.647ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.120s	2.668ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	34.840s	712.087us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.680s	465.697us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.529m	5.048ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.253m	11.589ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	29.970s	3.969ms	49	50	98.00
V2	stress_all	keymgr_stress_all	8.197m	42.431ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.990s	15.302us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	16.353us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.540s	255.127us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.540s	255.127us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.470s	58.931us	5	5	100.00
		keymgr_csr_rw	1.430s	48.362us	20	20	100.00
		keymgr_csr_aliasing	9.580s	740.020us	5	5	100.00
		keymgr_same_csr_outstanding	4.150s	117.539us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.470s	58.931us	5	5	100.00
		keymgr_csr_rw	1.430s	48.362us	20	20	100.00
		keymgr_csr_aliasing	9.580s	740.020us	5	5	100.00
		keymgr_same_csr_outstanding	4.150s	117.539us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
		keymgr_tl_intg_err	10.890s	522.175us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.720s	186.270us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.720s	186.270us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.720s	186.270us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.720s	186.270us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.070s	448.084us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.890s	522.175us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.720s	186.270us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.264m	5.427ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.480m	8.847ms	50	50	100.00
		keymgr_csr_rw	1.430s	48.362us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.480m	8.847ms	50	50	100.00
		keymgr_csr_rw	1.430s	48.362us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.480m	8.847ms	50	50	100.00
		keymgr_csr_rw	1.430s	48.362us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	34.840s	712.087us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.253m	11.589ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.253m	11.589ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.480m	8.847ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	22.010s	4.390ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	11.500s	312.913us	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	34.840s	712.087us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	11.500s	312.913us	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	11.500s	312.913us	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	11.500s	312.913us	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.580s	4.246ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	11.500s	312.913us	49	50	98.00
V2S		TOTAL			163	165	98.79
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	28.580s	2.348ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1082	1110	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	4	66.67
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.07	98.58	100.00	99.02	98.41	91.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 2.keymgr_stress_all_with_rand_reset.30511093252632732544536742774216088589462082952142542888655219842599756759586
    Line 598, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 924673667 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 924673667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.33849160071231954004432735249264909323923851658652275190639071701218682982336
    Line 436, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 512065643 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 512065643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sideload_protect has 1 failures.
  - 15.keymgr_sideload_protect.44402321343401692780528229482330037944541986471163447195589715542857868333037
    Line 322, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_sideload_protect/latest/run.log
```
  UVM_ERROR @   4040319 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   4040319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_lc_disable has 1 failures.
  - 30.keymgr_lc_disable.85393927904497341145433387240038399538233836898654535682393835594467706531031
    Line 313, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  46699750 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  46699750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 7.keymgr_stress_all_with_rand_reset.29847469825249365291217805007453586412385726525829439309958789004984978757498
    Line 881, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 794442374 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 794442374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 12.keymgr_kmac_rsp_err.47588814849751902404916843935316213563544714797912541461523233215619115613756
    Line 699, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  41643220 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  41643220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

12.keymgr_stress_all.48865668240532744158479106593631202818492432919683406568193354386320593392074
Line 1099, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 761426592 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3257628138054444361478105501864864378220055978247423511254865877811522396372018007949352859147340778300746767440474567180060676362720654314518029858055575 [0x3e32f464183b6ad006308d5adbaaffb14c48527b6f25838976052c326c772f30b2eb682f92671f9a2675bad82a7123e605de9deecd25b1bb272bc42c629d2597] vs 3257628138054444361478105501864864378220055978247423511254865877811522396372018007949352859147340778300746767440474567180060676362720654314518029858055575 [0x3e32f464183b6ad006308d5adbaaffb14c48527b6f25838976052c326c772f30b2eb682f92671f9a2675bad82a7123e605de9deecd25b1bb272bc42c629d2597]) AES key at state StOwnerKey for Attestation Aes
  UVM_INFO @ 761426592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 25.keymgr_sync_async_fault_cross.10199334866787373484486861240796475012666391570801370254390404790152600604933
    Line 302, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 2561792425 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2561792425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

28.keymgr_stress_all.23167478343530118423112465458940535114024611087527390218814786730292354198495
Line 2526, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 867256550 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10300248680735965907103353568057584058495101551627956812226856329716156917460656039148876235795295845366698800649704114334300595828351650770136808527129463 [0xc4aa911994d4295e49c36b95d57d61f30913728fc6bfbbe5357a1b8ddd8cf135ddac14b584fe4919783b9a5e1e30eb267d72ddef5130e875e0a5669f09fe6b77] vs 10300248680735965907103353568057584058495101551627956812226856329716156917460656039148876235795295845366698800649704114334300595828351650770136808527129463 [0xc4aa911994d4295e49c36b95d57d61f30913728fc6bfbbe5357a1b8ddd8cf135ddac14b584fe4919783b9a5e1e30eb267d72ddef5130e875e0a5669f09fe6b77]) AES key at state StOwnerIntKey for Attestation Aes
  UVM_INFO @ 867256550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_if.sv:403) [keymgr_if] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 29.keymgr_custom_cm.52535428480128594294278543762015625595928296422847435038066434193607176133888
    Line 278, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 1150522109 ps: (keymgr_if.sv:403) [keymgr_if] wait timeout occurred!
  UVM_INFO @ 1150522109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 33.keymgr_stress_all.50840403315558905817753696110904441153176171603771464569119968085307170529003
    Line 1493, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 416140020 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3227934308 [0xc0665e64] vs 3227934308 [0xc0665e64]) reg name: keymgr_reg_block.sw_share1_output_7
  UVM_INFO @ 416140020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```