KEYMGR Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.130s	1.339ms	50	50	100.00
V1	random	keymgr_random	1.492m	6.992ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.800s	78.590us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.050s	88.784us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.590s	852.477us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.680s	4.069ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.450s	26.121us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.050s	88.784us	20	20	100.00
		keymgr_csr_aliasing	14.680s	4.069ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.129m	5.066ms	50	50	100.00
V2	sideload	keymgr_sideload	52.330s	15.340ms	49	50	98.00
		keymgr_sideload_kmac	33.310s	1.325ms	50	50	100.00
		keymgr_sideload_aes	39.720s	5.592ms	50	50	100.00
		keymgr_sideload_otbn	43.180s	2.289ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	25.580s	13.527ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	31.440s	1.296ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.920s	440.853us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	54.280s	7.663ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.297m	8.727ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.130s	11.073ms	49	50	98.00
V2	stress_all	keymgr_stress_all	9.897m	40.167ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.320s	49.313us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.690s	62.837us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.890s	118.982us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.890s	118.982us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.800s	78.590us	5	5	100.00
		keymgr_csr_rw	2.050s	88.784us	20	20	100.00
		keymgr_csr_aliasing	14.680s	4.069ms	5	5	100.00
		keymgr_same_csr_outstanding	4.350s	112.714us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.800s	78.590us	5	5	100.00
		keymgr_csr_rw	2.050s	88.784us	20	20	100.00
		keymgr_csr_aliasing	14.680s	4.069ms	5	5	100.00
		keymgr_same_csr_outstanding	4.350s	112.714us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
		keymgr_tl_intg_err	10.260s	722.349us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	9.700s	397.934us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	9.700s	397.934us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	9.700s	397.934us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	9.700s	397.934us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	18.610s	911.798us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.260s	722.349us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	9.700s	397.934us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.129m	5.066ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.492m	6.992ms	50	50	100.00
		keymgr_csr_rw	2.050s	88.784us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.492m	6.992ms	50	50	100.00
		keymgr_csr_rw	2.050s	88.784us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.492m	6.992ms	50	50	100.00
		keymgr_csr_rw	2.050s	88.784us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	31.440s	1.296ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.297m	8.727ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.297m	8.727ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.492m	6.992ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	26.620s	3.719ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	35.250s	5.089ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	31.440s	1.296ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	35.250s	5.089ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	35.250s	5.089ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	35.250s	5.089ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.820s	2.179ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	35.250s	5.089ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.660s	1.525ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1078	1110	97.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	11	68.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.03	98.03	98.57	100.00	99.01	98.63	91.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test keymgr_stress_all_with_rand_reset has 26 failures.
  - 0.keymgr_stress_all_with_rand_reset.41668530298649615868835710409451777166656622531272734784690253222991584980160
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786042053 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 786042053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.93800164377232360201176887666179338029570680684495917790835406348900418287924
    Line 285, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 444200283 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 444200283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 2 failures.

7.keymgr_stress_all.83818062812936239682634291131242160988864079872317071085940320453732469302290
Line 484, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/7.keymgr_stress_all/latest/run.log

  UVM_ERROR @  76403894 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  76403894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.keymgr_stress_all.8458085184201993630184401488296598095734010983853812690344326539449844250947
Line 2014, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/42.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 263823014 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 263823014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload has 1 failures.

37.keymgr_sideload.86484690552436205096429516608696084525348385259070656044855160516918919380603
Line 107, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/37.keymgr_sideload/latest/run.log

  UVM_ERROR @  28529906 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  28529906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

19.keymgr_lc_disable.44680212924543219295080289815688328908753270024400584241869110760290945400812
Line 631, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/19.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 401292998 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12478585185312395347941717657901639664197377036812115743365743949930094899532871591604456755067672244318172039444372114781521800501354918564119253656099154 [0xee420dc835e9aaab28686f6c8d1f560a35c7b493692b9fd2e31b7060fc4e68353bb5398e4913b0beefebda44deb66405212dc1ea12e9a800efa0ad105bf95952] vs 12478585185312395347941717657901639664197377036812115743365743949930094899532871591604456755067672244318172039444372114781521800501354918564119253656099154 [0xee420dc835e9aaab28686f6c8d1f560a35c7b493692b9fd2e31b7060fc4e68353bb5398e4913b0beefebda44deb66405212dc1ea12e9a800efa0ad105bf95952]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @ 401292998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 32.keymgr_kmac_rsp_err.83697540609080779626241617250027099384110609582504336404741517487547162817357
    Line 345, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  51600602 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  51600602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 45.keymgr_sync_async_fault_cross.82088850168508888032944204304455075703940297089962942972514191991347138211731
    Line 142, in log /workspaces/repo/scratch/os_regression_2024_10_02/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 11072952193 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @ 11072952193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```