KEYMGR Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	54.070s	10.344ms	48	50	96.00
V1	random	keymgr_random	1.087m	8.505ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.090s	118.126us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.190s	29.452us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	35.630s	898.509us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.140s	262.841us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.470s	55.472us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.190s	29.452us	20	20	100.00
		keymgr_csr_aliasing	12.140s	262.841us	5	5	100.00
V1		TOTAL			152	155	98.06
V2	cfgen_during_op	keymgr_cfg_regwen	1.651m	8.065ms	50	50	100.00
V2	sideload	keymgr_sideload	39.580s	1.684ms	50	50	100.00
		keymgr_sideload_kmac	41.701s		49	50	98.00
		keymgr_sideload_aes	58.890s	7.097ms	49	50	98.00
		keymgr_sideload_otbn	41.699s		49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	40.977s		49	50	98.00
V2	lc_disable	keymgr_lc_disable	40.928s		47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	41.571s		48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.241m	9.221ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.191m	5.107ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	41.840s		46	50	92.00
V2	stress_all	keymgr_stress_all	3.603m	81.118ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.360s	81.817us	50	50	100.00
V2	alert_test	keymgr_alert_test	41.753s		49	50	98.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	8.010s	538.800us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	8.010s	538.800us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.090s	118.126us	5	5	100.00
		keymgr_csr_rw	2.190s	29.452us	20	20	100.00
		keymgr_csr_aliasing	12.140s	262.841us	5	5	100.00
		keymgr_same_csr_outstanding	6.000s	152.024us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.090s	118.126us	5	5	100.00
		keymgr_csr_rw	2.190s	29.452us	20	20	100.00
		keymgr_csr_aliasing	12.140s	262.841us	5	5	100.00
		keymgr_same_csr_outstanding	6.000s	152.024us	20	20	100.00
V2		TOTAL			724	740	97.84
V2S	sec_cm_additional_check	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
		keymgr_tl_intg_err	12.660s	225.254us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.410s	279.637us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.410s	279.637us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.410s	279.637us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.410s	279.637us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.320s	909.588us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	12.660s	225.254us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.410s	279.637us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.651m	8.065ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.087m	8.505ms	49	50	98.00
		keymgr_csr_rw	2.190s	29.452us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.087m	8.505ms	49	50	98.00
		keymgr_csr_rw	2.190s	29.452us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.087m	8.505ms	49	50	98.00
		keymgr_csr_rw	2.190s	29.452us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	40.928s		47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.191m	5.107ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.191m	5.107ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.087m	8.505ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	42.110s	9.550ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	26.670s	2.557ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	40.928s		47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	26.670s	2.557ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	26.670s	2.557ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	26.670s	2.557ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	34.540s	1.965ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	26.670s	2.557ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	41.743s		26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1067	1110	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	16	16	7	43.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.11	98.39	100.00	99.02	98.63	91.22

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 1.keymgr_stress_all_with_rand_reset.5467944599577872543985721962104151290895527086534481971031297703972756784205
    Line 179, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112424203 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112424203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.105033509678039449814323783077723798906504845235625136373892447268475743608949
    Line 90, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206297383 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 206297383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

Job returned non-zero exit code has 13 failures:

Test keymgr_sync_async_fault_cross has 2 failures.

28.keymgr_sync_async_fault_cross.68537749806113023985059768151715776360230115200060968427629604811618331107805
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:32 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

30.keymgr_sync_async_fault_cross.19920897312314864838412449861969117205029359347304573285047961274760135401437
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:33 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_stress_all_with_rand_reset has 1 failures.

28.keymgr_stress_all_with_rand_reset.28114790742807080509404855299459706508211911757601721701130315251264000515372
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:32 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_alert_test has 1 failures.

28.keymgr_alert_test.17171778548788165298605928658290195155466128794587105830898204629627700715511
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/28.keymgr_alert_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:32 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_smoke has 2 failures.

29.keymgr_smoke.108901426811250911515795458331499285047506494655337075456448489311186282158247
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:32 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

30.keymgr_smoke.81309840253081972157454556336007998626168472572120709606307120002328684842836
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/30.keymgr_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:33 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test keymgr_sideload_kmac has 1 failures.

29.keymgr_sideload_kmac.59860785917824295493693875596091171605582843177757538934276802302772063053536
Log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep  1 13:32 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 6 more tests.

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 6.keymgr_kmac_rsp_err.107025951717705759012538519101273734559037740293666782778872881887647141710817
    Line 483, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @ 116444353 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 116444353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 23.keymgr_sync_async_fault_cross.70538474402578573528237441282218202474588278388718055957639276940033520806573
    Line 118, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  36191185 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  36191185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 2.keymgr_stress_all.22984875144198957633221922459786046854557001998987718739687516417460631337992
    Line 2349, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 4938316080 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
  UVM_INFO @ 4938316080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

3.keymgr_lc_disable.8627173426743033157533751651410660543634303383552160373792075526451451675222
Line 485, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/3.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 195340533 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12999780703654551711544166969337120855772648816917350281937784171458510186630830307929223957812150175163282035548399024666729203029648143023283417482291962 [0xf8359abe0f5457f336e2270031ce6876aba2ad2e3e4bc4ce4592aad42d0645326ff1b522bfba0b6b24aea078f49785fef6913135de9bb8928a5e8da68f0c6afa] vs 12999780703654551711544166969337120855772648816917350281937784171458510186630830307929223957812150175163282035548399024666729203029648143023283417482291962 [0xf8359abe0f5457f336e2270031ce6876aba2ad2e3e4bc4ce4592aad42d0645326ff1b522bfba0b6b24aea078f49785fef6913135de9bb8928a5e8da68f0c6afa]) AES key at state StDisabled for Sealing Aes
  UVM_INFO @ 195340533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 23.keymgr_stress_all_with_rand_reset.21754923886808321664312426030942199939574313876426915452024830501160090631336
    Line 607, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123507352 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_3
  UVM_INFO @ 123507352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 35.keymgr_sync_async_fault_cross.84095917848599222663502173615314208266036818450103837149702558441157420761995
    Line 88, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  72137272 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  72137272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test keymgr_stress_all has 1 failures.

43.keymgr_stress_all.28342630114488119063764089024095047916931560344427381413796536652369403388138
Line 1764, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/43.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 526332813 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (6511336939422381747475922476484863240117891808945456205497492925480947659031245617495348957343119621919898423732331958196924868856673611714148665410146891 [0x7c52c0822745f8872421ce51d3bb6eb487a1d0aff89d8fe9f7704c4d5eddce1bff2dacb09da48471cf5c9225d7b2fc96cf1f65771e38920e844fea002ce3524b] vs 6511336939422381747475922476484863240117891808945456205497492925480947659031245617495348957343119621919898423732331958196924868856673611714148665410146891 [0x7c52c0822745f8872421ce51d3bb6eb487a1d0aff89d8fe9f7704c4d5eddce1bff2dacb09da48471cf5c9225d7b2fc96cf1f65771e38920e844fea002ce3524b]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @ 526332813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:771) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 45.keymgr_stress_all_with_rand_reset.8401386777431632698986324924139390699440701669576498576799509556671108504375
    Line 398, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 192130699 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 192130699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 47.keymgr_stress_all_with_rand_reset.91830725063534347430124839172175631075803051468944147828192678204012620706139
    Line 687, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 183248939 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 183248939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 49.keymgr_lc_disable.95583661815111873815841896738115338276866079929410864318195791939589547373833
    Line 249, in log /workspaces/repo/scratch/os_regression_2024_08_31/keymgr-sim-vcs/49.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  21438482 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @  21438482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```