KEYMGR Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.460s	6.200ms	50	50	100.00
V1	random	keymgr_random	30.510s	1.165ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.720s	480.268us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.680s	30.429us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.620s	903.838us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.420s	7.070ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.960s	68.135us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.680s	30.429us	20	20	100.00
		keymgr_csr_aliasing	15.420s	7.070ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.953m	9.014ms	50	50	100.00
V2	sideload	keymgr_sideload	48.280s	5.219ms	50	50	100.00
		keymgr_sideload_kmac	47.650s	33.180ms	50	50	100.00
		keymgr_sideload_aes	44.710s	3.878ms	50	50	100.00
		keymgr_sideload_otbn	43.780s	7.633ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	41.010s	7.005ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.320s	340.587us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.380s	210.297us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.455m	20.856ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	48.160s	4.395ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	36.110s	3.881ms	49	50	98.00
V2	stress_all	keymgr_stress_all	8.548m	19.088ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.170s	123.953us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.540s	18.083us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.830s	176.763us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.830s	176.763us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.720s	480.268us	5	5	100.00
		keymgr_csr_rw	1.680s	30.429us	20	20	100.00
		keymgr_csr_aliasing	15.420s	7.070ms	5	5	100.00
		keymgr_same_csr_outstanding	4.980s	118.663us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.720s	480.268us	5	5	100.00
		keymgr_csr_rw	1.680s	30.429us	20	20	100.00
		keymgr_csr_aliasing	15.420s	7.070ms	5	5	100.00
		keymgr_same_csr_outstanding	4.980s	118.663us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
		keymgr_tl_intg_err	10.450s	289.635us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.820s	728.176us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.820s	728.176us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.820s	728.176us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.820s	728.176us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	8.660s	323.413us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.450s	289.635us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.820s	728.176us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.953m	9.014ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	30.510s	1.165ms	50	50	100.00
		keymgr_csr_rw	1.680s	30.429us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	30.510s	1.165ms	50	50	100.00
		keymgr_csr_rw	1.680s	30.429us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	30.510s	1.165ms	50	50	100.00
		keymgr_csr_rw	1.680s	30.429us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.320s	340.587us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	48.160s	4.395ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	48.160s	4.395ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	30.510s	1.165ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	36.520s	6.968ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	31.140s	3.484ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.320s	340.587us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	31.140s	3.484ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	31.140s	3.484ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	31.140s	3.484ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	22.200s	847.837us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	31.140s	3.484ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.910s	1.196ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.78	99.03	97.95	98.71	100.00	99.01	98.63	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 5.keymgr_stress_all_with_rand_reset.51346706271060602860422791939976612678841019272559153818793192868618553660864
    Line 220, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 424355351 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 424355351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.keymgr_stress_all_with_rand_reset.54796222295311741828900323637762087061713349695452617955830138763459918947587
    Line 124, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 250835243 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 250835243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sideload_otbn has 1 failures.
  - 21.keymgr_sideload_otbn.56406037500941441078734637046852517412399051930914897338670726891651416394313
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @  19426952 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  19426952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 26.keymgr_stress_all.47960844629447500614189309164185531916394447964822430230427903645284625623225
    Line 2690, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2039091050 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 2039091050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 32.keymgr_stress_all_with_rand_reset.20105211299498940943049044231236768158732835373775037688419145687896308286580
    Line 1088, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 356712983 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 356712983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 3.keymgr_sync_async_fault_cross.110940113346997425983401782411789099410436347415665087874927322751601812372818
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  34510091 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  34510091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

33.keymgr_stress_all.26162290238044444809991049714874734192670823186084642136709378967504184825180
Line 2778, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/33.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 47783341297 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2126733610843243646161491907272989663362716594288750633746653190813917344585937149009212894110644637924072722593241633044885167807561554712319310576129991 [0x289b41e1a2e59775152b5e6f1e2e5dc5a155d31a7ee1571cc70c901a8b806427fc5fad844d10855d4edcda34cc1397e53f774ee250cc584c1330c471cb9297c7] vs 2126733610843243646161491907272989663362716594288750633746653190813917344585937149009212894110644637924072722593241633044885167807561554712319310576129991 [0x289b41e1a2e59775152b5e6f1e2e5dc5a155d31a7ee1571cc70c901a8b806427fc5fad844d10855d4edcda34cc1397e53f774ee250cc584c1330c471cb9297c7]) AES key at state StOwnerIntKey for Attestation Aes
  UVM_INFO @ 47783341297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 49.keymgr_stress_all_with_rand_reset.52154626490418755270108208765880602074874032505800332238431826269523741283840
    Line 1071, in log /workspaces/repo/scratch/os_regression_2024_09_17/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 648193973 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 648193973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```