KEYMGR Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	44.380s	6.612ms	50	50	100.00
V1	random	keymgr_random	51.800s	12.932ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.140s	504.192us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.750s	89.278us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.070s	2.956ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.240s	507.599us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.520s	48.034us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.750s	89.278us	20	20	100.00
		keymgr_csr_aliasing	10.240s	507.599us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.785m	2.150ms	50	50	100.00
V2	sideload	keymgr_sideload	33.630s	6.133ms	50	50	100.00
		keymgr_sideload_kmac	43.590s	3.286ms	50	50	100.00
		keymgr_sideload_aes	1.226m	17.780ms	50	50	100.00
		keymgr_sideload_otbn	43.550s	21.298ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	8.370s	260.582us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	16.100s	247.890us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	13.540s	1.294ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.414m	16.883ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	51.650s	6.112ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.830s	868.901us	48	50	96.00
V2	stress_all	keymgr_stress_all	6.483m	20.038ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.330s	14.645us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.510s	35.123us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.040s	496.671us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.040s	496.671us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.140s	504.192us	5	5	100.00
		keymgr_csr_rw	1.750s	89.278us	20	20	100.00
		keymgr_csr_aliasing	10.240s	507.599us	5	5	100.00
		keymgr_same_csr_outstanding	4.830s	487.260us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.140s	504.192us	5	5	100.00
		keymgr_csr_rw	1.750s	89.278us	20	20	100.00
		keymgr_csr_aliasing	10.240s	507.599us	5	5	100.00
		keymgr_same_csr_outstanding	4.830s	487.260us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
		keymgr_tl_intg_err	10.550s	476.232us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.990s	873.822us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.990s	873.822us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.990s	873.822us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.990s	873.822us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.800s	643.514us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.550s	476.232us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.990s	873.822us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.785m	2.150ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	51.800s	12.932ms	50	50	100.00
		keymgr_csr_rw	1.750s	89.278us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	51.800s	12.932ms	50	50	100.00
		keymgr_csr_rw	1.750s	89.278us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	51.800s	12.932ms	50	50	100.00
		keymgr_csr_rw	1.750s	89.278us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.100s	247.890us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	51.650s	6.112ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	51.650s	6.112ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	51.800s	12.932ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.290s	1.676ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.500s	171.761us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.100s	247.890us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.500s	171.761us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.500s	171.761us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.500s	171.761us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.580s	1.031ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.500s	171.761us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	33.600s	5.876ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1083	1110	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.07	98.43	100.00	99.02	98.63	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 1.keymgr_stress_all_with_rand_reset.56859039456970716095926622824687669707276616376135109435089393988599149990520
    Line 1544, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3327213571 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3327213571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.37704171121521774655399232170518857583079292537693071232862355269197648533002
    Line 159, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 483341366 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 483341366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 7.keymgr_stress_all_with_rand_reset.4302083565668329063787575824444013274202677413231627999392432023443241875269
    Line 587, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 556680160 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 556680160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.keymgr_stress_all_with_rand_reset.105225455915165990519402362611023122319054628402979929617326352967498754555212
    Line 193, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 481305064 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 481305064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 40.keymgr_sync_async_fault_cross.40098091525817742178045132274429061214871186875643617525211632240894137540060
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  10792655 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  10792655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_otbn has 1 failures.
  - 41.keymgr_sideload_otbn.97179014220366877774539757157670635278285140158321782290569053172886122951582
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @  17592082 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  17592082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

3.keymgr_stress_all.56157491606674889252540266241831915904358533104916637036303972436211471944947
Line 545, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 3057991270 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12393203219859155752947868214747048869491546811517988434512825078498524160267242441598578544561198959645119132747003513747717006957785186704508781527545372 [0xeca0b729dd226d2fa0ef69de7755ef029fbdb3100cf518fcb6fd73c577083feaf23599b74c05bbfed172ca49d535324aef6623ea2a16543a790328dbe45fb61c] vs 12393203219859155752947868214747048869491546811517988434512825078498524160267242441598578544561198959645119132747003513747717006957785186704508781527545372 [0xeca0b729dd226d2fa0ef69de7755ef029fbdb3100cf518fcb6fd73c577083feaf23599b74c05bbfed172ca49d535324aef6623ea2a16543a790328dbe45fb61c]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @ 3057991270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 10.keymgr_sync_async_fault_cross.86538357998807074228741684468728188694392317939537329155585641457708408896279
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  71853908 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  71853908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 19.keymgr_hwsw_invalid_input.11905616124098822050736391081351410272938509510116198600693365668957972317901
    Line 321, in log /workspaces/repo/scratch/os_regression_2024_09_03/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  23911207 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  23911207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```