KEYMGR Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	30.990s	1.315ms	50	50	100.00
V1	random	keymgr_random	1.116m	7.781ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.490s	18.550us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.920s	118.653us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.570s	577.458us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.390s	4.915ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.460s	92.679us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.920s	118.653us	20	20	100.00
		keymgr_csr_aliasing	14.390s	4.915ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.261m	2.586ms	50	50	100.00
V2	sideload	keymgr_sideload	1.142m	6.336ms	50	50	100.00
		keymgr_sideload_kmac	1.017m	3.342ms	50	50	100.00
		keymgr_sideload_aes	1.122m	4.183ms	50	50	100.00
		keymgr_sideload_otbn	51.980s	1.297ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.310s	5.548ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	10.890s	203.142us	47	50	94.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.440s	189.089us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	43.080s	2.180ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	42.270s	1.152ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	31.410s	4.665ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.520m	28.635ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.140s	24.317us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.290s	20.330us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.830s	724.649us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.830s	724.649us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.490s	18.550us	5	5	100.00
		keymgr_csr_rw	1.920s	118.653us	20	20	100.00
		keymgr_csr_aliasing	14.390s	4.915ms	5	5	100.00
		keymgr_same_csr_outstanding	5.080s	2.438ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.490s	18.550us	5	5	100.00
		keymgr_csr_rw	1.920s	118.653us	20	20	100.00
		keymgr_csr_aliasing	14.390s	4.915ms	5	5	100.00
		keymgr_same_csr_outstanding	5.080s	2.438ms	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
		keymgr_tl_intg_err	11.990s	987.146us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.220s	942.391us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.220s	942.391us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.220s	942.391us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.220s	942.391us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.460s	801.683us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.990s	987.146us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.220s	942.391us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.261m	2.586ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.116m	7.781ms	50	50	100.00
		keymgr_csr_rw	1.920s	118.653us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.116m	7.781ms	50	50	100.00
		keymgr_csr_rw	1.920s	118.653us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.116m	7.781ms	50	50	100.00
		keymgr_csr_rw	1.920s	118.653us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	10.890s	203.142us	47	50	94.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	42.270s	1.152ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	42.270s	1.152ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.116m	7.781ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	31.170s	2.763ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	35.330s	2.031ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	10.890s	203.142us	47	50	94.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	35.330s	2.031ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	35.330s	2.031ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	35.330s	2.031ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.060s	443.939us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	35.330s	2.031ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	48.650s	3.465ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1085	1110	97.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.04	98.15	98.28	100.00	99.02	98.63	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 2.keymgr_stress_all_with_rand_reset.102485936466485267206031344281845216408059839444937857554632885144082363880807
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137517228 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10007 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137517228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.39584917361338354221017284562731128182067481824866200858861608244886493762835
    Line 1514, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1043843396 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1043843396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_lc_disable has 1 failures.
  - 27.keymgr_lc_disable.6579047230834680893285197112334939714673780755886846360666172702921683904525
    Line 360, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/27.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  28627514 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  28627514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 39.keymgr_stress_all.5202995127162857463314412642872113960670124820162669732482419355437206539050
    Line 1890, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1469102577 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 1469102577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 22.keymgr_kmac_rsp_err.33676388708002808356374526904357011903101714374080866345460632687331007766105
    Line 290, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  40085060 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  40085060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

28.keymgr_lc_disable.42320712475482385747763438345461364626883619448611358608398699286044116937516
Line 443, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/28.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 103638452 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (8205808939546802413798746388043210853137698154244539887955492546408008699456179260171653677053155763005346769656014934185645410546185761870893376206292727 [0x9cad2899a085eaa2614a070bfa324b14ba64c8486035167b2fc651af2a61b1ef536c9675966c7ce3e158892ee71d83e71825446df6883bae9416561e01e846f7] vs 8205808939546802413798746388043210853137698154244539887955492546408008699456179260171653677053155763005346769656014934185645410546185761870893376206292727 [0x9cad2899a085eaa2614a070bfa324b14ba64c8486035167b2fc651af2a61b1ef536c9675966c7ce3e158892ee71d83e71825446df6883bae9416561e01e846f7]) AES key at state StOwnerKey for Sealing Aes
  UVM_INFO @ 103638452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

42.keymgr_lc_disable.109069709238945053623827380774602827420856201663076076642605355815554625935651
Line 450, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/42.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 101242472 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (5939033548708202665612055143171330710133376494230555746164931931099009029785107251231286464404359228004374699707324882918432016477059592166256239305656445 [0x7165642b2291eb9e8eedf511cb65455d488798a3f201f226a83c7ab9fed39dfbbef6c67562d74a1750919c108d1f1e9ece479ccc0035c356a0270c1418a1887d] vs 5939033548708202665612055143171330710133376494230555746164931931099009029785107251231286464404359228004374699707324882918432016477059592166256239305656445 [0x7165642b2291eb9e8eedf511cb65455d488798a3f201f226a83c7ab9fed39dfbbef6c67562d74a1750919c108d1f1e9ece479ccc0035c356a0270c1418a1887d]) AES key at state StDisabled for Sealing Aes
  UVM_INFO @ 101242472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 47.keymgr_stress_all.46998052808331490027189752313379261584313558282747020551919543870631380927066
    Line 2928, in log /workspaces/repo/scratch/os_regression_2024_09_10/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 28634776988 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (3 [0x3] vs 6 [0x6])
  UVM_INFO @ 28634776988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```