KEYMGR Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	46.510s	5.556ms	50	50	100.00
V1	random	keymgr_random	43.130s	3.255ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.220s	43.241us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.300s	61.411us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	40.650s	5.117ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	22.370s	3.954ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.570s	62.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.300s	61.411us	20	20	100.00
		keymgr_csr_aliasing	22.370s	3.954ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.949m	2.219ms	50	50	100.00
V2	sideload	keymgr_sideload	38.370s	5.350ms	50	50	100.00
		keymgr_sideload_kmac	1.049m	5.485ms	50	50	100.00
		keymgr_sideload_aes	43.730s	6.276ms	50	50	100.00
		keymgr_sideload_otbn	1.154m	19.202ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	37.440s	8.046ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	12.250s	1.949ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.970s	1.193ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.295m	30.842ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	38.060s	7.313ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.070s	1.580ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.438m	21.781ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.410s	13.281us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.490s	71.896us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.510s	168.790us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.510s	168.790us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.220s	43.241us	5	5	100.00
		keymgr_csr_rw	2.300s	61.411us	20	20	100.00
		keymgr_csr_aliasing	22.370s	3.954ms	5	5	100.00
		keymgr_same_csr_outstanding	4.970s	94.082us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.220s	43.241us	5	5	100.00
		keymgr_csr_rw	2.300s	61.411us	20	20	100.00
		keymgr_csr_aliasing	22.370s	3.954ms	5	5	100.00
		keymgr_same_csr_outstanding	4.970s	94.082us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
		keymgr_tl_intg_err	10.760s	258.641us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	8.920s	232.115us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	8.920s	232.115us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	8.920s	232.115us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	8.920s	232.115us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	17.720s	2.728ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.760s	258.641us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	8.920s	232.115us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.949m	2.219ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	43.130s	3.255ms	50	50	100.00
		keymgr_csr_rw	2.300s	61.411us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	43.130s	3.255ms	50	50	100.00
		keymgr_csr_rw	2.300s	61.411us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	43.130s	3.255ms	50	50	100.00
		keymgr_csr_rw	2.300s	61.411us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	12.250s	1.949ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	38.060s	7.313ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	38.060s	7.313ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	43.130s	3.255ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	41.050s	2.531ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	12.070s	935.025us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	12.250s	1.949ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	12.070s	935.025us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	12.070s	935.025us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	12.070s	935.025us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.060s	895.641us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	12.070s	935.025us	50	50	100.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	40.420s	1.769ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1091	1110	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.03	97.99	98.30	100.00	99.01	98.63	91.22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:

  • Test keymgr_stress_all_with_rand_reset has 15 failures.

    • 4.keymgr_stress_all_with_rand_reset.95312676084155444485257584583507297203086047787531016609786661953033365018335
      Line 280, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 131786947 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 131786947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.keymgr_stress_all_with_rand_reset.15284395498845756722504184362262215546299022155098087602946982687534985884725
      Line 272, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 181663247 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 181663247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 13 more failures.

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:

  • Test keymgr_stress_all has 1 failures.

    • 28.keymgr_stress_all.78339271729853533158064297747866917211045957075517164147575028761939576655547
      Line 3474, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/28.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 991475184 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (746581276 [0x2c7fed1c] vs 746581276 [0x2c7fed1c]) reg name: keymgr_reg_block.sw_share1_output_1
        UVM_INFO @ 991475184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 32.keymgr_stress_all_with_rand_reset.93516214436305247417463474453006332499650308181305278615303571179357237475712
      Line 927, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1080053654 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (52339422 [0x31ea2de] vs 52339422 [0x31ea2de]) reg name: keymgr_reg_block.sw_share1_output_5
        UVM_INFO @ 1080053654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 48.keymgr_kmac_rsp_err.28923235880607926916364800234346508987462411302853435997169265539324304698460
      Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @   4997740 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   4997740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_protect has 1 failures.

    • 49.keymgr_sideload_protect.90402710721855971665049353452642382644012577188278617668977600885113648231128
      Line 129, in log /workspaces/repo/scratch/os_regression_2024_10_08/keymgr-sim-vcs/49.keymgr_sideload_protect/latest/run.log

        UVM_ERROR @  10490023 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  10490023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.04_00.41.32
• 2024.09.25_11.00.32
• 2024.09.19_09.04.18
• 2024.09.12_10.15.57
• 2024.09.10_08.10.49
• 2024.09.05_04.20.21