KEYMGR Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 29.280s 8.089ms 48 50 96.00
V1 random keymgr_random 31.850s 1.345ms 49 50 98.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.970s 43.333us 5 5 100.00
V1 csr_rw keymgr_csr_rw 2.020s 56.986us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 18.030s 4.304ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 9.990s 772.009us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 3.110s 105.287us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 2.020s 56.986us 20 20 100.00
keymgr_csr_aliasing 9.990s 772.009us 5 5 100.00
V1 TOTAL 152 155 98.06
V2 cfgen_during_op keymgr_cfg_regwen 1.645m 8.982ms 49 50 98.00
V2 sideload keymgr_sideload 40.330s 7.201ms 49 50 98.00
keymgr_sideload_kmac 25.096s 47 50 94.00
keymgr_sideload_aes 33.610s 1.472ms 48 50 96.00
keymgr_sideload_otbn 50.050s 14.611ms 48 50 96.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 43.990s 2.896ms 49 50 98.00
V2 lc_disable keymgr_lc_disable 18.270s 2.982ms 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 6.420s 584.622us 50 50 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.109m 25.901ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 24.930s 1.923ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 13.380s 2.047ms 50 50 100.00
V2 stress_all keymgr_stress_all 8.877m 57.899ms 48 50 96.00
V2 intr_test keymgr_intr_test 1.370s 16.484us 50 50 100.00
V2 alert_test keymgr_alert_test 26.903s 48 50 96.00
V2 tl_d_oob_addr_access keymgr_tl_errors 6.960s 271.411us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 6.960s 271.411us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.970s 43.333us 5 5 100.00
keymgr_csr_rw 2.020s 56.986us 20 20 100.00
keymgr_csr_aliasing 9.990s 772.009us 5 5 100.00
keymgr_same_csr_outstanding 5.880s 441.183us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.970s 43.333us 5 5 100.00
keymgr_csr_rw 2.020s 56.986us 20 20 100.00
keymgr_csr_aliasing 9.990s 772.009us 5 5 100.00
keymgr_same_csr_outstanding 5.880s 441.183us 20 20 100.00
V2 TOTAL 725 740 97.97
V2S sec_cm_additional_check keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
keymgr_tl_intg_err 13.300s 324.709us 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 5.480s 194.012us 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 5.480s 194.012us 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 5.480s 194.012us 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 5.480s 194.012us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 17.870s 409.773us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 13.300s 324.709us 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 5.480s 194.012us 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.645m 8.982ms 49 50 98.00
V2S sec_cm_reseed_config_regwen keymgr_random 31.850s 1.345ms 49 50 98.00
keymgr_csr_rw 2.020s 56.986us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 31.850s 1.345ms 49 50 98.00
keymgr_csr_rw 2.020s 56.986us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 31.850s 1.345ms 49 50 98.00
keymgr_csr_rw 2.020s 56.986us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 18.270s 2.982ms 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 24.930s 1.923ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 24.930s 1.923ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 31.850s 1.345ms 49 50 98.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 25.770s 3.246ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 37.500s 2.543ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 18.270s 2.982ms 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 37.500s 2.543ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 37.500s 2.543ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 37.500s 2.543ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 13.490s 2.266ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 37.500s 2.543ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 23.590s 543.635us 35 50 70.00
V3 TOTAL 35 50 70.00
TOTAL 1077 1110 97.03

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 16 16 7 43.75
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.74 99.03 97.75 98.53 100.00 99.01 98.63 91.19

Failure Buckets

Past Results