8a1401d614| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 29.280s | 8.089ms | 48 | 50 | 96.00 |
| V1 | random | keymgr_random | 31.850s | 1.345ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.970s | 43.333us | 5 | 5 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 18.030s | 4.304ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 9.990s | 772.009us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 3.110s | 105.287us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 |
| keymgr_csr_aliasing | 9.990s | 772.009us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 152 | 155 | 98.06 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 1.645m | 8.982ms | 49 | 50 | 98.00 |
| V2 | sideload | keymgr_sideload | 40.330s | 7.201ms | 49 | 50 | 98.00 |
| keymgr_sideload_kmac | 25.096s | 47 | 50 | 94.00 | |||
| keymgr_sideload_aes | 33.610s | 1.472ms | 48 | 50 | 96.00 | ||
| keymgr_sideload_otbn | 50.050s | 14.611ms | 48 | 50 | 96.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 43.990s | 2.896ms | 49 | 50 | 98.00 |
| V2 | lc_disable | keymgr_lc_disable | 18.270s | 2.982ms | 49 | 50 | 98.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 6.420s | 584.622us | 50 | 50 | 100.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.109m | 25.901ms | 50 | 50 | 100.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 24.930s | 1.923ms | 50 | 50 | 100.00 |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 13.380s | 2.047ms | 50 | 50 | 100.00 |
| V2 | stress_all | keymgr_stress_all | 8.877m | 57.899ms | 48 | 50 | 96.00 |
| V2 | intr_test | keymgr_intr_test | 1.370s | 16.484us | 50 | 50 | 100.00 |
| V2 | alert_test | keymgr_alert_test | 26.903s | 48 | 50 | 96.00 | |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 6.960s | 271.411us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 6.960s | 271.411us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.970s | 43.333us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 | ||
| keymgr_csr_aliasing | 9.990s | 772.009us | 5 | 5 | 100.00 | ||
| keymgr_same_csr_outstanding | 5.880s | 441.183us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.970s | 43.333us | 5 | 5 | 100.00 |
| keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 | ||
| keymgr_csr_aliasing | 9.990s | 772.009us | 5 | 5 | 100.00 | ||
| keymgr_same_csr_outstanding | 5.880s | 441.183us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 725 | 740 | 97.97 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| keymgr_tl_intg_err | 13.300s | 324.709us | 20 | 20 | 100.00 | ||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.480s | 194.012us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.480s | 194.012us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.480s | 194.012us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.480s | 194.012us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 17.870s | 409.773us | 20 | 20 | 100.00 |
| V2S | prim_count_check | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 13.300s | 324.709us | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.480s | 194.012us | 20 | 20 | 100.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.645m | 8.982ms | 49 | 50 | 98.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 31.850s | 1.345ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 31.850s | 1.345ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 31.850s | 1.345ms | 49 | 50 | 98.00 |
| keymgr_csr_rw | 2.020s | 56.986us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 18.270s | 2.982ms | 49 | 50 | 98.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 24.930s | 1.923ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 24.930s | 1.923ms | 50 | 50 | 100.00 |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 31.850s | 1.345ms | 49 | 50 | 98.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 25.770s | 3.246ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 37.500s | 2.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 18.270s | 2.982ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 37.500s | 2.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 37.500s | 2.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 37.500s | 2.543ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 13.490s | 2.266ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 37.500s | 2.543ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 165 | 165 | 100.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 23.590s | 543.635us | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 1077 | 1110 | 97.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 16 | 16 | 7 | 43.75 |
| V2S | 6 | 6 | 6 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.74 | 99.03 | 97.75 | 98.53 | 100.00 | 99.01 | 98.63 | 91.19 |
UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.keymgr_stress_all_with_rand_reset.63029407096279920706015103218883273401879882687613925602011823711624338310498
Line 355, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 160503960 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 160503960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.9353421898683364429074400319844432202687015049000076007354977247745495463358
Line 818, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1312455552 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1312455552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Job returned non-zero exit code has 14 failures:
Test keymgr_sideload_kmac has 2 failures.
17.keymgr_sideload_kmac.79381726221921666925774968326685501247343665494824832136505718109850143359466
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:34 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
44.keymgr_sideload_kmac.59967774753762996977943606082033158992838937631823734213412052295611100495901
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test keymgr_sideload_aes has 2 failures.
17.keymgr_sideload_aes.63092109503078498886336872289044933494053253868462535311627167317543810475026
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sideload_aes/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:34 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
44.keymgr_sideload_aes.78887250484800755116058921583147445857664244988259823904862847711451801959780
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sideload_aes/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test keymgr_sideload_otbn has 2 failures.
17.keymgr_sideload_otbn.25229444960804555400772053129481897199466246083294777885208083597042266493781
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:34 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
44.keymgr_sideload_otbn.75489624628193768948499301840769561130805635117447454220122157952678669051418
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test keymgr_alert_test has 2 failures.
37.keymgr_alert_test.80645311771599995711401474705838493326484030974399221775075985424989574218675
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/37.keymgr_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
43.keymgr_alert_test.98291414126322452410182127203074139684420253149048548074736591307416277450945
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/43.keymgr_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test keymgr_smoke has 2 failures.
38.keymgr_smoke.8393089873061218726047858586969004904558802464839786014614893650751316646084
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/38.keymgr_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
44.keymgr_smoke.32949208255380111009191474400116401825714402449941646868920073905414272380540
Log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/44.keymgr_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Oct 12 02:36 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 4 more tests.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
Test keymgr_stress_all has 2 failures.
19.keymgr_stress_all.112268984350352459315707103388945115797372034636975969812384989156780151548701
Line 3541, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/19.keymgr_stress_all/latest/run.log
UVM_ERROR @ 980458766 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 980458766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.keymgr_stress_all.106260342737580736395220827368932827935753593501261839469608165473468056910570
Line 908, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/30.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1144752473 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1144752473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_sideload_kmac has 1 failures.
36.keymgr_sideload_kmac.59015210182882732305295445110815643706862911505731707344976822932366576799945
Line 77, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest/run.log
UVM_ERROR @ 4660267 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 4660267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
1.keymgr_lc_disable.110418718187160130004831239075189140310053878339042237287233714942415334010351
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/1.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 28645952 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
UVM_INFO @ 28645952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
16.keymgr_stress_all_with_rand_reset.38769954216915680357857260060575517101085200269172526407416865031512160493091
Line 774, in log /workspaces/repo/scratch/os_regression_2024_10_11/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 517874035 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 517874035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---