KMAC/MASKED Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.542m 14.688ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.150s 35.243us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.220s 134.044us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 23.800s 3.167ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 8.850s 164.587us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.420s 31.775us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.220s 134.044us 20 20 100.00
kmac_csr_aliasing 8.850s 164.587us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.810s 19.906us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.470s 37.374us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 54.328m 127.719ms 50 50 100.00
V2 burst_write kmac_burst_write 27.564m 15.338ms 48 50 96.00
V2 test_vectors kmac_test_vectors_sha3_224 42.434m 138.372ms 50 50 100.00
kmac_test_vectors_sha3_256 42.015m 234.404ms 50 50 100.00
kmac_test_vectors_sha3_384 34.884m 713.094ms 50 50 100.00
kmac_test_vectors_sha3_512 23.793m 197.489ms 50 50 100.00
kmac_test_vectors_shake_128 1.842h 403.662ms 48 50 96.00
kmac_test_vectors_shake_256 1.568h 2.477s 50 50 100.00
kmac_test_vectors_kmac 7.350s 677.185us 50 50 100.00
kmac_test_vectors_kmac_xof 9.740s 1.879ms 50 50 100.00
V2 sideload kmac_sideload 9.197m 12.387ms 49 50 98.00
V2 app kmac_app 7.600m 6.752ms 48 50 96.00
V2 app_with_partial_data kmac_app_with_partial_data 6.595m 30.749ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 7.474m 40.059ms 50 50 100.00
V2 error kmac_error 9.035m 16.372ms 50 50 100.00
V2 key_error kmac_key_error 7.350s 5.746ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 50.470s 2.427ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 29.480s 1.290ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.011m 6.499ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 42.090s 859.069us 50 50 100.00
V2 stress_all kmac_stress_all 47.255m 102.359ms 48 50 96.00
V2 intr_test kmac_intr_test 0.870s 24.493us 50 50 100.00
V2 alert_test kmac_alert_test 0.930s 38.262us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.720s 507.497us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.720s 507.497us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.150s 35.243us 5 5 100.00
kmac_csr_rw 1.220s 134.044us 20 20 100.00
kmac_csr_aliasing 8.850s 164.587us 5 5 100.00
kmac_same_csr_outstanding 3.060s 948.531us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.150s 35.243us 5 5 100.00
kmac_csr_rw 1.220s 134.044us 20 20 100.00
kmac_csr_aliasing 8.850s 164.587us 5 5 100.00
kmac_same_csr_outstanding 3.060s 948.531us 20 20 100.00
V2 TOTAL 1041 1050 99.14
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.270s 526.487us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.270s 526.487us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.270s 526.487us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.270s 526.487us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 5.160s 241.775us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 2.246m 9.372ms 5 5 100.00
kmac_tl_intg_err 5.780s 515.163us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.780s 515.163us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 42.090s 859.069us 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.542m 14.688ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 9.197m 12.387ms 49 50 98.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.270s 526.487us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 2.246m 9.372ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 2.246m 9.372ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 2.246m 9.372ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.542m 14.688ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 42.090s 859.069us 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 2.246m 9.372ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 7.140m 96.280ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.542m 14.688ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 51.522m 114.947ms 38 50 76.00
V3 TOTAL 38 50 76.00
TOTAL 1269 1290 98.37

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 20 80.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.06 98.40 93.36 99.93 94.55 96.03 98.87 98.31

Failure Buckets

Past Results