e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.542m | 14.688ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.150s | 35.243us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.220s | 134.044us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 23.800s | 3.167ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 8.850s | 164.587us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.420s | 31.775us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.220s | 134.044us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 8.850s | 164.587us | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.810s | 19.906us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.470s | 37.374us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 54.328m | 127.719ms | 50 | 50 | 100.00 |
V2 | burst_write | kmac_burst_write | 27.564m | 15.338ms | 48 | 50 | 96.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 42.434m | 138.372ms | 50 | 50 | 100.00 |
kmac_test_vectors_sha3_256 | 42.015m | 234.404ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_384 | 34.884m | 713.094ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 23.793m | 197.489ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.842h | 403.662ms | 48 | 50 | 96.00 | ||
kmac_test_vectors_shake_256 | 1.568h | 2.477s | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac | 7.350s | 677.185us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 9.740s | 1.879ms | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 9.197m | 12.387ms | 49 | 50 | 98.00 |
V2 | app | kmac_app | 7.600m | 6.752ms | 48 | 50 | 96.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 6.595m | 30.749ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 7.474m | 40.059ms | 50 | 50 | 100.00 |
V2 | error | kmac_error | 9.035m | 16.372ms | 50 | 50 | 100.00 |
V2 | key_error | kmac_key_error | 7.350s | 5.746ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 50.470s | 2.427ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 29.480s | 1.290ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 1.011m | 6.499ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 42.090s | 859.069us | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 47.255m | 102.359ms | 48 | 50 | 96.00 |
V2 | intr_test | kmac_intr_test | 0.870s | 24.493us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.930s | 38.262us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.720s | 507.497us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.720s | 507.497us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.150s | 35.243us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.220s | 134.044us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 8.850s | 164.587us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.060s | 948.531us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.150s | 35.243us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.220s | 134.044us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 8.850s | 164.587us | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 3.060s | 948.531us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1041 | 1050 | 99.14 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.270s | 526.487us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.270s | 526.487us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.270s | 526.487us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.270s | 526.487us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 5.160s | 241.775us | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 2.246m | 9.372ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.780s | 515.163us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.780s | 515.163us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 42.090s | 859.069us | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.542m | 14.688ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 9.197m | 12.387ms | 49 | 50 | 98.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.270s | 526.487us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.246m | 9.372ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.246m | 9.372ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.246m | 9.372ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.542m | 14.688ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 42.090s | 859.069us | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.246m | 9.372ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.140m | 96.280ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.542m | 14.688ms | 50 | 50 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 51.522m | 114.947ms | 38 | 50 | 76.00 |
V3 | TOTAL | 38 | 50 | 76.00 | |||
TOTAL | 1269 | 1290 | 98.37 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 20 | 80.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.06 | 98.40 | 93.36 | 99.93 | 94.55 | 96.03 | 98.87 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 8 failures:
5.kmac_stress_all_with_rand_reset.769001775
Line 458, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 133563867617 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
UVM_INFO @ 133563867617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.kmac_stress_all_with_rand_reset.1830785561
Line 438, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7814817464 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 7814817464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request
has 4 failures:
2.kmac_stress_all_with_rand_reset.1083448891
Line 928, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 205340644381 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 205340644381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.kmac_stress_all_with_rand_reset.1408529021
Line 822, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 44240465899 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 44240465899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 4 failures:
Test kmac_test_vectors_shake_128 has 2 failures.
7.kmac_test_vectors_shake_128.4289135765
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 27958692 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 27958692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.kmac_test_vectors_shake_128.1246727707
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 101009488 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 101009488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_sideload has 1 failures.
24.kmac_sideload.2984311045
Line 243, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_sideload/latest/run.log
UVM_ERROR @ 234137965 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 234137965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
25.kmac_stress_all.1817459527
Line 282, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log
UVM_ERROR @ 7752550217 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 7752550217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 3 failures:
Test kmac_burst_write has 2 failures.
1.kmac_burst_write.858423210
Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.kmac_burst_write.3881155687
Line 375, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
27.kmac_app.1940574179
Line 384, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_app/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 2 failures:
Test kmac_app has 1 failures.
3.kmac_app.221583684
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app/latest/run.log
UVM_FATAL @ 1663959204 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (186 [0xba] vs 68 [0x44]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1663959204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
32.kmac_stress_all.3780550216
Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest/run.log
UVM_FATAL @ 24568575892 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 24568575892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---