748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.561m | 8.305ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.140s | 57.710us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.250s | 35.345us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.530s | 3.981ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.750s | 684.234us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.100s | 55.778us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 35.345us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.750s | 684.234us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.770s | 31.211us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.460s | 75.953us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 56.675m | 1.099s | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 29.798m | 187.883ms | 49 | 50 | 98.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 46.080m | 1.350s | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 41.976m | 887.183ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 35.081m | 1.169s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 24.451m | 61.589ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.969h | 5.000s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_256 | 1.516h | 2.140s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 8.980s | 902.686us | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 7.220s | 3.185ms | 49 | 50 | 98.00 | ||
| V2 | sideload | kmac_sideload | 8.787m | 123.947ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.085m | 36.234ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.719m | 18.891ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.896m | 16.148ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 8.573m | 76.129ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 10.940s | 10.569ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 56.080s | 2.601ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 48.670s | 4.483ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.366m | 8.094ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 38.930s | 1.697ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 1.037h | 540.645ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.840s | 19.721us | 44 | 50 | 88.00 |
| V2 | alert_test | kmac_alert_test | 0.990s | 198.676us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.580s | 503.411us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.580s | 503.411us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.140s | 57.710us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 35.345us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.750s | 684.234us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.790s | 487.937us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.140s | 57.710us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 35.345us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.750s | 684.234us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.790s | 487.937us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1036 | 1050 | 98.67 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.490s | 139.073us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.490s | 139.073us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.490s | 139.073us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.490s | 139.073us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.120s | 475.166us | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.978m | 29.583ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.740s | 279.554us | 19 | 20 | 95.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.740s | 279.554us | 19 | 20 | 95.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 38.930s | 1.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.561m | 8.305ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.787m | 123.947ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.490s | 139.073us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.978m | 29.583ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.978m | 29.583ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.978m | 29.583ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.561m | 8.305ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 38.930s | 1.697ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.978m | 29.583ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.369m | 143.793ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.561m | 8.305ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 73 | 75 | 97.33 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.007h | 224.360ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 1258 | 1290 | 97.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 16 | 64.00 |
| V2S | 5 | 5 | 3 | 60.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.77 | 98.38 | 93.15 | 99.93 | 92.73 | 96.04 | 98.89 | 98.31 |
UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 13 failures:
0.kmac_stress_all_with_rand_reset.90676552711201920402686801017926759842657156554687750283485181938088382084971
Line 492, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34382881373 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 34382881373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.kmac_stress_all_with_rand_reset.8192529269393543699442798576652081642259148634926405422953383972211485289253
Line 486, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18621463310 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
UVM_INFO @ 18621463310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 9 failures:
Test kmac_same_csr_outstanding has 1 failures.
9.kmac_same_csr_outstanding.108477408818907483316417046091687732753148233372296114064789110433477654401552
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/9.kmac_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807064080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.807064080 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_csr_mem_rw_with_rand_reset has 1 failures.
12.kmac_csr_mem_rw_with_rand_reset.103260078557288477622942259825379584210827450100629027116683347955386162439600
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.20014512 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test kmac_intr_test has 6 failures.
14.kmac_intr_test.113518555234452348847867145727908347720100420500183757250860364648221393855597
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/14.kmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243811949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.3243811949 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
20.kmac_intr_test.13720257742402052302390153245206087540794914591854650685297186712047153424870
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/20.kmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097261030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2097261030 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
Test kmac_tl_intg_err has 1 failures.
16.kmac_tl_intg_err.48758190231190016796534350985595289595858431871264042536892755919302713628986
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/16.kmac_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525714746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2525714746 +enable_masking=1 +sw_key_masked=0
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:44 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
Test kmac_test_vectors_kmac has 1 failures.
3.kmac_test_vectors_kmac.17267369153612158125781531029513599557577059056897462574365775750424320593716
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 63462469 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 63462469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
19.kmac_test_vectors_shake_256.18815253166827195814368154916711967924250612469869599816997317967931108881200
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 99764400 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 99764400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac_xof has 1 failures.
20.kmac_test_vectors_kmac_xof.25593454834415767978656799758894141385817912695099497429789822102563081597421
Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_kmac_xof/latest/run.log
UVM_ERROR @ 81699049 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 81699049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test kmac_entropy_refresh has 1 failures.
12.kmac_entropy_refresh.27663059290095866835198077862807129042351657085583848774492660399892554576313
Line 384, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
39.kmac_test_vectors_shake_128.30787309309871250173824924174351274758158899730316444203173812202732897463882
Line 2006, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_shake_128/latest/run.log
UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_burst_write has 1 failures.
49.kmac_burst_write.85219376964908884220756602478369854628022781177892359493953114338106818078053
Line 404, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
32.kmac_stress_all_with_rand_reset.113298376543710309723955238921931578438060456703216706515632786038597171838694
Line 666, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 47707026792 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 47707026792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.kmac_stress_all_with_rand_reset.51363623308244898270173205597405068131179752796796495619886931781504757478374
Line 1221, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 62739202416 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 62739202416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
15.kmac_stress_all.42047471280387270174059798714475700429918319233435833462839468474046803602984
Line 455, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all/latest/run.log
UVM_FATAL @ 37558377522 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (209 [0xd1] vs 0 [0x0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 37558377522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
18.kmac_shadow_reg_errors_with_csr_rw.5285061984329811762794865932306315209406418265285114826731104545135225084620
Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 18443369 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (3523966604 [0xd20b768c] vs 3545253544 [0xd35046a8]) Regname: kmac_reg_block.prefix_8 reset value: 0x0
UVM_INFO @ 18443369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---