KMAC/MASKED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.394m	4.610ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	208.583us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.250s	108.627us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.930s	5.950ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.210s	474.383us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.760s	1.318ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.250s	108.627us	20	20	100.00
		kmac_csr_aliasing	9.210s	474.383us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	84.091us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.620s	38.156us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	51.709m	180.561ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.005m	64.809ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.265m	99.382ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.820m	880.997ms	49	50	98.00
		kmac_test_vectors_sha3_384	32.504m	1.160s	50	50	100.00
		kmac_test_vectors_sha3_512	23.529m	211.834ms	50	50	100.00
		kmac_test_vectors_shake_128	1.774h	1.867s	49	50	98.00
		kmac_test_vectors_shake_256	1.478h	280.665ms	49	50	98.00
		kmac_test_vectors_kmac	7.750s	4.507ms	49	50	98.00
		kmac_test_vectors_kmac_xof	7.190s	347.557us	50	50	100.00
V2	sideload	kmac_sideload	9.278m	21.838ms	50	50	100.00
V2	app	kmac_app	6.374m	5.115ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.847m	51.542ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.280m	38.188ms	48	50	96.00
V2	error	kmac_error	8.316m	19.732ms	49	50	98.00
V2	key_error	kmac_key_error	8.980s	12.629ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.710s	11.775ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.980s	8.912ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.051m	5.696ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.112m	1.069ms	50	50	100.00
V2	stress_all	kmac_stress_all	49.826m	200.432ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.910s	26.077us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	88.116us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.170s	560.494us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.170s	560.494us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	208.583us	5	5	100.00
		kmac_csr_rw	1.250s	108.627us	20	20	100.00
		kmac_csr_aliasing	9.210s	474.383us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	124.861us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	208.583us	5	5	100.00
		kmac_csr_rw	1.250s	108.627us	20	20	100.00
		kmac_csr_aliasing	9.210s	474.383us	5	5	100.00
		kmac_same_csr_outstanding	2.670s	124.861us	20	20	100.00
V2		TOTAL			1036	1050	98.67
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.370s	136.847us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.370s	136.847us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.370s	136.847us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.370s	136.847us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.950s	432.536us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.821m	8.044ms	5	5	100.00
		kmac_tl_intg_err	5.360s	1.142ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.360s	1.142ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.112m	1.069ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.394m	4.610ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.278m	21.838ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.370s	136.847us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.821m	8.044ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.821m	8.044ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.821m	8.044ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.394m	4.610ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.112m	1.069ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.821m	8.044ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	8.086m	15.774ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.394m	4.610ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	43.860m	105.672ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1242	1290	96.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.94	98.10	92.43	99.89	95.45	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test kmac_stress_all_with_rand_reset has 22 failures.
  - 0.kmac_stress_all_with_rand_reset.44175681316326170461837530227544295695711700792129295140380889292713731145322
    Line 366, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19636317140 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19636317140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.8206846365676200958492411451930153729949201889585048799448391826949573699429
    Line 349, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14284830309 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14284830309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:
- Test kmac_stress_all_with_rand_reset has 10 failures.
  - 1.kmac_stress_all_with_rand_reset.39897791411768593320516232621604710157107449743075353022747474419652268209369
    Line 825, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33742434879 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 33742434879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.97683322117037495656248580595148719063128348037674104356659556127684811536071
    Line 2617, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 72151277957 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 72151277957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_mubi has 1 failures.

2.kmac_mubi.96501072683331849231274533559078550178291031153666464369406562246066756775254
Line 513, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mubi/latest/run.log

  UVM_FATAL @ 3074944269 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (129 [0x81] vs 109 [0x6d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3074944269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

2.kmac_stress_all.37296608617563995915961272774828369839863129593079453337003043589725732521246
Line 923, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest/run.log

  UVM_FATAL @ 73580872330 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (228 [0xe4] vs 114 [0x72]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 73580872330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_stress_all.34065440672889070034064613946624453325285377135780308933773906957567995522582
Line 2013, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log

  UVM_FATAL @ 73390309243 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (109 [0x6d] vs 23 [0x17]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 73390309243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

15.kmac_app.60379941091889366255644769061368078938758074340138491057703665080787513766386
Line 519, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_app/latest/run.log

  UVM_FATAL @ 4803279738 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (185 [0xb9] vs 162 [0xa2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4803279738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

46.kmac_entropy_refresh.23113604478537161909559439814124939709193074697991096573707230317445004130050
Line 473, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 17819974720 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (1 [0x1] vs 25 [0x19]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 17819974720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
- Test kmac_stress_all has 1 failures.
  - 9.kmac_stress_all.115127049991471517512730426226632671543290809914952609486087896237231507476281
    Line 1089, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 26093151888 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 26093151888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_kmac has 1 failures.
  - 12.kmac_test_vectors_kmac.27237324835316953390335642323680220542294360538986319107993081430501944344433
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  71575291 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  71575291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 32.kmac_test_vectors_sha3_256.96429897022364890221864634749846067723716379029979774995800369175396177179396
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  63710881 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  63710881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 34.kmac_test_vectors_shake_128.53442208007151213538694420118470227890095043854275533588396570207267897086904
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  46435361 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  46435361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 49.kmac_test_vectors_shake_256.31043620382931359101178299710704540791770155089578001887016256547555811968387
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @ 117858340 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 117858340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all has 2 failures.
  - 4.kmac_stress_all.73579182265072965112420621634130627219345968969885742844854459074657835451496
    Line 1465, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 65617691983 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 65617691983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.kmac_stress_all.15656059247256137996921905670753780883345085279109569809910456240699477335896
    Line 566, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 23308353858 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 23308353858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 7.kmac_stress_all_with_rand_reset.94753244641600726834977379058550804960485779694291553190763981490925587409027
    Line 648, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 24391223054 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 24391223054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 21.kmac_error.32510844277265415967473409352880127734816511613400897457241597779096949235274
    Line 410, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
```
  UVM_FATAL @ 10373063307 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10373063307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 3.kmac_entropy_refresh.16222384349352732370377112866876094407397374135128196716404156817047883602232
    Line 742, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 41.kmac_burst_write.47984315903818974512541083342918512663130214058997263449066258282632117266386
    Line 735, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```