KMAC/MASKED Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.420m	16.621ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	37.535us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	46.629us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	21.390s	8.491ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.930s	610.826us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.710s	75.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	46.629us	20	20	100.00
		kmac_csr_aliasing	9.930s	610.826us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	34.838us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	40.312us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	58.729m	185.222ms	49	50	98.00
V2	burst_write	kmac_burst_write	26.467m	83.703ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	40.092m	348.043ms	49	50	98.00
		kmac_test_vectors_sha3_256	39.628m	443.491ms	49	50	98.00
		kmac_test_vectors_sha3_384	31.641m	283.889ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.022m	378.984ms	49	50	98.00
		kmac_test_vectors_shake_128	1.700h	1.083s	49	50	98.00
		kmac_test_vectors_shake_256	1.640h	3.137s	50	50	100.00
		kmac_test_vectors_kmac	10.740s	1.404ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.650s	743.185us	50	50	100.00
V2	sideload	kmac_sideload	9.401m	85.395ms	49	50	98.00
V2	app	kmac_app	6.030m	34.210ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.046m	11.688ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.879m	173.449ms	46	50	92.00
V2	error	kmac_error	8.553m	78.722ms	50	50	100.00
V2	key_error	kmac_key_error	7.680s	1.437ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.650s	5.388ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.910s	2.442ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.081m	12.600ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.970s	3.999ms	49	50	98.00
V2	stress_all	kmac_stress_all	43.613m	59.016ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.920s	15.710us	50	50	100.00
V2	alert_test	kmac_alert_test	0.930s	23.785us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.640s	839.098us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.640s	839.098us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	37.535us	5	5	100.00
		kmac_csr_rw	1.270s	46.629us	20	20	100.00
		kmac_csr_aliasing	9.930s	610.826us	5	5	100.00
		kmac_same_csr_outstanding	2.730s	442.425us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	37.535us	5	5	100.00
		kmac_csr_rw	1.270s	46.629us	20	20	100.00
		kmac_csr_aliasing	9.930s	610.826us	5	5	100.00
		kmac_same_csr_outstanding	2.730s	442.425us	20	20	100.00
V2		TOTAL			1034	1050	98.48
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.520s	415.959us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.520s	415.959us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.520s	415.959us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.520s	415.959us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.320s	1.857ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.698m	39.265ms	5	5	100.00
		kmac_tl_intg_err	7.000s	4.344ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	7.000s	4.344ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.970s	3.999ms	49	50	98.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.420m	16.621ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.401m	85.395ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.520s	415.959us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.698m	39.265ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.698m	39.265ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.698m	39.265ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.420m	16.621ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.970s	3.999ms	49	50	98.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.698m	39.265ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.408m	9.819ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.420m	16.621ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	48.659m	227.735ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1241	1290	96.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	14	56.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.42	98.10	92.43	99.89	91.82	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test kmac_stress_all_with_rand_reset has 27 failures.
  - 0.kmac_stress_all_with_rand_reset.36136021694480640280769956347256019005738296176641637228639899101114994219706
    Line 1154, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 154417710949 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 154417710949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.11859627892745664879673116689936508194029868263116709527214283411998107055741
    Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2178883481 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2178883481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 5.kmac_test_vectors_sha3_512.85399751655529154419943480389444474029703253042569220454099398259363253439874
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @ 192015541 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 192015541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 10.kmac_test_vectors_shake_128.28868256161273718673833251309647640545858933538548742738004890368496887397643
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @ 120660901 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 120660901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 25.kmac_test_vectors_sha3_224.78581089584156568285185855925571309459411660469893882025751040377761542168921
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @ 126969812 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 126969812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 28.kmac_stress_all.11148599024097852158313047066498968073574746369579952582367966037865280361325
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest/run.log
```
  UVM_ERROR @  61338568 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61338568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 33.kmac_test_vectors_sha3_384.78292477336996368144211691460508307027713261041152052450436455009130491838788
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  33337035 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  33337035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test kmac_entropy_refresh has 3 failures.
  - 2.kmac_entropy_refresh.114248445346166725477907352378433777469701146905406916552206736170577919380815
    Line 888, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.kmac_entropy_refresh.49867929973895715693824830017420595370404028839244739795842728059692452866876
    Line 683, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_sideload has 1 failures.
  - 41.kmac_sideload.36351011697550656684028733931983333994969737397905333610643495866484683960004
    Line 1047, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 22.kmac_stress_all_with_rand_reset.115357328104878859475965127528331609755865142885812963350489344432859869326257
    Line 947, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28021887313 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 28021887313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.kmac_stress_all_with_rand_reset.89423151056608988472310102179904082699819380790040134825555198199963020111211
    Line 827, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132414290307 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 132414290307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_lc_escalation has 1 failures.

4.kmac_lc_escalation.48705329336496308481222338154632149961355417343470203820844456281072658277429
Line 316, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest/run.log

  UVM_FATAL @ 1616728670 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (248 [0xf8] vs 26 [0x1a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1616728670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

11.kmac_stress_all.40520500607012807315089507426472120818851173608295078303342020535741425393985
Line 991, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest/run.log

  UVM_FATAL @ 13575243599 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (223 [0xdf] vs 214 [0xd6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13575243599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

24.kmac_entropy_refresh.75811981339436417777079364273887511491100826877549860233991411157269421478847
Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3579507911 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (145 [0x91] vs 0 [0x0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3579507911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 19.kmac_stress_all.2238203601004259434361354423134745177277424218236720107652958041585856458104
    Line 1182, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 249449068834 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 249449068834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 46.kmac_stress_all_with_rand_reset.89742345898146860350403111551237389254968926890050970416550115702693712569295
    Line 1998, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 182961729883 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 182961729883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.kmac_stress_all_with_rand_reset.21784193138825247260652449998988008609672019070427322060890983720356033805076
    Line 1242, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 172407620411 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 172407620411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
- Test kmac_key_error has 1 failures.
  - 13.kmac_key_error.309568672449880287421560262790081678490880239072893918011889919836420576704
    Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_key_error/latest/run.log
```
  UVM_ERROR @  55250112 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
  UVM_INFO @  55250112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 19.kmac_long_msg_and_output.60319722626009479355689236816036430685721728720495777218247345233222444298038
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:7df99b57-ca4b-4808-a8d6-1102ab19eb92
```