2723ca659d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.368m | 7.006ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.140s | 85.454us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.170s | 114.753us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.190s | 1.511ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.210s | 406.340us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.560s | 143.087us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.170s | 114.753us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.210s | 406.340us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.830s | 13.801us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.520s | 46.996us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 55.184m | 364.371ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 23.942m | 14.697ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 39.428m | 820.754ms | 48 | 50 | 96.00 |
| kmac_test_vectors_sha3_256 | 36.803m | 97.538ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_384 | 31.380m | 292.771ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 22.782m | 196.948ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.722h | 1.594s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_256 | 1.440h | 878.085ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 7.720s | 2.728ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 7.150s | 1.152ms | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.073m | 84.721ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.986m | 19.993ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.753m | 26.748ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.022m | 30.645ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 9.171m | 95.881ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 7.870s | 4.506ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 49.820s | 28.639ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 31.270s | 4.275ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.340m | 17.326ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 37.310s | 3.426ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 52.095m | 293.553ms | 47 | 50 | 94.00 |
| V2 | intr_test | kmac_intr_test | 0.920s | 29.891us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.980s | 17.924us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.040s | 102.285us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.040s | 102.285us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.140s | 85.454us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 114.753us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.210s | 406.340us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.710s | 432.802us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.140s | 85.454us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 114.753us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.210s | 406.340us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.710s | 432.802us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1039 | 1050 | 98.95 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.470s | 69.246us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.470s | 69.246us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.470s | 69.246us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.470s | 69.246us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.250s | 114.176us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.517m | 9.674ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.240s | 494.293us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.240s | 494.293us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 37.310s | 3.426ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.368m | 7.006ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.073m | 84.721ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.470s | 69.246us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.517m | 9.674ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.517m | 9.674ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.517m | 9.674ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.368m | 7.006ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 37.310s | 3.426ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.517m | 9.674ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.979m | 18.328ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.368m | 7.006ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 35.894m | 32.251ms | 15 | 50 | 30.00 |
| V3 | TOTAL | 15 | 50 | 30.00 | |||
| TOTAL | 1244 | 1290 | 96.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.81 | 98.10 | 92.43 | 99.89 | 94.55 | 95.91 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
3.kmac_stress_all_with_rand_reset.100286663452655871867433282335957711474678679527785915549486504670358505675779
Line 573, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 96091342200 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 96091342200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.kmac_stress_all_with_rand_reset.32917419097391530022035799857178817249748315843227880889262118085509889340558
Line 527, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10694046840 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10694046840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:
1.kmac_stress_all_with_rand_reset.13737333957771893470467404078822211162348739250239132516940913829432701241789
Line 1970, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 145889356424 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 145889356424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.5306864842424812561209338643811168766418897112938221201026749127920183408884
Line 520, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27622724743 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
UVM_INFO @ 27622724743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 6 failures:
Test kmac_stress_all has 3 failures.
0.kmac_stress_all.87469137826037792817850704736289794643402509482483442163909650470855088481725
Line 2676, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
UVM_FATAL @ 47155642757 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 47155642757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.kmac_stress_all.4637823268289838386725682376585506369826420547188591007184212093407972859159
Line 544, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest/run.log
UVM_FATAL @ 12837118851 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 12837118851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test kmac_stress_all_with_rand_reset has 2 failures.
14.kmac_stress_all_with_rand_reset.87560197724318054784331505853688274922186104050484188572532940419430942268971
Line 663, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 161772854730 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 161772854730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.kmac_stress_all_with_rand_reset.62928166383757909578178993612040444704881677566747102461498591142156757666761
Line 588, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14346743940 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 14346743940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
21.kmac_error.89372927568456653265780082672702784746588765815506193765200220232113054239689
Line 1026, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
UVM_FATAL @ 10051061996 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10051061996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:
Test kmac_test_vectors_shake_128 has 1 failures.
11.kmac_test_vectors_shake_128.109215136509443577831169474910543858316507857138216814278883257891912129418637
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 81160818 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 81160818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
12.kmac_test_vectors_kmac.42322044790180905043183565116018593062614025853704735980606387530398096388740
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 75621844 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 75621844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_256 has 1 failures.
34.kmac_test_vectors_sha3_256.89691306968364579931401711975055205251587896511500382034170163282585394007305
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 49316508 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 49316508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
36.kmac_test_vectors_shake_256.65583093239971108825311692702999965529238929974683188989137540783915595168360
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 152141926 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 152141926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_224 has 2 failures.
40.kmac_test_vectors_sha3_224.56383873708320014368441852430559074206843321077181764632312073303881692143997
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_224/latest/run.log
UVM_ERROR @ 39785686 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 39785686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.kmac_test_vectors_sha3_224.71798627635698931178305359912798901678275685066119231746657336552463787670961
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_224/latest/run.log
UVM_ERROR @ 125045249 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 125045249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
35.kmac_key_error.107556878555459837357326873096096968848438760542345067803824058191419365120714
Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_key_error/latest/run.log
UVM_ERROR @ 1509828004 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 1509828004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---