ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.257m | 8.002ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 34.199us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.210s | 109.613us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.370s | 6.372ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.070s | 1.860ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.900s | 325.442us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.210s | 109.613us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.070s | 1.860ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.790s | 111.149us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.620s | 41.137us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 59.544m | 854.508ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 26.679m | 28.657ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 42.564m | 612.337ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 40.878m | 767.364ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 36.615m | 1.421s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_512 | 22.425m | 213.323ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_128 | 1.740h | 1.895s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.440h | 234.769ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 6.640s | 337.412us | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.200s | 2.132ms | 49 | 50 | 98.00 | ||
| V2 | sideload | kmac_sideload | 9.275m | 76.674ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 6.685m | 139.116ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 5.471m | 16.872ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.560m | 15.038ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 8.096m | 16.362ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 8.660s | 12.783ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 53.980s | 2.242ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 41.750s | 1.467ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.145m | 35.794ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 52.920s | 11.948ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 41.123m | 133.599ms | 48 | 50 | 96.00 |
| V2 | intr_test | kmac_intr_test | 0.880s | 15.579us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.910s | 31.560us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.450s | 219.877us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.450s | 219.877us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 34.199us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.210s | 109.613us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.070s | 1.860ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.970s | 964.247us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 34.199us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.210s | 109.613us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.070s | 1.860ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.970s | 964.247us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1041 | 1050 | 99.14 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.490s | 425.065us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.490s | 425.065us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.490s | 425.065us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.490s | 425.065us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.010s | 152.188us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.869m | 37.261ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.700s | 520.103us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.700s | 520.103us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 52.920s | 11.948ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.257m | 8.002ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.275m | 76.674ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.490s | 425.065us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.869m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.869m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.869m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.257m | 8.002ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 52.920s | 11.948ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.869m | 37.261ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.075m | 55.719ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.257m | 8.002ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 54.071m | 80.072ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 1247 | 1290 | 96.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.86 | 98.10 | 92.71 | 99.89 | 94.55 | 95.97 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
0.kmac_stress_all_with_rand_reset.12880213391574926929614506799563421518664556769356418421481892296510357273466
Line 711, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18998423258 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 18998423258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.7631496441705241751996370170535970015562226216973584107987819714942720189922
Line 889, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14842620196 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14842620196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
2.kmac_stress_all_with_rand_reset.81180710675692841172507583114439412473934624640745400157459290247942962843768
Line 780, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18528607985 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
UVM_INFO @ 18528607985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.kmac_stress_all_with_rand_reset.36981970720357553673125478772356292062940048475278324923843016656668109101611
Line 2456, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25951770075 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
UVM_INFO @ 25951770075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:
Test kmac_test_vectors_sha3_384 has 1 failures.
3.kmac_test_vectors_sha3_384.40879681172127121832580434212439631882326982068006746654456887581604984645385
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest/run.log
UVM_ERROR @ 21720069 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 21720069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_512 has 1 failures.
8.kmac_test_vectors_sha3_512.73972812966763530131851699080792748947499662038168810059358720349661617869243
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 73228298 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 73228298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac_xof has 1 failures.
14.kmac_test_vectors_kmac_xof.82545897700333552001135473131347831602742731226481029359096634138588390111621
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_kmac_xof/latest/run.log
UVM_ERROR @ 41746572 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 41746572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_smoke has 1 failures.
38.kmac_smoke.35526139197653165422765600290401856798422886113526205319143063844855435396415
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_smoke/latest/run.log
UVM_ERROR @ 57581695 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 57581695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
Test kmac_error has 1 failures.
12.kmac_error.46118625385142876458145915763954545398106658700301451610031380647914640086000
Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_error/latest/run.log
UVM_FATAL @ 10811538138 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 10811538138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 2 failures.
38.kmac_stress_all.47013850036168901077743920682453038354387865394683111401903509346846686836895
Line 1439, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log
UVM_FATAL @ 185577328545 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 185577328545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.kmac_stress_all.70331293363192202506275141904229133412586692441152345653313182544136873648286
Line 2194, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log
UVM_FATAL @ 150428827494 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 150428827494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_stress_all_with_rand_reset has 1 failures.
35.kmac_stress_all_with_rand_reset.43655805276783193300074277183649942578257366582119486365262869032283172927653
Line 1290, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 49427942685 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (166 [0xa6] vs 60 [0x3c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 49427942685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
36.kmac_entropy_refresh.11327620320969630674601746042749714160360174488810054836044645795207699814199
Line 449, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 22689927902 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (89 [0x59] vs 84 [0x54]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 22689927902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
6.kmac_app.70054879718849219513632457957708982108013193793906951207075608070576388916173
Line 1155, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:
17.kmac_key_error.40363699127425756205997713294387371298263161141620700396953006672300080683426
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_key_error/latest/run.log
UVM_ERROR @ 154646588 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
UVM_INFO @ 154646588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---