KMAC/MASKED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.572m	16.324ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	107.318us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.350s	31.351us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.430s	1.512ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.430s	543.528us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.680s	147.314us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.350s	31.351us	20	20	100.00
		kmac_csr_aliasing	10.430s	543.528us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.840s	13.935us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	195.470us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.250m	109.302ms	35	50	70.00
V2	burst_write	kmac_burst_write	29.282m	15.369ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.729m	133.100ms	39	50	78.00
		kmac_test_vectors_sha3_256	58.212m	419.971ms	43	50	86.00
		kmac_test_vectors_sha3_384	48.025m	269.641ms	49	50	98.00
		kmac_test_vectors_sha3_512	31.678m	196.849ms	50	50	100.00
		kmac_test_vectors_shake_128	1.881h	273.449ms	23	50	46.00
		kmac_test_vectors_shake_256	1.608h	209.566ms	18	50	36.00
		kmac_test_vectors_kmac	9.040s	5.522ms	48	50	96.00
		kmac_test_vectors_kmac_xof	8.200s	4.962ms	48	50	96.00
V2	sideload	kmac_sideload	10.030m	20.882ms	50	50	100.00
V2	app	kmac_app	7.611m	15.993ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	8.814m	353.389ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.960m	134.942ms	50	50	100.00
V2	error	kmac_error	9.973m	98.537ms	49	50	98.00
V2	key_error	kmac_key_error	16.650s	7.971ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	54.550s	8.784ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	35.240s	462.780us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.105m	23.177ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	19.400s	2.894ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.263h	564.734ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.900s	15.474us	50	50	100.00
V2	alert_test	kmac_alert_test	0.970s	44.098us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.520s	172.575us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.520s	172.575us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	107.318us	5	5	100.00
		kmac_csr_rw	1.350s	31.351us	20	20	100.00
		kmac_csr_aliasing	10.430s	543.528us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	637.767us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	107.318us	5	5	100.00
		kmac_csr_rw	1.350s	31.351us	20	20	100.00
		kmac_csr_aliasing	10.430s	543.528us	5	5	100.00
		kmac_same_csr_outstanding	2.720s	637.767us	20	20	100.00
V2		TOTAL			951	1050	90.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.490s	54.000us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.490s	54.000us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.490s	54.000us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.490s	54.000us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.250s	490.636us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.531m	27.602ms	5	5	100.00
		kmac_tl_intg_err	5.210s	641.267us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.210s	641.267us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	19.400s	2.894ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.572m	16.324ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.030m	20.882ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.490s	54.000us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.531m	27.602ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.531m	27.602ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.531m	27.602ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.572m	16.324ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	19.400s	2.894ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.531m	27.602ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.011m	18.683ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.572m	16.324ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	58.693m	795.425ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1144	1250	91.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	15	60.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.30	97.89	92.55	99.89	77.46	95.53	98.89	97.88

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 91 failures:
- Test kmac_test_vectors_shake_128 has 27 failures.
  - 0.kmac_test_vectors_shake_128.68352879600834176286676726590103572918179432144112785747203647243484572494664
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:a7807cc4-5672-4991-a567-ca2b330747de
```
  - 4.kmac_test_vectors_shake_128.27077255853185858174600739951675735793361107313060779351239840527110829914275
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:71289755-34c6-4698-a7e6-652c0ee34062
```
  - ... and 25 more failures.
- Test kmac_test_vectors_shake_256 has 32 failures.
  - 0.kmac_test_vectors_shake_256.98004375220839359953889734753293762733456835671305008986513494624570167298669
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:b85243e4-3009-48ee-8de3-2c93e747adcc
```
  - 2.kmac_test_vectors_shake_256.61915428696549405373022775229805919399096501286608511789787176798963874262242
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:dc0254bd-8b0c-4e24-8bf6-cba6ce1297e8
```
  - ... and 30 more failures.
- Test kmac_long_msg_and_output has 15 failures.
  - 2.kmac_long_msg_and_output.50860965935889785539780419138363625644447608711886497155181928922722285087058
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:3e2c66af-8a20-4edd-b28b-506390d4abe7
```
  - 3.kmac_long_msg_and_output.100265151719911794837681662742725984935406318093991922244161729232993914671192
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:89a2d012-5185-455e-bc34-ac0e481af5c9
```
  - ... and 13 more failures.
- Test kmac_test_vectors_sha3_224 has 11 failures.
  - 3.kmac_test_vectors_sha3_224.44799604042968921661619263880528718258630670738682412243295123313769031562117
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:d38cb112-7826-4d39-a11d-b3e030088bc7
```
  - 6.kmac_test_vectors_sha3_224.24651314440847487748848326657809477879862751367792948908065079885444765836001
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:c6e5b8dc-9d79-449f-958d-3562cc5282d4
```
  - ... and 9 more failures.
- Test kmac_test_vectors_sha3_256 has 6 failures.
  - 7.kmac_test_vectors_sha3_256.88259217113260069410013682309034849307277760919538629894147826177623095173067
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:c434fa75-fb67-46e1-86f6-fcc3cbca65f6
```
  - 16.kmac_test_vectors_sha3_256.43556208487003743833748714623954588107740433534746012497648638952566574584450
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:2b7aeea5-fd52-49bd-abe7-a15cbcd49290
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_kmac has 2 failures.

10.kmac_test_vectors_kmac.22532620812515898277045331205975847267434127281717347153040543605011245997283
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  30330884 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  30330884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_test_vectors_kmac.65805106802313539965881852217287464195962471511297225256737510382019802649328
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  34976561 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34976561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac_xof has 2 failures.

10.kmac_test_vectors_kmac_xof.115123274758680783884762944648024691459687118852772865800209709547566658130246
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac_xof/latest/run.log

  UVM_ERROR @  65280420 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  65280420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.kmac_test_vectors_kmac_xof.30489617665805000396929444106147202528035664282782522427843902289921291856364
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_kmac_xof/latest/run.log

  UVM_ERROR @ 126017843 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 126017843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_256 has 1 failures.

33.kmac_test_vectors_sha3_256.9994171523391029427328537159634003155442921098847414783475813669314734416789
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_256/latest/run.log

  UVM_ERROR @  83509920 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  83509920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

49.kmac_test_vectors_sha3_384.107780407566357923265586036310168194591478566344544763919382287330196023279250
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  34725154 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34725154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.6244569094213652624585937183999462228442793520030296461359579759980685070919
    Line 888, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 320452290303 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 320452290303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.70440315664950719888831302584497784037004797972392518124313294226703889852337
    Line 642, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 71385393123 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 71385393123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 3.kmac_stress_all_with_rand_reset.6137059670794353911277986884733754809450643043957159276514081100804998713433
    Line 3763, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 75195566253 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 75195566253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.kmac_stress_all_with_rand_reset.29466004157969833612348422963939136868071171832050729316171361945980979252293
    Line 815, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5930448311 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5930448311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 1.kmac_error.102351911699937610101108986060745699489785781227526872871407684707127257530023
    Line 890, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 11.kmac_key_error.39372465667885969444710726610827583326384882948246894178562781506345328327251
    Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 748433344 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 748433344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```