KMAC/MASKED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.599m	7.938ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.230s	199.624us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	38.256us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.500s	3.014ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.200s	144.082us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.510s	394.388us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	38.256us	20	20	100.00
		kmac_csr_aliasing	8.200s	144.082us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	16.439us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.260s	106.440us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.030m	464.061ms	50	50	100.00
V2	burst_write	kmac_burst_write	31.104m	65.534ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	48.102m	1.410s	48	50	96.00
		kmac_test_vectors_sha3_256	40.968m	771.639ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.965m	540.578ms	49	50	98.00
		kmac_test_vectors_sha3_512	26.379m	547.995ms	49	50	98.00
		kmac_test_vectors_shake_128	1.761h	1.035s	50	50	100.00
		kmac_test_vectors_shake_256	1.583h	1.572s	50	50	100.00
		kmac_test_vectors_kmac	8.270s	4.801ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.790s	1.483ms	50	50	100.00
V2	sideload	kmac_sideload	8.508m	24.282ms	50	50	100.00
V2	app	kmac_app	6.751m	13.562ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.501m	15.728ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	7.023m	7.362ms	49	50	98.00
V2	error	kmac_error	8.847m	20.518ms	49	50	98.00
V2	key_error	kmac_key_error	15.920s	15.446ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.080s	2.900ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.550s	1.090ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.386m	25.026ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	28.720s	317.729us	50	50	100.00
V2	stress_all	kmac_stress_all	46.887m	452.418ms	46	50	92.00
V2	intr_test	kmac_intr_test	0.880s	16.840us	50	50	100.00
V2	alert_test	kmac_alert_test	0.990s	28.689us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.890s	314.977us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.890s	314.977us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.230s	199.624us	5	5	100.00
		kmac_csr_rw	1.190s	38.256us	20	20	100.00
		kmac_csr_aliasing	8.200s	144.082us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	886.598us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.230s	199.624us	5	5	100.00
		kmac_csr_rw	1.190s	38.256us	20	20	100.00
		kmac_csr_aliasing	8.200s	144.082us	5	5	100.00
		kmac_same_csr_outstanding	2.960s	886.598us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.540s	111.894us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.540s	111.894us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.540s	111.894us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.540s	111.894us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.830s	240.516us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.086m	40.147ms	5	5	100.00
		kmac_tl_intg_err	5.110s	343.849us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.110s	343.849us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	28.720s	317.729us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.599m	7.938ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.508m	24.282ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.540s	111.894us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.086m	40.147ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.086m	40.147ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.086m	40.147ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.599m	7.938ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	28.720s	317.729us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.086m	40.147ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.897m	22.466ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.599m	7.938ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.139h	82.066ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1228	1250	98.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.14	97.91	92.62	99.89	76.06	95.59	99.05	97.88

Failure Buckets

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 8 failures:

Test kmac_app has 4 failures.

1.kmac_app.95707484051994735281618639122685032611085676438575227667888319963815295106185
Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 2942439131 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (42 [0x2a] vs 231 [0xe7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2942439131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_app.35375136885575715958782213623948579743048372780790492633192402631040935846037
Line 621, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app/latest/run.log

  UVM_FATAL @ 10898418538 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (121 [0x79] vs 74 [0x4a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10898418538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test kmac_app_with_partial_data has 1 failures.

7.kmac_app_with_partial_data.40000886499523385516593062222120267809706195443414337022702533813988056694348
Line 453, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 6553347371 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (206 [0xce] vs 138 [0x8a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 6553347371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

9.kmac_stress_all.61855788406023760114300712817274884161228924240351309957956365609404627702317
Line 979, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log

  UVM_FATAL @ 176331596564 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (174 [0xae] vs 87 [0x57]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 176331596564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

20.kmac_error.74389998226328230195436319510419125946516258332662944192723111200914062618588
Line 642, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest/run.log

  UVM_FATAL @ 30821400728 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (87 [0x57] vs 247 [0xf7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 30821400728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

46.kmac_entropy_refresh.96667266463647494272090597344655697305771978970476652401428444749697395260065
Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 3622437357 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (38 [0x26] vs 79 [0x4f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3622437357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.16249577325507263471820511385131798484546961084297539955286567359730806328345
    Line 1123, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 258231474657 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 258231474657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.93240750339369944076808917441988476270582090169422545408449272371528211558534
    Line 431, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7075911512 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7075911512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_test_vectors_sha3_224 has 2 failures.

4.kmac_test_vectors_sha3_224.45644111504269056423205470758907897355257636824112761377827100960603775038951
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  24274130 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  24274130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.kmac_test_vectors_sha3_224.30257610511759690023083267868985411766031733148330353044025453514736788738328
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  56180502 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  56180502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_512 has 1 failures.

6.kmac_test_vectors_sha3_512.26132996402540143809201476486283491706914373716481072730438417313076590965445
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @  23871853 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  23871853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

46.kmac_stress_all.9709567709421339590945175067482881602877987692103014936341020298426176696641
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_ERROR @  60777151 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  60777151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.kmac_stress_all.43465565248752238361861803297375377082842022031574648289276729473195759580311
Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log

  UVM_ERROR @  73941598 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73941598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_384 has 1 failures.

48.kmac_test_vectors_sha3_384.44372872711377264495115626230773483944392591820274826472424647508498408499142
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  77245232 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  77245232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.55277306061028677065288326161286570987186531909481600341264499357692798361053
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  58518751 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @  58518751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 34.kmac_stress_all.82481758927066795875210571334297573475905309533331173522228603191870167890253
    Line 2052, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 37289871765 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 37289871765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```