KMAC/MASKED Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.820m	53.826ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	61.156us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	38.040us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.100s	5.086ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.430s	514.085us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.870s	383.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	38.040us	20	20	100.00
		kmac_csr_aliasing	9.430s	514.085us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	17.851us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.510s	51.942us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.701m	144.492ms	35	50	70.00
V2	burst_write	kmac_burst_write	31.177m	93.901ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	59.780m	1.185s	38	50	76.00
		kmac_test_vectors_sha3_256	59.539m	133.819ms	46	50	92.00
		kmac_test_vectors_sha3_384	50.798m	1.025s	48	50	96.00
		kmac_test_vectors_sha3_512	33.449m	125.199ms	50	50	100.00
		kmac_test_vectors_shake_128	1.989h	269.674ms	17	50	34.00
		kmac_test_vectors_shake_256	1.588h	309.388ms	15	50	30.00
		kmac_test_vectors_kmac	7.650s	997.760us	50	50	100.00
		kmac_test_vectors_kmac_xof	7.940s	341.783us	50	50	100.00
V2	sideload	kmac_sideload	10.045m	104.094ms	50	50	100.00
V2	app	kmac_app	7.255m	17.800ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.462m	37.323ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.518m	150.885ms	50	50	100.00
V2	error	kmac_error	9.476m	70.243ms	50	50	100.00
V2	key_error	kmac_key_error	14.840s	2.367ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	51.260s	3.472ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	30.190s	1.413ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.317m	7.377ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	34.060s	1.309ms	50	50	100.00
V2	stress_all	kmac_stress_all	45.284m	52.666ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	48.800us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	34.944us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.350s	1.121ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.350s	1.121ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	61.156us	5	5	100.00
		kmac_csr_rw	1.190s	38.040us	20	20	100.00
		kmac_csr_aliasing	9.430s	514.085us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	128.624us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	61.156us	5	5	100.00
		kmac_csr_rw	1.190s	38.040us	20	20	100.00
		kmac_csr_aliasing	9.430s	514.085us	5	5	100.00
		kmac_same_csr_outstanding	2.750s	128.624us	20	20	100.00
V2		TOTAL			947	1050	90.19
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	71.210us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	71.210us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	71.210us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	71.210us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.300s	189.305us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.843m	7.389ms	5	5	100.00
		kmac_tl_intg_err	4.970s	735.481us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.970s	735.481us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	34.060s	1.309ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.820m	53.826ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	10.045m	104.094ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	71.210us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.843m	7.389ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.843m	7.389ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.843m	7.389ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.820m	53.826ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	34.060s	1.309ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.843m	7.389ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.167m	49.043ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.820m	53.826ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	37.448m	120.294ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			1140	1250	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.18	97.89	92.58	99.89	76.76	95.53	98.89	97.73

Failure Buckets

Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 98 failures:
- Test kmac_test_vectors_sha3_256 has 4 failures.
  - 0.kmac_test_vectors_sha3_256.73041071802025242971464486441876749800646380189153194763254341644440977710631
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:c8a125e3-bc9a-482a-9a25-96f22d3cba5f
```
  - 28.kmac_test_vectors_sha3_256.3881783046147770103458817826465715488284705706468189063509212762930297454903
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_256/latest/run.log
```
  Job ID: smart:e0a7c0e6-c0b0-48cc-b698-fc5aee26cb54
```
  - ... and 2 more failures.
- Test kmac_test_vectors_shake_128 has 33 failures.
  - 0.kmac_test_vectors_shake_128.56590340049628525213396674570860764932975939141285118110380846290090274550446
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:bb3c0487-8644-45c8-b891-59522bebe083
```
  - 1.kmac_test_vectors_shake_128.78672159912486960013439399654808558990059516335007116776605014865683365635198
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
```
  Job ID: smart:f22192d2-b74f-418b-9381-5806610dd790
```
  - ... and 31 more failures.
- Test kmac_long_msg_and_output has 15 failures.
  - 1.kmac_long_msg_and_output.97658250436936958605332915912827750611699412771486922264724968798245229029509
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:acc4b991-aef2-4af1-b803-457c3c33db03
```
  - 4.kmac_long_msg_and_output.88162911371392467121226495316860632459167699910725022239756969962770277718610
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:54dc8a35-0376-4dac-80f5-77db6c541040
```
  - ... and 13 more failures.
- Test kmac_test_vectors_shake_256 has 34 failures.
  - 1.kmac_test_vectors_shake_256.68296374364764696563331626208064662234423847290955803641656957752251562385087
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:67ca2209-70ff-4a7c-bf2a-f5bbd785c4b5
```
  - 2.kmac_test_vectors_shake_256.7922664662164925312755059410171255010901369065832616179036245188601193200576
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest/run.log
```
  Job ID: smart:6f1632ed-da56-44bc-8fbb-33a2b0bac310
```
  - ... and 32 more failures.
- Test kmac_test_vectors_sha3_224 has 12 failures.
  - 4.kmac_test_vectors_sha3_224.25540837462026947465808568223778281265111508634944674852227450225491863103009
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:87862d2a-5994-4178-8c46-999619f40803
```
  - 7.kmac_test_vectors_sha3_224.94013091041646570898123264276100578875392666530344152471437913448441549208182
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_224/latest/run.log
```
  Job ID: smart:c15fd98d-c422-4fac-b700-8eab12e706ca
```
  - ... and 10 more failures.

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:

Test kmac_test_vectors_sha3_384 has 2 failures.

2.kmac_test_vectors_sha3_384.89899556329784989317710456102592834684814728234538329783376363448573104182236
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @ 123596748 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 123596748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_test_vectors_sha3_384.64366084831753342243917335549679534752954514730143526253777178041298831439648
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_384/latest/run.log

  UVM_ERROR @  30918335 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  30918335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

14.kmac_stress_all.60169858439735616670706257886917788710121801277137908137623151816495934766668
Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_ERROR @ 196857105 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 196857105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_stress_all.53735601357904861183647150802798621512897307505637890674215237802293232974470
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log

  UVM_ERROR @  38287040 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38287040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 1 failures.

24.kmac_test_vectors_shake_256.12189538303676055383998704601239628714431786618603218317925875076090899534813
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 223273810 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 223273810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 4.kmac_stress_all_with_rand_reset.10701497880786761423562021314620155205034108014462518054097344043340489302000
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 349119540 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 349119540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.kmac_stress_all_with_rand_reset.60603508830389650413631884126263306225990201321867416406307649257387049466593
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4168299408 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4168299408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 3.kmac_stress_all_with_rand_reset.32394447100581026664031363184429081065371992140385408301224619974657931443022
    Line 457, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9121589548 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9121589548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1458) [scoreboard] Check failed digest_share*.size() == output_len_bytes (* [*] vs * [*]) Calculated output length(32) doesn't match actual output length(48)! has 1 failures:
- Test kmac_mubi has 1 failures.
  - 8.kmac_mubi.70881368494289418004185030911365477333714452777988500475502721460129077349240
    Line 271, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 1421677763 ps: (kmac_scoreboard.sv:1458) [uvm_test_top.env.scoreboard] Check failed digest_share0.size() == output_len_bytes (48 [0x30] vs 32 [0x20]) Calculated output length(32) doesn't match actual output length(48)!
  UVM_INFO @ 1421677763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```