KMAC/MASKED Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.629m	21.139ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.190s	33.075us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	33.151us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.700s	3.108ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.040s	287.109us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.020s	387.184us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	33.151us	20	20	100.00
		kmac_csr_aliasing	8.040s	287.109us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	39.150us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.570s	40.261us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	58.325m	219.025ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.235m	51.681ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.061m	705.421ms	49	50	98.00
		kmac_test_vectors_sha3_256	39.995m	488.597ms	50	50	100.00
		kmac_test_vectors_sha3_384	31.600m	580.517ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.483m	34.467ms	50	50	100.00
		kmac_test_vectors_shake_128	1.891h	1.842s	50	50	100.00
		kmac_test_vectors_shake_256	1.540h	890.684ms	49	50	98.00
		kmac_test_vectors_kmac	7.960s	4.628ms	50	50	100.00
		kmac_test_vectors_kmac_xof	8.140s	5.391ms	50	50	100.00
V2	sideload	kmac_sideload	8.371m	21.513ms	50	50	100.00
V2	app	kmac_app	6.967m	97.484ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.459m	13.507ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.362m	61.026ms	48	50	96.00
V2	error	kmac_error	8.771m	22.803ms	49	50	98.00
V2	key_error	kmac_key_error	21.970s	30.322ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.280s	1.563ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.340s	3.662ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.255m	49.821ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	38.830s	1.215ms	50	50	100.00
V2	stress_all	kmac_stress_all	47.073m	82.867ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.870s	13.370us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	41.354us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.660s	151.809us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.660s	151.809us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.190s	33.075us	5	5	100.00
		kmac_csr_rw	1.210s	33.151us	20	20	100.00
		kmac_csr_aliasing	8.040s	287.109us	5	5	100.00
		kmac_same_csr_outstanding	2.740s	646.497us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.190s	33.075us	5	5	100.00
		kmac_csr_rw	1.210s	33.151us	20	20	100.00
		kmac_csr_aliasing	8.040s	287.109us	5	5	100.00
		kmac_same_csr_outstanding	2.740s	646.497us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.590s	59.308us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.590s	59.308us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.590s	59.308us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.590s	59.308us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.250s	635.421us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.843m	73.775ms	5	5	100.00
		kmac_tl_intg_err	5.540s	417.823us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.540s	417.823us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	38.830s	1.215ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.629m	21.139ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.371m	21.513ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.590s	59.308us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.843m	73.775ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.843m	73.775ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.843m	73.775ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.629m	21.139ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	38.830s	1.215ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.843m	73.775ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.400m	12.117ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.629m	21.139ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	52.519m	481.599ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			1233	1250	98.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	25	25	19	76.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.20	97.89	92.58	99.89	76.76	95.53	98.89	97.88

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 1.kmac_stress_all_with_rand_reset.84501442826684517736958716740258999062790255150310983331527941645984045714923
    Line 1356, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 41923495128 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 41923495128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.81322905807456516089108224280077415421146694203744765008428347334475035651558
    Line 839, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33230280477 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33230280477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_entropy_refresh has 2 failures.

7.kmac_entropy_refresh.31419450420832548348202694262608918577746157903677843327218164859236978920283
Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 838551460 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (108 [0x6c] vs 167 [0xa7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 838551460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.kmac_entropy_refresh.78269064983476870092531014288568256261667057593333852268397285487748138575175
Line 287, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 938555884 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (13 [0xd] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 938555884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

25.kmac_app.100146548175572823829928460712319166597491843496640935181772660347847248382396
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 2084678970 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (66 [0x42] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2084678970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_app.11598648190551248601513703262128155199188611112979335271070716864266351325112
Line 597, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_app/latest/run.log

  UVM_FATAL @ 2516262950 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (0 [0x0] vs 100 [0x64]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2516262950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 20.kmac_test_vectors_shake_256.93094674355115755118290908616410751338242019401043751986621240762607153848851
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @  91515025 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  91515025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_224 has 1 failures.
  - 21.kmac_test_vectors_sha3_224.35597630904984000764041555759117879426525055638999212271881339299252269820095
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_sha3_224/latest/run.log
```
  UVM_ERROR @  94416878 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  94416878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 31.kmac_smoke.33148918507919813927486483794654179675427424159619492326716531069693604271552
    Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_smoke/latest/run.log
```
  UVM_ERROR @  34159593 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34159593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_stress_all has 2 failures.
  - 9.kmac_stress_all.49096001815012475329942598686381601247984324962088383669159903099219842849397
    Line 978, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 190853528560 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 190853528560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.kmac_stress_all.18910060273834101849734364211441237671056364639758513502739248505689640341016
    Line 868, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 14008972895 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 14008972895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 5.kmac_stress_all_with_rand_reset.64138479687885248683548665350412358080886390175763962575791176875330416479113
    Line 866, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44869560660 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 44869560660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 12.kmac_error.88251002228775011182942083898657187959685976640176075254449161985333022775248
    Line 976, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```