39f3866b56
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | kmac_smoke | 1.615m | 4.835ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | kmac_csr_hw_reset | 1.250s | 35.542us | 5 | 5 | 100.00 |
V1 | csr_rw | kmac_csr_rw | 1.190s | 34.065us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | kmac_csr_bit_bash | 24.180s | 19.173ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | kmac_csr_aliasing | 10.010s | 1.908ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.680s | 107.856us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.190s | 34.065us | 20 | 20 | 100.00 |
kmac_csr_aliasing | 10.010s | 1.908ms | 5 | 5 | 100.00 | ||
V1 | mem_walk | kmac_mem_walk | 0.800s | 113.843us | 5 | 5 | 100.00 |
V1 | mem_partial_access | kmac_mem_partial_access | 1.330s | 59.667us | 5 | 5 | 100.00 |
V1 | TOTAL | 115 | 115 | 100.00 | |||
V2 | long_msg_and_output | kmac_long_msg_and_output | 58.175m | 228.064ms | 38 | 50 | 76.00 |
V2 | burst_write | kmac_burst_write | 30.485m | 38.735ms | 50 | 50 | 100.00 |
V2 | test_vectors | kmac_test_vectors_sha3_224 | 58.583m | 97.701ms | 35 | 50 | 70.00 |
kmac_test_vectors_sha3_256 | 58.453m | 371.788ms | 42 | 50 | 84.00 | ||
kmac_test_vectors_sha3_384 | 47.658m | 75.177ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_sha3_512 | 34.369m | 294.599ms | 50 | 50 | 100.00 | ||
kmac_test_vectors_shake_128 | 1.910h | 157.806ms | 12 | 50 | 24.00 | ||
kmac_test_vectors_shake_256 | 1.583h | 189.522ms | 19 | 50 | 38.00 | ||
kmac_test_vectors_kmac | 7.380s | 438.004us | 50 | 50 | 100.00 | ||
kmac_test_vectors_kmac_xof | 7.670s | 883.979us | 50 | 50 | 100.00 | ||
V2 | sideload | kmac_sideload | 10.925m | 41.566ms | 50 | 50 | 100.00 |
V2 | app | kmac_app | 7.494m | 16.933ms | 49 | 50 | 98.00 |
V2 | app_with_partial_data | kmac_app_with_partial_data | 6.928m | 15.960ms | 10 | 10 | 100.00 |
V2 | entropy_refresh | kmac_entropy_refresh | 6.710m | 13.944ms | 48 | 50 | 96.00 |
V2 | error | kmac_error | 10.447m | 58.064ms | 50 | 50 | 100.00 |
V2 | key_error | kmac_key_error | 15.570s | 7.532ms | 50 | 50 | 100.00 |
V2 | edn_timeout_error | kmac_edn_timeout_error | 53.780s | 3.054ms | 20 | 20 | 100.00 |
V2 | entropy_mode_error | kmac_entropy_mode_error | 44.250s | 1.393ms | 20 | 20 | 100.00 |
V2 | entropy_ready_error | kmac_entropy_ready_error | 58.550s | 12.329ms | 10 | 10 | 100.00 |
V2 | lc_escalation | kmac_lc_escalation | 44.730s | 2.717ms | 50 | 50 | 100.00 |
V2 | stress_all | kmac_stress_all | 1.131h | 388.770ms | 48 | 50 | 96.00 |
V2 | intr_test | kmac_intr_test | 0.860s | 31.518us | 50 | 50 | 100.00 |
V2 | alert_test | kmac_alert_test | 0.910s | 21.005us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.770s | 304.214us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | kmac_tl_errors | 3.770s | 304.214us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.250s | 35.542us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.190s | 34.065us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.010s | 1.908ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.670s | 564.690us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.250s | 35.542us | 5 | 5 | 100.00 |
kmac_csr_rw | 1.190s | 34.065us | 20 | 20 | 100.00 | ||
kmac_csr_aliasing | 10.010s | 1.908ms | 5 | 5 | 100.00 | ||
kmac_same_csr_outstanding | 2.670s | 564.690us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 941 | 1050 | 89.62 | |||
V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.380s | 228.348us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.380s | 228.348us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.380s | 228.348us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.380s | 228.348us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 2.990s | 734.066us | 20 | 20 | 100.00 |
V2S | tl_intg_err | kmac_sec_cm | 2.155m | 8.647ms | 5 | 5 | 100.00 |
kmac_tl_intg_err | 5.030s | 1.043ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.030s | 1.043ms | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 44.730s | 2.717ms | 50 | 50 | 100.00 |
V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.615m | 4.835ms | 50 | 50 | 100.00 |
V2S | sec_cm_key_sideload | kmac_sideload | 10.925m | 41.566ms | 50 | 50 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.380s | 228.348us | 20 | 20 | 100.00 |
V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.155m | 8.647ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.155m | 8.647ms | 5 | 5 | 100.00 |
V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.155m | 8.647ms | 5 | 5 | 100.00 |
V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.615m | 4.835ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 44.730s | 2.717ms | 50 | 50 | 100.00 |
V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.155m | 8.647ms | 5 | 5 | 100.00 |
V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 6.220m | 11.588ms | 10 | 10 | 100.00 |
V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.615m | 4.835ms | 50 | 50 | 100.00 |
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 36.097m | 485.888ms | 1 | 10 | 10.00 |
V3 | TOTAL | 1 | 10 | 10.00 | |||
TOTAL | 1132 | 1250 | 90.56 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 8 | 8 | 8 | 100.00 |
V2 | 25 | 25 | 17 | 68.00 |
V2S | 5 | 5 | 5 | 100.00 |
V3 | 2 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.30 | 97.89 | 92.55 | 99.89 | 77.46 | 95.53 | 98.89 | 97.88 |
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 103 failures:
0.kmac_long_msg_and_output.38675089593858464160317192899679925380400213231158361504584709656823072490968
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
Job ID: smart:884dc298-9d9c-411d-8cbb-fe964614abe1
3.kmac_long_msg_and_output.40759097023376727329575309983831057605419059870390608331250020927143460519156
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest/run.log
Job ID: smart:8f0286b0-8f03-4dcb-b5b2-4dd4ba0f179c
... and 10 more failures.
0.kmac_test_vectors_sha3_224.20507393484763541446293403086723011365054760522593334556598007206260484506688
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:15d5e5ca-5662-4fc9-b4c0-b1ddca816e52
1.kmac_test_vectors_sha3_224.35373266979271245458746495119647410656149197500841063309684641875489740630957
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:ae36c2f2-55a7-4d5f-82b4-405b335d2ddf
... and 13 more failures.
1.kmac_test_vectors_sha3_256.36458515612481492012963579842058041595125886513381027385533249130684315271297
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:8689ba79-c3c1-42df-8fc6-4e85c86187ea
3.kmac_test_vectors_sha3_256.72419664401707169073761877975237364241404285120042462116333375393691606826820
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:0c71077a-9094-4f8c-9ccd-bce23d07406e
... and 6 more failures.
1.kmac_test_vectors_shake_128.63139493580236792812216617613581053686463435543779834664411993252540627367527
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:ca2e1056-fac9-4d39-803c-58cd5e3ce198
2.kmac_test_vectors_shake_128.3533180813082987253170232877240450149857115945513433243096864822845198737059
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:421884af-f76b-4dfa-b985-d1d5d3e02724
... and 35 more failures.
4.kmac_test_vectors_shake_256.80811893083975473711544654187207554476454595633214480387817714623321177711294
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:8224efbc-6c22-40e3-ab83-c466d321cccc
5.kmac_test_vectors_shake_256.114883281524319455133087315121919358539683214557346170114891379720553419404939
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:778b8a5c-7f8d-4c1f-be6d-4f717da77a4f
... and 29 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 7 failures:
1.kmac_stress_all_with_rand_reset.229334233925844792965977992192698743110661346361155124206831946949572534579
Line 1041, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31901616431 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 31901616431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.98150036493388554950889125119072806757877264925143654408060621389522401975364
Line 469, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43870319097 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 43870319097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]
has 4 failures:
Test kmac_app has 1 failures.
14.kmac_app.31241998880314093753092518981733271066257217509777530811660583619059094775438
Line 441, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_app/latest/run.log
UVM_FATAL @ 1477728202 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (139 [0x8b] vs 197 [0xc5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 1477728202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all has 1 failures.
18.kmac_stress_all.71576495729229873329159690141962869987966307971695370404980960845033576284586
Line 1371, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log
UVM_FATAL @ 10571969168 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (219 [0xdb] vs 120 [0x78]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 10571969168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 2 failures.
31.kmac_entropy_refresh.45918122924988711513973966826438904718477714296859324309761507391482074901011
Line 465, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 7952803791 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (131 [0x83] vs 81 [0x51]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 7952803791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.kmac_entropy_refresh.28866102981833452527458438325874177072080006965478970302766347016810163117021
Line 827, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 5187480039 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (222 [0xde] vs 59 [0x3b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 5187480039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code
has 2 failures:
4.kmac_stress_all_with_rand_reset.84271272391189580743259688820144061398194451788911742809483209021411020905966
Line 2336, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 485888424037 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 485888424037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.kmac_stress_all_with_rand_reset.3704515272468104400211046624488472248014811930461304354748579153183474349314
Line 423, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31346764906 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 31346764906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: *
has 2 failures:
Test kmac_stress_all has 1 failures.
10.kmac_stress_all.49821095966367690862743711951229970332624721989441966516565347471165186558726
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest/run.log
UVM_ERROR @ 56960603 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 56960603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
24.kmac_test_vectors_shake_128.21343216492065909162888412546564662686728242785286733286304906161751086612233
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 39778946 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 39778946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---