KMAC/MASKED Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: 39f3866b56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.615m 4.835ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.250s 35.542us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.190s 34.065us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 24.180s 19.173ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 10.010s 1.908ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.680s 107.856us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.190s 34.065us 20 20 100.00
kmac_csr_aliasing 10.010s 1.908ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.800s 113.843us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.330s 59.667us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 58.175m 228.064ms 38 50 76.00
V2 burst_write kmac_burst_write 30.485m 38.735ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 58.583m 97.701ms 35 50 70.00
kmac_test_vectors_sha3_256 58.453m 371.788ms 42 50 84.00
kmac_test_vectors_sha3_384 47.658m 75.177ms 50 50 100.00
kmac_test_vectors_sha3_512 34.369m 294.599ms 50 50 100.00
kmac_test_vectors_shake_128 1.910h 157.806ms 12 50 24.00
kmac_test_vectors_shake_256 1.583h 189.522ms 19 50 38.00
kmac_test_vectors_kmac 7.380s 438.004us 50 50 100.00
kmac_test_vectors_kmac_xof 7.670s 883.979us 50 50 100.00
V2 sideload kmac_sideload 10.925m 41.566ms 50 50 100.00
V2 app kmac_app 7.494m 16.933ms 49 50 98.00
V2 app_with_partial_data kmac_app_with_partial_data 6.928m 15.960ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 6.710m 13.944ms 48 50 96.00
V2 error kmac_error 10.447m 58.064ms 50 50 100.00
V2 key_error kmac_key_error 15.570s 7.532ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 53.780s 3.054ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 44.250s 1.393ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 58.550s 12.329ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 44.730s 2.717ms 50 50 100.00
V2 stress_all kmac_stress_all 1.131h 388.770ms 48 50 96.00
V2 intr_test kmac_intr_test 0.860s 31.518us 50 50 100.00
V2 alert_test kmac_alert_test 0.910s 21.005us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.770s 304.214us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.770s 304.214us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.250s 35.542us 5 5 100.00
kmac_csr_rw 1.190s 34.065us 20 20 100.00
kmac_csr_aliasing 10.010s 1.908ms 5 5 100.00
kmac_same_csr_outstanding 2.670s 564.690us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.250s 35.542us 5 5 100.00
kmac_csr_rw 1.190s 34.065us 20 20 100.00
kmac_csr_aliasing 10.010s 1.908ms 5 5 100.00
kmac_same_csr_outstanding 2.670s 564.690us 20 20 100.00
V2 TOTAL 941 1050 89.62
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.380s 228.348us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.380s 228.348us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.380s 228.348us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.380s 228.348us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 2.990s 734.066us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 2.155m 8.647ms 5 5 100.00
kmac_tl_intg_err 5.030s 1.043ms 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 5.030s 1.043ms 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 44.730s 2.717ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.615m 4.835ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 10.925m 41.566ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.380s 228.348us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 2.155m 8.647ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 2.155m 8.647ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 2.155m 8.647ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.615m 4.835ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 44.730s 2.717ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 2.155m 8.647ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 6.220m 11.588ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.615m 4.835ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 36.097m 485.888ms 1 10 10.00
V3 TOTAL 1 10 10.00
TOTAL 1132 1250 90.56

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 17 68.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.30 97.89 92.55 99.89 77.46 95.53 98.89 97.88

Failure Buckets

Past Results