c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.428m | 4.084ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.150s | 113.510us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.270s | 124.111us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.730s | 2.873ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 10.930s | 1.854ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.620s | 144.211us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.270s | 124.111us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 10.930s | 1.854ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.780s | 12.999us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.490s | 46.280us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 56.471m | 1.336s | 38 | 50 | 76.00 |
| V2 | burst_write | kmac_burst_write | 28.524m | 115.757ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 59.744m | 101.311ms | 36 | 50 | 72.00 |
| kmac_test_vectors_sha3_256 | 59.772m | 337.062ms | 45 | 50 | 90.00 | ||
| kmac_test_vectors_sha3_384 | 48.719m | 963.863ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 32.567m | 202.107ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_128 | 1.963h | 145.804ms | 20 | 50 | 40.00 | ||
| kmac_test_vectors_shake_256 | 1.649h | 883.148ms | 24 | 50 | 48.00 | ||
| kmac_test_vectors_kmac | 7.830s | 1.050ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.630s | 643.431us | 50 | 50 | 100.00 | ||
| V2 | sideload | kmac_sideload | 10.255m | 78.556ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.124m | 68.601ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.794m | 7.353ms | 9 | 10 | 90.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 8.691m | 345.470ms | 49 | 50 | 98.00 |
| V2 | error | kmac_error | 11.037m | 139.744ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 13.210s | 7.360ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 50.170s | 6.979ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 51.060s | 3.847ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.252m | 29.670ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 51.410s | 10.752ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 1.041h | 1.899s | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 0.960s | 17.127us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.900s | 49.497us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.270s | 503.768us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.270s | 503.768us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.150s | 113.510us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.270s | 124.111us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.930s | 1.854ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.820s | 318.398us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.150s | 113.510us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.270s | 124.111us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 10.930s | 1.854ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.820s | 318.398us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 960 | 1050 | 91.43 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.500s | 190.445us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.500s | 190.445us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.500s | 190.445us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.500s | 190.445us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.080s | 159.226us | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.925m | 9.941ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.910s | 997.693us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.910s | 997.693us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 51.410s | 10.752ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.428m | 4.084ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 10.255m | 78.556ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.500s | 190.445us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.925m | 9.941ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.925m | 9.941ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.925m | 9.941ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.428m | 4.084ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 51.410s | 10.752ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.925m | 9.941ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 8.947m | 200.000ms | 9 | 10 | 90.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.428m | 4.084ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 73 | 75 | 97.33 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 37.125m | 262.655ms | 4 | 10 | 40.00 |
| V3 | TOTAL | 4 | 10 | 40.00 | |||
| TOTAL | 1152 | 1250 | 92.16 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 17 | 68.00 |
| V2S | 5 | 5 | 3 | 60.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 94.25 | 97.91 | 92.65 | 99.89 | 76.76 | 95.59 | 99.05 | 97.88 |
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 85 failures:
0.kmac_test_vectors_sha3_224.27612072223942363514083065873078254156138818650380028483780856607108972623657
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:57fa0ab4-2e48-46b8-9774-e70a27a64a87
2.kmac_test_vectors_sha3_224.109866261884853805469890942812174437111380416835866050288567189540374977530762
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest/run.log
Job ID: smart:78e44e50-78df-4865-a74f-4e98ed71f5b7
... and 12 more failures.
0.kmac_test_vectors_shake_128.52424587109779140834899301026532489096260317781170500052801521810449698133458
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:1db4a2b2-201e-43b0-9caf-7f7eda086b42
1.kmac_test_vectors_shake_128.85883012639399746638402575565861240623892875734882002199117834886719705081900
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:dacc2144-46ed-430f-9f7f-162fd27baa6b
... and 27 more failures.
0.kmac_test_vectors_shake_256.22541834572344686484765565606645081586956687512000442214375740562736710404197
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:e88d1111-19f2-4b43-9ec8-cdffe8464452
1.kmac_test_vectors_shake_256.48285380668645854962262912089442969102311753637141174397930216388276869275365
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest/run.log
Job ID: smart:e8f002d0-aad5-4b8a-a965-b79b1cc6ecca
... and 24 more failures.
1.kmac_long_msg_and_output.110742096764164883022834835850800404325439946210144542261065851292538319212618
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
Job ID: smart:e2311376-7f50-4f26-9116-6eb7144061d1
2.kmac_long_msg_and_output.49223354659402117204713483693122464007325699575572899979050745659188439615616
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
Job ID: smart:699d3341-35c1-439b-a1d6-3301a09092a5
... and 10 more failures.
28.kmac_test_vectors_sha3_256.102796481235510940863383675417042350414515592684972119154770334596645708639286
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:3946fff5-07c3-4240-80f2-19ed9b29105d
30.kmac_test_vectors_sha3_256.59729551957481384379766416802411199424846249470124207019254734516642684441462
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_256/latest/run.log
Job ID: smart:28542211-903f-4ff5-85b9-4eb2ea2b2164
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
0.kmac_stress_all_with_rand_reset.69958999394752623730973387807056717324174409561807039298517761144575477351148
Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10279671369 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10279671369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.82101928376953896705086904121597866489571427285540282332079636908600911397166
Line 836, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 122260154366 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 122260154366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:
Test kmac_entropy_refresh has 1 failures.
1.kmac_entropy_refresh.83485686719319666939855781929257492328477369773792547812990794883755933479369
Line 885, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 50550932067 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (109 [0x6d] vs 73 [0x49]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 50550932067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app_with_partial_data has 1 failures.
9.kmac_app_with_partial_data.58344900601803833450772544624559901992674442058241930665445281537470624469979
Line 653, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest/run.log
UVM_FATAL @ 25299494209 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (154 [0x9a] vs 201 [0xc9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 25299494209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
9.kmac_stress_all_with_rand_reset.97842283743630358009448870668890667928952510301275125789745924226561630427732
Line 468, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 8066837370 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (88 [0x58] vs 111 [0x6f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 8066837370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
4.kmac_test_vectors_sha3_256.64423745124657323822099548713754652714914790569536982111072024635630808372950
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 27675031 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 27675031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
29.kmac_test_vectors_shake_128.96269313652671247794971245538981162958761694376894019217131864058176114402002
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 33271881 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 33271881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_512 has 1 failures.
42.kmac_test_vectors_sha3_512.13140390538920964392716483093705286606287630623932374782945657597281668945561
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 77354384 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 77354384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1188) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
2.kmac_stress_all_with_rand_reset.78203011929941617000937263535659319959122182489173096989542157586805580921541
Line 646, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74685672935 ps: (kmac_scoreboard.sv:1188) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
UVM_INFO @ 74685672935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
8.kmac_mubi.70829528423647746916355796869492625198242813820910486325710511662399583346610
Line 1102, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_mubi/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
16.kmac_shadow_reg_errors_with_csr_rw.12788822649760920556167780690326336632467500800880528865782955091689967305184
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 36588468 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (4271916323 [0xfea04523] vs 1598281359 [0x5f43d68f]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
UVM_INFO @ 36588468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---