KMAC/MASKED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 1.518m 19.721ms 50 50 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.200s 116.790us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.200s 89.422us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 15.650s 287.159us 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 9.820s 505.085us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.580s 447.456us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.200s 89.422us 20 20 100.00
kmac_csr_aliasing 9.820s 505.085us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.820s 13.415us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.500s 76.588us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 long_msg_and_output kmac_long_msg_and_output 59.692m 52.520ms 32 50 64.00
V2 burst_write kmac_burst_write 30.126m 65.123ms 50 50 100.00
V2 test_vectors kmac_test_vectors_sha3_224 59.867m 170.421ms 38 50 76.00
kmac_test_vectors_sha3_256 59.528m 149.408ms 47 50 94.00
kmac_test_vectors_sha3_384 48.710m 148.355ms 50 50 100.00
kmac_test_vectors_sha3_512 31.023m 206.180ms 50 50 100.00
kmac_test_vectors_shake_128 1.984h 246.182ms 12 50 24.00
kmac_test_vectors_shake_256 1.643h 116.372ms 22 50 44.00
kmac_test_vectors_kmac 8.660s 776.464us 50 50 100.00
kmac_test_vectors_kmac_xof 7.270s 2.029ms 49 50 98.00
V2 sideload kmac_sideload 10.964m 322.372ms 50 50 100.00
V2 app kmac_app 7.630m 28.774ms 50 50 100.00
V2 app_with_partial_data kmac_app_with_partial_data 5.995m 33.990ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 7.477m 47.298ms 50 50 100.00
V2 error kmac_error 10.141m 143.842ms 50 50 100.00
V2 key_error kmac_key_error 14.880s 6.447ms 50 50 100.00
V2 edn_timeout_error kmac_edn_timeout_error 42.350s 743.613us 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 52.410s 2.430ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.213m 6.950ms 10 10 100.00
V2 lc_escalation kmac_lc_escalation 47.430s 1.718ms 50 50 100.00
V2 stress_all kmac_stress_all 52.068m 66.599ms 49 50 98.00
V2 intr_test kmac_intr_test 0.880s 19.994us 50 50 100.00
V2 alert_test kmac_alert_test 0.940s 120.768us 50 50 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.660s 390.357us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.660s 390.357us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.200s 116.790us 5 5 100.00
kmac_csr_rw 1.200s 89.422us 20 20 100.00
kmac_csr_aliasing 9.820s 505.085us 5 5 100.00
kmac_same_csr_outstanding 2.720s 451.065us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.200s 116.790us 5 5 100.00
kmac_csr_rw 1.200s 89.422us 20 20 100.00
kmac_csr_aliasing 9.820s 505.085us 5 5 100.00
kmac_same_csr_outstanding 2.720s 451.065us 20 20 100.00
V2 TOTAL 949 1050 90.38
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.410s 82.635us 20 20 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.410s 82.635us 20 20 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.410s 82.635us 20 20 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.410s 82.635us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.110s 570.365us 20 20 100.00
V2S tl_intg_err kmac_sec_cm 1.504m 67.155ms 5 5 100.00
kmac_tl_intg_err 4.940s 807.015us 20 20 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.940s 807.015us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 47.430s 1.718ms 50 50 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 1.518m 19.721ms 50 50 100.00
V2S sec_cm_key_sideload kmac_sideload 10.964m 322.372ms 50 50 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.410s 82.635us 20 20 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.504m 67.155ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.504m 67.155ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.504m 67.155ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 1.518m 19.721ms 50 50 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 47.430s 1.718ms 50 50 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.504m 67.155ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 5.766m 4.985ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 1.518m 19.721ms 50 50 100.00
V2S TOTAL 75 75 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.449h 338.711ms 2 10 20.00
V3 TOTAL 2 10 20.00
TOTAL 1141 1250 91.28

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 25 25 18 72.00
V2S 5 5 5 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.27 97.91 92.58 99.54 77.46 95.59 99.05 97.73

Failure Buckets

Past Results