KMAC/UNMASKED Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.184m	4.227ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.160s	249.401us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	273.142us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.150s	6.748ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.790s	4.968ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.420s	33.504us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	273.142us	20	20	100.00
		kmac_csr_aliasing	10.790s	4.968ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	20.203us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	38.251us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.798m	245.546ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.959m	175.627ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.670m	1.388s	50	50	100.00
		kmac_test_vectors_sha3_256	37.420m	1.518s	50	50	100.00
		kmac_test_vectors_sha3_384	25.791m	421.589ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.657m	607.010ms	50	50	100.00
		kmac_test_vectors_shake_128	1.513h	1.074s	50	50	100.00
		kmac_test_vectors_shake_256	1.256h	918.158ms	50	50	100.00
		kmac_test_vectors_kmac	5.890s	511.240us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.920s	3.960ms	50	50	100.00
V2	sideload	kmac_sideload	6.338m	78.481ms	50	50	100.00
V2	app	kmac_app	5.288m	12.578ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.941m	57.898ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.410m	18.112ms	48	50	96.00
V2	error	kmac_error	7.593m	42.218ms	50	50	100.00
V2	key_error	kmac_key_error	7.510s	13.195ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.140s	12.502ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.630s	4.294ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.268m	28.312ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.820s	1.549ms	50	50	100.00
V2	stress_all	kmac_stress_all	24.588m	105.925ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.850s	20.365us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	20.213us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.860s	198.986us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.860s	198.986us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.160s	249.401us	5	5	100.00
		kmac_csr_rw	1.180s	273.142us	20	20	100.00
		kmac_csr_aliasing	10.790s	4.968ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	145.857us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.160s	249.401us	5	5	100.00
		kmac_csr_rw	1.180s	273.142us	20	20	100.00
		kmac_csr_aliasing	10.790s	4.968ms	5	5	100.00
		kmac_same_csr_outstanding	2.900s	145.857us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.180s	169.758us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.180s	169.758us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.180s	169.758us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.180s	169.758us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.700s	491.982us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	55.910s	13.311ms	5	5	100.00
		kmac_tl_intg_err	5.690s	2.226ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.690s	2.226ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.820s	1.549ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.184m	4.227ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.338m	78.481ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.180s	169.758us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.910s	13.311ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.910s	13.311ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.910s	13.311ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.184m	4.227ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.820s	1.549ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.910s	13.311ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.137m	62.729ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.184m	4.227ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.941m	433.612ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1279	1290	99.15

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	22	88.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.76	96.65	92.52	100.00	90.91	94.67	98.82	96.74

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

Test kmac_stress_all_with_rand_reset has 5 failures.

0.kmac_stress_all_with_rand_reset.1189827116
Line 992, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 109845769939 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 109845769939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_stress_all_with_rand_reset.3062976510
Line 372, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17476402654 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17476402654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all has 1 failures.

4.kmac_stress_all.2627778648
Line 445, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 112433328088 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (68 [0x44] vs 217 [0xd9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 112433328088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

5.kmac_entropy_refresh.1243697346
Line 313, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 7328475148 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (83 [0x53] vs 28 [0x1c]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7328475148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

25.kmac_app.3286303874
Line 278, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 21816391509 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (23 [0x17] vs 211 [0xd3]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21816391509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

31.kmac_stress_all_with_rand_reset.4282722940
Line 478, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 4738616365 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (160 [0xa0] vs 194 [0xc2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4738616365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

39.kmac_stress_all_with_rand_reset.2502196964
Line 294, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/39.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5728834514 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_kmac_app_agent[2].m_data_push_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.kmac_entropy_refresh_vseq.kmac_app_seq.host_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5728834514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 47.kmac_entropy_refresh.1830410581
    Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```