KMAC/UNMASKED Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.403m	46.513ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.040s	35.890us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	116.986us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.760s	2.957ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.990s	2.364ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.980s	324.937us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	116.986us	20	20	100.00
		kmac_csr_aliasing	10.990s	2.364ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.720s	21.556us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.380s	131.339us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.790m	85.248ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.593m	34.144ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.792m	387.448ms	50	50	100.00
		kmac_test_vectors_sha3_256	35.234m	1.359s	50	50	100.00
		kmac_test_vectors_sha3_384	24.283m	371.740ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.768m	328.397ms	50	50	100.00
		kmac_test_vectors_shake_128	1.513h	1.695s	50	50	100.00
		kmac_test_vectors_shake_256	1.279h	868.693ms	50	50	100.00
		kmac_test_vectors_kmac	5.190s	374.748us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.290s	181.789us	50	50	100.00
V2	sideload	kmac_sideload	6.788m	40.007ms	49	50	98.00
V2	app	kmac_app	5.480m	64.297ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.220m	57.461ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.530m	93.343ms	49	50	98.00
V2	error	kmac_error	7.347m	130.304ms	48	50	96.00
V2	key_error	kmac_key_error	10.120s	14.936ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	36.760s	1.475ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	52.630s	44.149ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.043m	51.788ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.150s	766.135us	50	50	100.00
V2	stress_all	kmac_stress_all	34.436m	101.060ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.840s	48.726us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	76.580us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.050s	1.665ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.050s	1.665ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.040s	35.890us	5	5	100.00
		kmac_csr_rw	1.220s	116.986us	20	20	100.00
		kmac_csr_aliasing	10.990s	2.364ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	246.066us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.040s	35.890us	5	5	100.00
		kmac_csr_rw	1.220s	116.986us	20	20	100.00
		kmac_csr_aliasing	10.990s	2.364ms	5	5	100.00
		kmac_same_csr_outstanding	2.760s	246.066us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.360s	308.054us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.360s	308.054us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.360s	308.054us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.360s	308.054us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.310s	532.086us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.014m	17.691ms	5	5	100.00
		kmac_tl_intg_err	5.340s	255.775us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.340s	255.775us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.150s	766.135us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.403m	46.513ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.788m	40.007ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.360s	308.054us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.014m	17.691ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.014m	17.691ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.014m	17.691ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.403m	46.513ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.150s	766.135us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.014m	17.691ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.534m	13.294ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.403m	46.513ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.970m	289.452ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1263	1290	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	18	72.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.88	96.58	92.46	100.00	92.05	94.67	98.84	96.60

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 17 failures:
- Test kmac_stress_all_with_rand_reset has 17 failures.
  - 1.kmac_stress_all_with_rand_reset.99247234680306882209701466850073836517311258705155475603669599061357110126562
    Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 91347530887 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 91347530887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.59304312305172062280260941831906489094017173170981077893544538815088852878463
    Line 574, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57481318252 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 57481318252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test kmac_error has 2 failures.

2.kmac_error.6193031204467927394272466932345274736714217679792649016485553868493331831091
Line 347, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.kmac_error.71321320030928738790577845850083512611727958156898444512214519503189719670670
Line 389, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_error/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_burst_write has 2 failures.

20.kmac_burst_write.108785511267823956541735764582967412329271988104723267606047599438497089494489
Line 315, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/20.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_burst_write.24382132682314116602950427620501973061325272204103282348674949440065111757440
Line 340, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_sideload has 1 failures.

24.kmac_sideload.113953678072288954267888792992488012293710493544285095293261026283194338218256
Line 391, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_sideload/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 1 failures.

0.kmac_app.33280225422643955214237113993473977595371443779428617820255477919425483383785
Line 302, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app/latest/run.log

  UVM_FATAL @ 7120094396 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (168 [0xa8] vs 159 [0x9f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7120094396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

14.kmac_stress_all.1266446903577101450266871752470271958105634734921331780512723881787712969356
Line 279, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/14.kmac_stress_all/latest/run.log

  UVM_FATAL @ 551887255 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (58 [0x3a] vs 2 [0x2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 551887255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

31.kmac_entropy_refresh.36284289947092724344358707021029874657179664283222157729734195540051567031006
Line 362, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 9429716136 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (88 [0x58] vs 9 [0x9]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 9429716136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all_with_rand_reset has 1 failures.

44.kmac_stress_all_with_rand_reset.26179257225537051066343555990906303169840782996115477304778073471353507911414
Line 604, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 21711232974 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (230 [0xe6] vs 88 [0x58]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 21711232974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 41.kmac_key_error.4506500965395726709941949696477761824604055401833468686400521129075513025752
    Line 263, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 2897471697 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 2897471697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```