Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00			0.00	0.00		u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	0	0.00
ALWAYS	65	3	0	0.00
CONT_ASSIGN	72	1	0	0.00
ALWAYS	78	6	0	0.00
ALWAYS	90	5	0	0.00
ALWAYS	157	4	0	0.00
CONT_ASSIGN	165	1	0	0.00
CONT_ASSIGN	166	1	0	0.00
CONT_ASSIGN	170	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	174	1	0	0.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
ALWAYS	185	9	0	0.00
ALWAYS	214	8	0	0.00
ALWAYS	235	3	0	0.00
ALWAYS	243	14	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	291	0	0
CONT_ASSIGN	294	1	0	0.00
CONT_ASSIGN	295	1	0	0.00
CONT_ASSIGN	296	1	0	0.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	0	1
66	0	1
67	0	1
72	0	1
78	0	1
80	0	1
81	0	1
82	0	1
83	0	1
84	0	1
90	0	1
91	0	1
92	0	1
93	0	1
95	0	1
157	0	1
158	0	1
159	0	1
160	0	1
			==> MISSING_ELSE
165	0	1
166	0	1
170	0	1
171	0	1
174	0	1
175	0	1
178	0	1
180	0	1
185	0	1
187	0	1
188	0	1
192	0	1
193	0	1
197	0	1
198	0	1
202	0	1
203	0	1
214	0	1
215	0	1
216	0	1
217	0	1
218	0	1
219	0	1
221	0	1
222	0	1
235	0	1
236	0	1
238	0	1
243	0	1
245	0	1
246	0	1
248	0	1
250	0	1
251	0	1
253	0	1
258	0	1
259	0	1
261	0	1
262	0	1
264	0	1
266	0	1
267	0	1
279	0	1
283	0	1
291		unreachable
294	0	1
295	0	1
296	0	1
299		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 8'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 8'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       159
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       165
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       166
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       170
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       171
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       283
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Unreachable

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	0	0.00
TERNARY	170	2	0	0.00
TERNARY	171	2	0	0.00
TERNARY	283	1	0	0.00
IF	159	2	0	0.00
CASE	185	5	0	0.00
IF	214	3	0	0.00
IF	235	2	0	0.00
CASE	248	5	0	0.00
CASE	80	5	0	0.00
IF	90	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	171	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	283	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable
0	Not Covered

	LineNo.	Expression
-1-:	159	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	185	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Not Covered
2'b01	Not Covered
2'b10	Not Covered
2'b11	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	214	if ((!rst_ni))
-2-:	217	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	235	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	248	case (flush_st)
-2-:	250	if (flush_i)
-3-:	258	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Not Covered
FlushIdle	0	-	Not Covered
FlushSend	-	1	Not Covered
FlushSend	-	0	Not Covered
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Not Covered
2'b01	1	-	Not Covered
2'b01	0	-	Unreachable
2'b10	-	-	Not Covered
2'b11	-	1	Not Covered
2'b11	-	0	Unreachable
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered