Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[5].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[5].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[5].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[5].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		7	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	6