Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.11	0.00	0.00	5.54	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	1.74	0.00	0.00	8.70	0.00	0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.74	0.00	0.00	8.70	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
46.21	48.31	64.41	16.56	0.00	48.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	0.00	0.00	0.00			0.00
intr_kmac_done	0.00	0.00	0.00			0.00
intr_kmac_err	0.00	0.00	0.00			0.00
kmac_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_app_intf	0.00	0.00	0.00		0.00	0.00
u_errchk	0.00	0.00	0.00		0.00	0.00
u_kmac_core	0.00	0.00	0.00	0.00	0.00	0.00
u_msgfifo	0.00	0.00	0.00		0.00	0.00
u_prim_lc_sync	0.00	0.00				0.00
u_reg	94.28	98.97	96.31	77.47		98.63	100.00
u_sha3	0.00	0.00	0.00	0.00	0.00	0.00
u_sha3_done_sender	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00
u_staterd	0.00	0.00	0.00			0.00
u_tlul_adapter_msgfifo	0.00	0.00	0.00			0.00

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	0	0.00
ALWAYS	343	0	0
ALWAYS	343	2	0	0.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	423	1	0	0.00
ALWAYS	426	9	0	0.00
CONT_ASSIGN	461	1	0	0.00
CONT_ASSIGN	462	1	0	0.00
CONT_ASSIGN	463	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	470	1	0	0.00
CONT_ASSIGN	471	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
ALWAYS	485	6	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	515	1	0	0.00
CONT_ASSIGN	522	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	526	1	0	0.00
CONT_ASSIGN	527	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	532	1	0	0.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	0	0.00
CONT_ASSIGN	540	1	0	0.00
CONT_ASSIGN	542	1	0	0.00
CONT_ASSIGN	543	1	0	0.00
CONT_ASSIGN	546	1	0	0.00
CONT_ASSIGN	547	1	0	0.00
CONT_ASSIGN	550	1	0	0.00
ALWAYS	558	5	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	575	1	0	0.00
CONT_ASSIGN	576	1	0	0.00
CONT_ASSIGN	577	1	0	0.00
CONT_ASSIGN	585	1	0	0.00
CONT_ASSIGN	627	1	0	0.00
CONT_ASSIGN	633	1	0	0.00
CONT_ASSIGN	641	1	0	0.00
CONT_ASSIGN	646	1	0	0.00
ALWAYS	649	5	0	0.00
CONT_ASSIGN	678	1	0	0.00
CONT_ASSIGN	683	1	0	0.00
ALWAYS	686	7	0	0.00
CONT_ASSIGN	722	1	0	0.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	0	0.00
CONT_ASSIGN	744	1	0	0.00
ALWAYS	764	3	0	0.00
ALWAYS	768	28	0	0.00
CONT_ASSIGN	918	1	0	0.00
CONT_ASSIGN	921	1	0	0.00
CONT_ASSIGN	990	1	0	0.00
CONT_ASSIGN	992	1	0	0.00
CONT_ASSIGN	1022	1	0	0.00
CONT_ASSIGN	1027	1	0	0.00
CONT_ASSIGN	1028	1	0	0.00
CONT_ASSIGN	1030	1	0	0.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	0	0.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	0	0.00
CONT_ASSIGN	1306	1	0	0.00
CONT_ASSIGN	1316	1	0	0.00
CONT_ASSIGN	1317	1	0	0.00
CONT_ASSIGN	1323	1	0	0.00
CONT_ASSIGN	1324	1	0	0.00
CONT_ASSIGN	1325	1	0	0.00
CONT_ASSIGN	1326	1	0	0.00
CONT_ASSIGN	1329	1	0	0.00
CONT_ASSIGN	1338	1	0	0.00
CONT_ASSIGN	1380	1	0	0.00
CONT_ASSIGN	1394	1	0	0.00
CONT_ASSIGN	1401	1	0	0.00
CONT_ASSIGN	1406	1	0	0.00
ALWAYS	1412	6	0	0.00
CONT_ASSIGN	1421	1	0	0.00
CONT_ASSIGN	1423	1	0	0.00
ALWAYS	1435	4	0	0.00
CONT_ASSIGN	1441	1	0	0.00
ALWAYS	1464	4	0	0.00
ALWAYS	1474	3	0	0.00
CONT_ASSIGN	1485	1	0	0.00
CONT_ASSIGN	1489	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	0	1
344	0	1
349	0	1
418	0	1
419	0	1
423	0	1
426	0	1
427	0	1
428	0	1
429	0	1
431	0	1
433	0	1
437	0	1
441	0	1
445	0	1
461	0	1
462	0	1
463	0	1
466	0	1
470	0	1
471	0	1
475	0	1
478	0	1
485	0	1
486	0	1
487	0	1
488	0	1
489	0	1
490	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
510	0	1
515	0	1
522	0	1
525	0	1
526	0	1
527	0	1
529	0	1
530	0	1
532	0	1
534		unreachable
536	0	1
540	0	1
542	0	1
543	0	1
546	0	1
547	0	1
550	0	1
558	0	1
559	0	1
560	0	1
561	0	1
563	0	1
568	0	1
575	0	1
576	0	1
577	0	1
585	0	1
627	0	1
633	0	1
641	0	1
646	0	1
649	0	1
650	0	1
651	0	1
653	0	1
654	0	1
678	0	1
683	0	1
686	0	1
688	0	1
693	0	1
697	0	1
701	0	1
705	0	1
709	0	1
722	0	1
727	0	1
734	0	1
744	0	1
764	0	3
768	0	1
770	0	1
771	0	1
773	0	1
775	0	1
777	0	1
778	0	1
781	0	1
784	0	1
790	0	1
791	0	1
793	0	1
798	0	1
799	0	1
800	0	1
802	0	1
808	0	1
813	0	1
814	0	1
816	0	1
818	0	1
824	0	1
825	0	1
827	0	1
833	0	1
834	0	1
846	0	1
847	0	1
			==> MISSING_ELSE
918	0	1
921	0	1
990	0	1
992	0	1
1022	0	1
1027	0	1
1028	0	1
1030	0	1
1033		unreachable
1151	0	1
1152	0	1
1304	0	1
1305	0	1
1306	0	1
1316	0	1
1317	0	1
1323	0	1
1324	0	1
1325	0	1
1326	0	1
1329	0	1
1338	0	1
1380	0	1
1394	0	1
1401	0	1
1406	0	1
1412	0	1
1413	0	1
1414	0	1
1415	0	1
1416	0	1
1417	0	1
			==> MISSING_ELSE
1421	0	1
1423	0	1
1435	0	1
1436	0	1
1437	0	1
1438	0	1
			==> MISSING_ELSE
1441	0	1
1464	0	1
1465	0	1
1466	0	1
1468	0	1
			==> MISSING_ELSE
1474	0	1
1475	0	1
1478	0	1
1485	0	1
1489	0	1
1491	0	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	0	0.00
Logical	90	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	38	53.52
Total Bits	6534	362	5.54
Total Bits 0->1	3267	181	5.54
Total Bits 1->0	3267	181	5.54

Ports	71	38	53.52
Port Bits	6534	362	5.54
Port Bits 0->1	3267	181	5.54
Port Bits 1->0	3267	181	5.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
intr_fifo_empty_o	Yes	Yes	T6,T7,T9	Yes	T6,T7,T9	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Not Covered
KmacIdle	784	Not Covered
KmacKeyBlock	791	Not Covered
KmacMsgFeed	781	Not Covered
KmacPrefix	778	Not Covered
KmacTerminalError	833	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Not Covered
KmacDigest->KmacTerminalError	847	Not Covered
KmacIdle->KmacMsgFeed	781	Not Covered
KmacIdle->KmacPrefix	778	Not Covered
KmacIdle->KmacTerminalError	847	Not Covered
KmacKeyBlock->KmacMsgFeed	800	Not Covered
KmacKeyBlock->KmacTerminalError	847	Not Covered
KmacMsgFeed->KmacDigest	816	Not Covered
KmacMsgFeed->KmacIdle	813	Not Covered
KmacMsgFeed->KmacTerminalError	847	Not Covered
KmacPrefix->KmacKeyBlock	791	Not Covered
KmacPrefix->KmacMsgFeed	791	Not Covered
KmacPrefix->KmacTerminalError	847	Not Covered

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	0	0.00
TERNARY	423	2	0	0.00
TERNARY	633	4	0	0.00
TERNARY	641	4	0	0.00
TERNARY	646	2	0	0.00
CASE	431	6	0	0.00
IF	485	3	0	0.00
IF	558	3	0	0.00
IF	649	2	0	0.00
CASE	688	6	0	0.00
IF	764	2	0	0.00
CASE	773	15	0	0.00
IF	846	2	0	0.00
TERNARY	1152	2	0	0.00
IF	1412	4	0	0.00
IF	1435	3	0	0.00
IF	1464	3	0	0.00
IF	1474	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	0	0.00
ALWAYS	343	0	0
ALWAYS	343	2	0	0.00
ALWAYS	349	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	423	1	0	0.00
ALWAYS	426	9	0	0.00
CONT_ASSIGN	461	1	0	0.00
CONT_ASSIGN	462	1	0	0.00
CONT_ASSIGN	463	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	470	1	0	0.00
CONT_ASSIGN	471	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
ALWAYS	485	6	0	0.00
CONT_ASSIGN	510	1	0	0.00
CONT_ASSIGN	515	1	0	0.00
CONT_ASSIGN	522	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	526	1	0	0.00
CONT_ASSIGN	527	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	532	1	0	0.00
CONT_ASSIGN	534	0	0
CONT_ASSIGN	536	1	0	0.00
CONT_ASSIGN	540	1	0	0.00
CONT_ASSIGN	542	1	0	0.00
CONT_ASSIGN	543	1	0	0.00
CONT_ASSIGN	546	1	0	0.00
CONT_ASSIGN	547	1	0	0.00
CONT_ASSIGN	550	1	0	0.00
ALWAYS	558	5	0	0.00
CONT_ASSIGN	568	1	0	0.00
CONT_ASSIGN	575	1	0	0.00
CONT_ASSIGN	576	1	0	0.00
CONT_ASSIGN	577	1	0	0.00
CONT_ASSIGN	585	1	0	0.00
CONT_ASSIGN	627	1	0	0.00
CONT_ASSIGN	633	1	0	0.00
CONT_ASSIGN	641	1	0	0.00
CONT_ASSIGN	646	1	0	0.00
ALWAYS	649	5	0	0.00
CONT_ASSIGN	678	1	0	0.00
CONT_ASSIGN	683	1	0	0.00
ALWAYS	686	7	0	0.00
CONT_ASSIGN	722	1	0	0.00
CONT_ASSIGN	727	1	0	0.00
CONT_ASSIGN	734	1	0	0.00
CONT_ASSIGN	744	1	0	0.00
ALWAYS	764	3	0	0.00
ALWAYS	768	28	0	0.00
CONT_ASSIGN	918	1	0	0.00
CONT_ASSIGN	921	1	0	0.00
CONT_ASSIGN	990	1	0	0.00
CONT_ASSIGN	992	1	0	0.00
CONT_ASSIGN	1022	1	0	0.00
CONT_ASSIGN	1027	1	0	0.00
CONT_ASSIGN	1028	1	0	0.00
CONT_ASSIGN	1030	1	0	0.00
CONT_ASSIGN	1033	0	0
ALWAYS	1151	0	0
ALWAYS	1151	2	0	0.00
CONT_ASSIGN	1304	1	0	0.00
CONT_ASSIGN	1305	1	0	0.00
CONT_ASSIGN	1306	1	0	0.00
CONT_ASSIGN	1316	1	0	0.00
CONT_ASSIGN	1317	1	0	0.00
CONT_ASSIGN	1323	1	0	0.00
CONT_ASSIGN	1324	1	0	0.00
CONT_ASSIGN	1325	1	0	0.00
CONT_ASSIGN	1326	1	0	0.00
CONT_ASSIGN	1329	1	0	0.00
CONT_ASSIGN	1338	1	0	0.00
CONT_ASSIGN	1380	1	0	0.00
CONT_ASSIGN	1394	1	0	0.00
CONT_ASSIGN	1401	1	0	0.00
CONT_ASSIGN	1406	1	0	0.00
ALWAYS	1412	6	0	0.00
CONT_ASSIGN	1421	1	0	0.00
CONT_ASSIGN	1423	1	0	0.00
ALWAYS	1435	4	0	0.00
CONT_ASSIGN	1441	1	0	0.00
ALWAYS	1464	4	0	0.00
ALWAYS	1474	3	0	0.00
CONT_ASSIGN	1485	1	0	0.00
CONT_ASSIGN	1489	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00
CONT_ASSIGN	1491	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
343	0	1
344	0	1
349	0	1
418	0	1
419	0	1
423	0	1
426	0	1
427	0	1
428	0	1
429	0	1
431	0	1
433	0	1
437	0	1
441	0	1
445	0	1
461	0	1
462	0	1
463	0	1
466	0	1
470	0	1
471	0	1
475	0	1
478	0	1
485	0	1
486	0	1
487	0	1
488	0	1
489	0	1
490	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
510	0	1
515	0	1
522	0	1
525	0	1
526	0	1
527	0	1
529	0	1
530	0	1
532	0	1
534		unreachable
536	0	1
540	0	1
542	0	1
543	0	1
546	0	1
547	0	1
550	0	1
558	0	1
559	0	1
560	0	1
561	0	1
563	0	1
568	0	1
575	0	1
576	0	1
577	0	1
585	0	1
627	0	1
633	0	1
641	0	1
646	0	1
649	0	1
650	0	1
651	0	1
653	0	1
654	0	1
678	0	1
683	0	1
686	0	1
688	0	1
693	0	1
697	0	1
701	0	1
705	0	1
709	0	1
722	0	1
727	0	1
734	0	1
744	0	1
764	0	3
768	0	1
770	0	1
771	0	1
773	0	1
775	0	1
777	0	1
778	0	1
781	0	1
784	0	1
790	0	1
791	0	1
793	0	1
798	0	1
799	0	1
800	0	1
802	0	1
808	0	1
813	0	1
814	0	1
816	0	1
818	0	1
824	0	1
825	0	1
827	0	1
833	0	1
834	0	1
846	0	1
847	0	1
			==> MISSING_ELSE
918	0	1
921	0	1
990	0	1
992	0	1
1022	0	1
1027	0	1
1028	0	1
1030	0	1
1033		unreachable
1151	0	1
1152	0	1
1304	0	1
1305	0	1
1306	0	1
1316	0	1
1317	0	1
1323	0	1
1324	0	1
1325	0	1
1326	0	1
1329	0	1
1338	0	1
1380	0	1
1394	0	1
1401	0	1
1406	0	1
1412	0	1
1413	0	1
1414	0	1
1415	0	1
1416	0	1
1417	0	1
			==> MISSING_ELSE
1421	0	1
1423	0	1
1435	0	1
1436	0	1
1437	0	1
1438	0	1
			==> MISSING_ELSE
1441	0	1
1464	0	1
1465	0	1
1466	0	1
1468	0	1
			==> MISSING_ELSE
1474	0	1
1475	0	1
1478	0	1
1485	0	1
1489	0	1
1491	0	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	0	0.00
Logical	90	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       423
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       461
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       462
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       463
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       475
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       527
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       536
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       540
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       547
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       560
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       560
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       560
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       568
 EXPRESSION (reg2hw.cfg_shadowed.err_processed.q & reg2hw.cfg_shadowed.err_processed.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       627
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       633
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       633
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       633
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       641
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       646
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       678
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       722
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       734
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       775
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       777
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       791
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1022
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1152
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1394
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1423
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	38	59.38
Total Bits	4160	362	8.70
Total Bits 0->1	2080	181	8.70
Total Bits 1->0	2080	181	8.70

Ports	64	38	59.38
Port Bits	4160	362	8.70
Port Bits 0->1	2080	181	8.70
Port Bits 1->0	2080	181	8.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT
intr_fifo_empty_o	Yes	Yes	T6,T7,T9	Yes	T6,T7,T9	OUTPUT
intr_kmac_err_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	816	Not Covered
KmacIdle	784	Not Covered
KmacKeyBlock	791	Not Covered
KmacMsgFeed	781	Not Covered
KmacPrefix	778	Not Covered
KmacTerminalError	833	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	825	Not Covered
KmacDigest->KmacTerminalError	847	Not Covered
KmacIdle->KmacMsgFeed	781	Not Covered
KmacIdle->KmacPrefix	778	Not Covered
KmacIdle->KmacTerminalError	847	Not Covered
KmacKeyBlock->KmacMsgFeed	800	Not Covered
KmacKeyBlock->KmacTerminalError	847	Not Covered
KmacMsgFeed->KmacDigest	816	Not Covered
KmacMsgFeed->KmacIdle	813	Not Covered
KmacMsgFeed->KmacTerminalError	847	Not Covered
KmacPrefix->KmacKeyBlock	791	Not Covered
KmacPrefix->KmacMsgFeed	791	Not Covered
KmacPrefix->KmacTerminalError	847	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	0	0.00
TERNARY	423	2	0	0.00
TERNARY	633	4	0	0.00
TERNARY	641	4	0	0.00
TERNARY	646	2	0	0.00
CASE	431	6	0	0.00
IF	485	3	0	0.00
IF	558	3	0	0.00
IF	649	2	0	0.00
CASE	688	6	0	0.00
IF	764	2	0	0.00
CASE	773	15	0	0.00
IF	846	2	0	0.00
TERNARY	1152	2	0	0.00
IF	1412	4	0	0.00
IF	1435	3	0	0.00
IF	1464	3	0	0.00
IF	1474	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	423	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	633	(msgfifo_full) ? 
-2-:	633	(msgfifo_empty_negedge) ? 
-3-:	633	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	641	(app_active) ? 
-2-:	641	((sha3_fsm != StAbsorb)) ? 
-3-:	641	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	646	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	431	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	485	if ((!rst_ni))
-2-:	487	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	558	if ((!rst_ni))
-2-:	560	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	649	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	688	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	764	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	773	case (kmac_st)
-2-:	775	if ((kmac_cmd == CmdStart))
-3-:	777	if ((CShake == app_sha3_mode))
-4-:	790	if (sha3_block_processed)
-5-:	791	(app_kmac_en) ? 
-6-:	799	if (sha3_block_processed)
-7-:	808	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	814	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	824	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	846	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1152	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1412	if ((!rst_ni))
-2-:	1414	if (alert_recov_operation)
-3-:	1416	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1435	if ((!rst_ni))
-2-:	1437	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1464	if ((!rst_ni))
-2-:	1466	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1474	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered