Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1317000	2898	0	0
entropy_period_rd_A	1317000	1527	0	0
intr_enable_rd_A	1317000	2117	0	0
prefix_0_rd_A	1317000	1634	0	0
prefix_10_rd_A	1317000	1637	0	0
prefix_1_rd_A	1317000	1714	0	0
prefix_2_rd_A	1317000	1755	0	0
prefix_3_rd_A	1317000	1638	0	0
prefix_4_rd_A	1317000	1652	0	0
prefix_5_rd_A	1317000	1561	0	0
prefix_6_rd_A	1317000	1687	0	0
prefix_7_rd_A	1317000	1659	0	0
prefix_8_rd_A	1317000	1629	0	0
prefix_9_rd_A	1317000	1649	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	2898	0	0
T2	5344	1	0	0
T3	9419	0	0	0
T4	2614	38	0	0
T5	2423	3	0	0
T6	1178	0	0	0
T7	1265	0	0	0
T9	1187	0	0	0
T10	2070	0	0	0
T11	26046	0	0	0
T12	6161	94	0	0
T14	0	194	0	0
T15	0	162	0	0
T16	0	25	0	0
T23	0	3	0	0
T24	0	1	0	0
T25	0	5	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1527	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	193	0	0
T12	6161	2	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	9	0	0
T21	2342	0	0	0
T22	10471	44	0	0
T28	0	30	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	3	0	0
T54	0	8	0	0
T68	0	16	0	0
T69	0	53	0	0
T70	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	2117	0	0
T7	1265	10	0	0
T8	1853	17	0	0
T9	1187	0	0	0
T11	26046	205	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	1	0	0
T21	2342	0	0	0
T22	10471	13	0	0
T28	0	8	0	0
T33	1032	0	0	0
T53	0	20	0	0
T54	0	2	0	0
T71	0	2	0	0
T72	0	8	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1634	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	222	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	8	0	0
T21	2342	0	0	0
T22	10471	39	0	0
T28	0	24	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	19	0	0
T54	0	16	0	0
T57	0	8	0	0
T68	0	5	0	0
T69	0	40	0	0
T70	0	8	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1637	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	198	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T15	0	4	0	0
T18	0	6	0	0
T21	2342	0	0	0
T22	10471	33	0	0
T28	0	53	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	14	0	0
T54	0	7	0	0
T57	0	1	0	0
T68	0	4	0	0
T69	0	26	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1714	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	198	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	5	0	0
T21	2342	0	0	0
T22	10471	27	0	0
T28	0	100	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	5	0	0
T54	0	9	0	0
T56	0	68	0	0
T57	0	2	0	0
T69	0	65	0	0
T70	0	6	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1755	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	205	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	5	0	0
T21	2342	0	0	0
T22	10471	13	0	0
T28	0	67	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	9	0	0
T54	0	6	0	0
T57	0	9	0	0
T68	0	4	0	0
T69	0	31	0	0
T70	0	5	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1638	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	193	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	4	0	0
T21	2342	0	0	0
T22	10471	24	0	0
T28	0	69	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	6	0	0
T54	0	12	0	0
T56	0	42	0	0
T68	0	6	0	0
T69	0	35	0	0
T70	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1652	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	215	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	11	0	0
T21	2342	0	0	0
T22	10471	2	0	0
T28	0	16	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	9	0	0
T54	0	10	0	0
T57	0	5	0	0
T68	0	4	0	0
T69	0	57	0	0
T70	0	2	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1561	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	221	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	9	0	0
T21	2342	0	0	0
T22	10471	30	0	0
T28	0	7	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	8	0	0
T54	0	5	0	0
T57	0	7	0	0
T68	0	6	0	0
T69	0	35	0	0
T70	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1687	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	235	0	0
T12	6161	2	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	8	0	0
T21	2342	0	0	0
T22	10471	11	0	0
T28	0	57	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	7	0	0
T54	0	4	0	0
T68	0	7	0	0
T69	0	48	0	0
T70	0	3	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1659	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	201	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T15	0	1	0	0
T18	0	4	0	0
T21	2342	0	0	0
T22	10471	0	0	0
T28	0	49	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	10	0	0
T54	0	13	0	0
T57	0	14	0	0
T68	0	4	0	0
T69	0	48	0	0
T70	0	8	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1629	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	206	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	10	0	0
T21	2342	0	0	0
T22	10471	17	0	0
T28	0	47	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	2	0	0
T54	0	7	0	0
T57	0	9	0	0
T68	0	3	0	0
T69	0	48	0	0
T70	0	7	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1317000	1649	0	0
T8	1853	0	0	0
T9	1187	0	0	0
T11	26046	236	0	0
T12	6161	0	0	0
T13	3019	0	0	0
T14	9006	0	0	0
T18	0	13	0	0
T21	2342	0	0	0
T22	10471	27	0	0
T28	0	69	0	0
T33	1032	0	0	0
T34	868	0	0	0
T53	0	3	0	0
T54	0	6	0	0
T56	0	74	0	0
T57	0	3	0	0
T68	0	2	0	0
T69	0	40	0	0