KMAC/UNMASKED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.720s	3.691ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	139.836us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	249.346us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.350s	4.612ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.380s	866.791us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	335.872us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	249.346us	20	20	100.00
		kmac_csr_aliasing	9.380s	866.791us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	127.269us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.480s	47.083us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	45.096m	988.144ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.187m	200.000ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.612m	403.177ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.260m	1.562s	50	50	100.00
		kmac_test_vectors_sha3_384	27.097m	957.917ms	50	50	100.00
		kmac_test_vectors_sha3_512	19.356m	859.618ms	50	50	100.00
		kmac_test_vectors_shake_128	1.811h	4.288s	50	50	100.00
		kmac_test_vectors_shake_256	1.315h	1.547s	50	50	100.00
		kmac_test_vectors_kmac	5.270s	245.285us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.560s	285.182us	50	50	100.00
V2	sideload	kmac_sideload	6.828m	88.786ms	50	50	100.00
V2	app	kmac_app	5.755m	84.327ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.897m	25.388ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.661m	36.493ms	50	50	100.00
V2	error	kmac_error	6.559m	176.341ms	50	50	100.00
V2	key_error	kmac_key_error	6.990s	4.092ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.850s	1.621ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.470s	4.323ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.229m	77.062ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	47.730s	828.713us	50	50	100.00
V2	stress_all	kmac_stress_all	44.471m	129.633ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	19.537us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	72.496us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.590s	871.054us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.590s	871.054us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	139.836us	5	5	100.00
		kmac_csr_rw	1.180s	249.346us	20	20	100.00
		kmac_csr_aliasing	9.380s	866.791us	5	5	100.00
		kmac_same_csr_outstanding	2.680s	417.172us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	139.836us	5	5	100.00
		kmac_csr_rw	1.180s	249.346us	20	20	100.00
		kmac_csr_aliasing	9.380s	866.791us	5	5	100.00
		kmac_same_csr_outstanding	2.680s	417.172us	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	773.207us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	773.207us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	773.207us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	773.207us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.990s	512.317us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.508m	43.641ms	5	5	100.00
		kmac_tl_intg_err	5.250s	1.407ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.250s	1.407ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	47.730s	828.713us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.720s	3.691ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.828m	88.786ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	773.207us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.508m	43.641ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.508m	43.641ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.508m	43.641ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.720s	3.691ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	47.730s	828.713us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.508m	43.641ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.186m	36.626ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.720s	3.691ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	36.967m	165.991ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			1248	1290	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.35	96.18	92.44	100.00	88.64	94.60	98.84	96.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:

  • Test kmac_stress_all_with_rand_reset has 35 failures.

    • 0.kmac_stress_all_with_rand_reset.92262395499702123411041215352738710822400499798098359075410845247240752820321
      Line 570, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9166120793 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9166120793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.40557365951872349773446038767013700703037328839056657990376515872316051506581
      Line 3022, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 368293290706 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 368293290706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 33 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:

  • Test kmac_stress_all_with_rand_reset has 4 failures.

    • 11.kmac_stress_all_with_rand_reset.78665871241324879236872045271719711750540603621694882902377540643341912177482
      Line 3460, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 165991367481 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 165991367481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.kmac_stress_all_with_rand_reset.23101020669862464728910561036238390163551451938903806200389510740329755482062
      Line 294, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1026974426 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1026974426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test kmac_burst_write has 2 failures.

    • 4.kmac_burst_write.50275046616592052273644960090867447707365524755867385950143802718408047744810
      Line 1232, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.kmac_burst_write.102155290256023582188886971047194228232296197036967138683275970978576808600110
      Line 776, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:

  • Test kmac_app has 1 failures.

    • 18.kmac_app.9222561807313053871844239489773965769207268549975908138403367398679424907985
      Line 309, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_app/latest/run.log

        UVM_FATAL @ 1090655022 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (250 [0xfa] vs 241 [0xf1]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 1090655022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.22_07.24.19
• 2024.04.19_05.05.30
• 2024.04.17_05.11.26
• 2024.04.16_04.11.25
• 2024.04.12_19.14.08
• 2024.04.08_19.16.41
• 2024.04.05_04.21.30