KMAC/UNMASKED Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.102m	7.754ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	57.970us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.200s	223.993us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.300s	3.857ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.310s	490.831us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.450s	314.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.200s	223.993us	20	20	100.00
		kmac_csr_aliasing	9.310s	490.831us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.780s	32.196us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	78.802us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.267m	247.403ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.573m	149.414ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.920m	514.647ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.466m	691.355ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.410m	74.118ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.034m	243.877ms	50	50	100.00
		kmac_test_vectors_shake_128	1.493h	1.024s	50	50	100.00
		kmac_test_vectors_shake_256	1.200h	226.481ms	50	50	100.00
		kmac_test_vectors_kmac	5.790s	264.726us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.720s	1.085ms	50	50	100.00
V2	sideload	kmac_sideload	8.288m	90.453ms	50	50	100.00
V2	app	kmac_app	5.587m	65.890ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.996m	24.846ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.842m	83.415ms	50	50	100.00
V2	error	kmac_error	7.056m	68.311ms	50	50	100.00
V2	key_error	kmac_key_error	10.460s	20.819ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.120s	1.015ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	40.690s	7.958ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.094m	28.850ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.130s	2.965ms	50	50	100.00
V2	stress_all	kmac_stress_all	38.024m	149.234ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.850s	148.632us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	61.384us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.470s	619.625us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.470s	619.625us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	57.970us	5	5	100.00
		kmac_csr_rw	1.200s	223.993us	20	20	100.00
		kmac_csr_aliasing	9.310s	490.831us	5	5	100.00
		kmac_same_csr_outstanding	2.690s	431.719us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	57.970us	5	5	100.00
		kmac_csr_rw	1.200s	223.993us	20	20	100.00
		kmac_csr_aliasing	9.310s	490.831us	5	5	100.00
		kmac_same_csr_outstanding	2.690s	431.719us	20	20	100.00
V2		TOTAL			1049	1050	99.90
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.300s	44.247us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.300s	44.247us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.300s	44.247us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.300s	44.247us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.150s	1.089ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	47.370s	14.831ms	5	5	100.00
		kmac_tl_intg_err	5.370s	440.637us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.370s	440.637us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.130s	2.965ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.102m	7.754ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.288m	90.453ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.300s	44.247us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	47.370s	14.831ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	47.370s	14.831ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	47.370s	14.831ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.102m	7.754ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.130s	2.965ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	47.370s	14.831ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.625m	68.055ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.102m	7.754ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.414m	103.012ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			1249	1290	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.41	96.18	92.13	100.00	89.77	94.52	98.84	96.45

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
  • Test kmac_stress_all_with_rand_reset has 37 failures.

    • 0.kmac_stress_all_with_rand_reset.15778836516892860885562157123952518575488978487992892716032137185092870090388
      Line 861, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111592728291 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 111592728291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.82266690697516598654144735725133482124368947922285726268078867264273944320382
      Line 1596, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66047885711 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 66047885711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 35 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
  • Test kmac_stress_all_with_rand_reset has 3 failures.

    • 15.kmac_stress_all_with_rand_reset.19693092840355811042995108784700267908816562715606309051626829082719893612142
      Line 399, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20496623405 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 20496623405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.kmac_stress_all_with_rand_reset.101726743423693060999197442426577656078419753423003282224597941366170356396311
      Line 1357, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 93471014021 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 93471014021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
  • Test kmac_stress_all has 1 failures.

    • 23.kmac_stress_all.16489169454323537507932194387411409445255765667312821099997351813029520745510
      Line 1111, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/23.kmac_stress_all/latest/run.log

        UVM_FATAL @ 14553399854 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (101 [0x65] vs 93 [0x5d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 14553399854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.04.03_03.40.12
• 2024.04.01_04.36.51
• 2024.03.29_04.05.36
• 2024.03.27_04.39.05
• 2024.03.25_03.57.28
• 2024.03.22_04.35.36
• 2024.03.20_03.38.50