KMAC/UNMASKED Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.221m	15.778ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	27.523us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.150s	37.064us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.010s	978.028us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.580s	461.119us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.650s	135.405us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.150s	37.064us	20	20	100.00
		kmac_csr_aliasing	8.580s	461.119us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.710s	37.935us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.190s	62.129us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	50.104m	570.156ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.240m	38.217ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.658m	1.595s	50	50	100.00
		kmac_test_vectors_sha3_256	33.088m	96.040ms	50	50	100.00
		kmac_test_vectors_sha3_384	27.227m	639.538ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.733m	197.962ms	50	50	100.00
		kmac_test_vectors_shake_128	1.528h	532.054ms	50	50	100.00
		kmac_test_vectors_shake_256	1.539h	4.356s	50	50	100.00
		kmac_test_vectors_kmac	5.570s	1.706ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.790s	1.994ms	50	50	100.00
V2	sideload	kmac_sideload	7.607m	182.364ms	49	50	98.00
V2	app	kmac_app	5.243m	65.768ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.345m	27.088ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.428m	16.209ms	48	50	96.00
V2	error	kmac_error	6.407m	86.210ms	50	50	100.00
V2	key_error	kmac_key_error	8.520s	14.137ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	31.560s	1.883ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.480s	10.561ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.214m	17.361ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	32.180s	8.356ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.748m	95.579ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	14.620us	50	50	100.00
V2	alert_test	kmac_alert_test	0.900s	69.118us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.430s	55.184us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.430s	55.184us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	27.523us	5	5	100.00
		kmac_csr_rw	1.150s	37.064us	20	20	100.00
		kmac_csr_aliasing	8.580s	461.119us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	193.524us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	27.523us	5	5	100.00
		kmac_csr_rw	1.150s	37.064us	20	20	100.00
		kmac_csr_aliasing	8.580s	461.119us	5	5	100.00
		kmac_same_csr_outstanding	2.700s	193.524us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.560s	269.030us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.560s	269.030us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.560s	269.030us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.560s	269.030us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.010s	434.941us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.413m	36.220ms	5	5	100.00
		kmac_tl_intg_err	5.040s	285.376us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.040s	285.376us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	32.180s	8.356ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.221m	15.778ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.607m	182.364ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.560s	269.030us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.413m	36.220ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.413m	36.220ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.413m	36.220ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.221m	15.778ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	32.180s	8.356ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.413m	36.220ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.290m	68.333ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.221m	15.778ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.107h	490.671ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			1250	1290	96.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	96.18	92.17	100.00	89.77	94.52	98.84	96.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:

  • Test kmac_stress_all_with_rand_reset has 28 failures.

    • 0.kmac_stress_all_with_rand_reset.19305987464700791331846899068941079141466447200949564958705728135973428295341
      Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 614024402 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 614024402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.kmac_stress_all_with_rand_reset.81285215002979947809197210189415963015162886442346495839103640704577415716017
      Line 2895, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 97018207542 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 97018207542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:

  • Test kmac_stress_all_with_rand_reset has 6 failures.

    • 1.kmac_stress_all_with_rand_reset.49677851453212689829500866409768758915075571215277268730084533278559629748797
      Line 1109, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 540159125153 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 540159125153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.kmac_stress_all_with_rand_reset.52106371719799637997312093949114114341777441223746184614931611378422423952876
      Line 913, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42592213813 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 42592213813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test kmac_sideload has 1 failures.

    • 11.kmac_sideload.98575488982354440654151545493598307223066690285973040940129222371185053729378
      Line 873, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/11.kmac_sideload/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_burst_write has 2 failures.

    • 18.kmac_burst_write.72056696025141023381103470802484853229350318164426334691502666262896890361625
      Line 802, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/18.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 44.kmac_burst_write.110305408209511521498376925675738327416731629236133703107920223582615814100379
      Line 720, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/44.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_entropy_refresh has 1 failures.

    • 31.kmac_entropy_refresh.18344320496359651680309754151943353924893714479694318274924821892405195923585
      Line 1054, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_app has 1 failures.

    • 10.kmac_app.30601777670288126042850280777713504021903447734724459077208632350640291713225
      Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/10.kmac_app/latest/run.log

        UVM_FATAL @ 102638411 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (44 [0x2c] vs 240 [0xf0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 102638411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_entropy_refresh has 1 failures.

    • 24.kmac_entropy_refresh.51522526351818033860546785399568925894692963883414652435866761971586876855184
      Line 841, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/24.kmac_entropy_refresh/latest/run.log

        UVM_FATAL @ 52879906370 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (131 [0x83] vs 189 [0xbd]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 52879906370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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