KMAC/UNMASKED Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.227m	15.377ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	169.300us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	122.642us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	25.840s	17.983ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.710s	2.064ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	396.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	122.642us	20	20	100.00
		kmac_csr_aliasing	9.710s	2.064ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.740s	18.629us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	36.088us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.692m	506.855ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.485m	35.762ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.508m	388.142ms	50	50	100.00
		kmac_test_vectors_sha3_256	31.664m	380.026ms	50	50	100.00
		kmac_test_vectors_sha3_384	23.744m	302.691ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.587m	964.740ms	50	50	100.00
		kmac_test_vectors_shake_128	1.617h	3.438s	50	50	100.00
		kmac_test_vectors_shake_256	1.465h	2.446s	50	50	100.00
		kmac_test_vectors_kmac	5.490s	2.447ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.240s	2.714ms	50	50	100.00
V2	sideload	kmac_sideload	7.166m	41.825ms	50	50	100.00
V2	app	kmac_app	4.925m	17.302ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.670m	17.123ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.596m	81.590ms	48	50	96.00
V2	error	kmac_error	6.543m	79.099ms	50	50	100.00
V2	key_error	kmac_key_error	8.430s	15.857ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.740s	2.101ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.090s	2.750ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.198m	8.592ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	43.660s	2.000ms	50	50	100.00
V2	stress_all	kmac_stress_all	36.576m	223.383ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	20.106us	50	50	100.00
V2	alert_test	kmac_alert_test	0.840s	70.694us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	138.415us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	138.415us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	169.300us	5	5	100.00
		kmac_csr_rw	1.190s	122.642us	20	20	100.00
		kmac_csr_aliasing	9.710s	2.064ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	1.123ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	169.300us	5	5	100.00
		kmac_csr_rw	1.190s	122.642us	20	20	100.00
		kmac_csr_aliasing	9.710s	2.064ms	5	5	100.00
		kmac_same_csr_outstanding	2.990s	1.123ms	20	20	100.00
V2		TOTAL			1047	1050	99.71
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.610s	105.630us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.610s	105.630us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.610s	105.630us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.610s	105.630us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.730s	100.818us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.022m	5.579ms	5	5	100.00
		kmac_tl_intg_err	4.880s	1.013ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.880s	1.013ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	43.660s	2.000ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.227m	15.377ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.166m	41.825ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.610s	105.630us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.022m	5.579ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.022m	5.579ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.022m	5.579ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.227m	15.377ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	43.660s	2.000ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.022m	5.579ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.371m	14.790ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.227m	15.377ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.486m	963.318ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1244	1290	96.43

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.60	96.18	92.13	100.00	90.91	94.52	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:
- Test kmac_stress_all_with_rand_reset has 38 failures.
  - 0.kmac_stress_all_with_rand_reset.1444925914313338122119113043220481471076338427877832102209987186319102062403
    Line 956, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 146266459543 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 146266459543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.23878742161940904955825087801596546985904312708001426458143977246784239392073
    Line 1044, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26195332169 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26195332169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 36 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 1.kmac_stress_all_with_rand_reset.67720172455322310979621750298002330572179296400618043471927155035046299158278
    Line 1989, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18820528515 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 18820528515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.29380243814080592789393700167161973802515117940151467377153191727439058242879
    Line 304, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6137522786 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6137522786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 3 failures:

Test kmac_entropy_refresh has 2 failures.

8.kmac_entropy_refresh.44681982423719771891054307846073717201841699672945343605632180981597725194475
Line 503, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 23289499325 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (213 [0xd5] vs 133 [0x85]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 23289499325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_entropy_refresh.105700765441719334135980177330805720231048736174004432760508639267360859205556
Line 335, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1355767472 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (155 [0x9b] vs 207 [0xcf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1355767472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

41.kmac_stress_all.33648379073937585290659432607534859054866260277643707770066758815498538810566
Line 1055, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_stress_all/latest/run.log

  UVM_FATAL @ 14084260400 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (183 [0xb7] vs 96 [0x60]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 14084260400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---