1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | kmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | kmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | kmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 0 | 20 | 0.00 | ||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | kmac_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | kmac_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 115 | 0.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 0 | 50 | 0.00 | ||
| V2 | burst_write | kmac_burst_write | 0 | 50 | 0.00 | ||
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 0 | 50 | 0.00 | ||
| kmac_test_vectors_sha3_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_384 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_sha3_512 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_128 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_shake_256 | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac | 0 | 50 | 0.00 | ||||
| kmac_test_vectors_kmac_xof | 0 | 50 | 0.00 | ||||
| V2 | sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2 | app | kmac_app | 0 | 50 | 0.00 | ||
| V2 | app_with_partial_data | kmac_app_with_partial_data | 0 | 10 | 0.00 | ||
| V2 | entropy_refresh | kmac_entropy_refresh | 0 | 50 | 0.00 | ||
| V2 | error | kmac_error | 0 | 50 | 0.00 | ||
| V2 | key_error | kmac_key_error | 0 | 50 | 0.00 | ||
| V2 | edn_timeout_error | kmac_edn_timeout_error | 0 | 20 | 0.00 | ||
| V2 | entropy_mode_error | kmac_entropy_mode_error | 0 | 20 | 0.00 | ||
| V2 | entropy_ready_error | kmac_entropy_ready_error | 0 | 10 | 0.00 | ||
| V2 | lc_escalation | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2 | stress_all | kmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | kmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | alert_test | kmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | kmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| kmac_csr_rw | 0 | 20 | 0.00 | ||||
| kmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| kmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1050 | 0.00 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | kmac_sec_cm | 0 | 5 | 0.00 | ||
| kmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sideload | kmac_sideload | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 0 | 50 | 0.00 | ||
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 0 | 10 | 0.00 | ||
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 0 | 75 | 0.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 1290 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 0 | 0.00 |
| V2 | 25 | 25 | 0 | 0.00 |
| V2S | 5 | 5 | 0 | 0.00 |
| V3 | 2 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 1290 failures:
0.kmac_smoke.102056878064108636581083025580820813911285693692593819674011384676670475611745
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_smoke/latest/run.log
1.kmac_smoke.9760097173411410513602989795572374866058422134299239458614550528289725834118
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_smoke/latest/run.log
... and 48 more failures.
0.kmac_long_msg_and_output.110482656021959337779963259977208780327411056226478753502521722968472969226894
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest/run.log
1.kmac_long_msg_and_output.59337773420194206419734251955230637217243204718886623147830916118979745310600
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_long_msg_and_output/latest/run.log
... and 48 more failures.
0.kmac_sideload.56162264881286197466729167986075399184718571281870489610878942172076471747498
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_sideload/latest/run.log
1.kmac_sideload.5547212230337608702392840414627073175550104925401879389937801992830197861663
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_sideload/latest/run.log
... and 48 more failures.
0.kmac_burst_write.14161324831055464992178616209830393352922935036782163723192960040914764815337
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest/run.log
1.kmac_burst_write.51003419932863763929118318018343114030354176975357231123297214424305319629431
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_burst_write/latest/run.log
... and 48 more failures.
0.kmac_test_vectors_sha3_224.11136001060755914843988910602313666501806687490101934046157622691125569542811
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log
1.kmac_test_vectors_sha3_224.37025428180373683178153683687102578488152545332508211028408625910429491559532
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_test_vectors_sha3_224/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/cov_report/cov_report.log