KMAC/UNMASKED Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.660s	7.000ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.180s	33.158us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	27.169us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.730s	603.819us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.290s	513.062us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.570s	77.280us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	27.169us	20	20	100.00
		kmac_csr_aliasing	7.290s	513.062us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	10.463us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	133.979us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.137m	344.361ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.978m	98.390ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.154m	395.470ms	50	50	100.00
		kmac_test_vectors_sha3_256	33.756m	414.924ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.693m	145.933ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.835m	57.764ms	50	50	100.00
		kmac_test_vectors_shake_128	1.658h	2.189s	50	50	100.00
		kmac_test_vectors_shake_256	1.374h	1.866s	50	50	100.00
		kmac_test_vectors_kmac	5.620s	4.231ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.480s	2.018ms	50	50	100.00
V2	sideload	kmac_sideload	7.207m	80.335ms	50	50	100.00
V2	app	kmac_app	5.038m	54.362ms	46	50	92.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.066m	27.722ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.316m	69.634ms	50	50	100.00
V2	error	kmac_error	6.822m	88.451ms	48	50	96.00
V2	key_error	kmac_key_error	6.610s	3.905ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.210s	2.340ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.450s	6.949ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.340s	23.892ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.650s	870.692us	50	50	100.00
V2	stress_all	kmac_stress_all	33.511m	61.205ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.850s	81.795us	50	50	100.00
V2	alert_test	kmac_alert_test	0.880s	95.220us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.110s	51.762us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.110s	51.762us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.180s	33.158us	5	5	100.00
		kmac_csr_rw	1.180s	27.169us	20	20	100.00
		kmac_csr_aliasing	7.290s	513.062us	5	5	100.00
		kmac_same_csr_outstanding	2.510s	344.519us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.180s	33.158us	5	5	100.00
		kmac_csr_rw	1.180s	27.169us	20	20	100.00
		kmac_csr_aliasing	7.290s	513.062us	5	5	100.00
		kmac_same_csr_outstanding	2.510s	344.519us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.310s	90.685us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.310s	90.685us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.310s	90.685us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.310s	90.685us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.070s	109.431us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.072m	4.433ms	5	5	100.00
		kmac_tl_intg_err	5.130s	1.111ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.130s	1.111ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.650s	870.692us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.660s	7.000ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.207m	80.335ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.310s	90.685us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.072m	4.433ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.072m	4.433ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.072m	4.433ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.660s	7.000ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.650s	870.692us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.072m	4.433ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.400m	15.261ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.660s	7.000ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	53.576m	618.921ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			1248	1290	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.65	96.18	92.44	100.00	90.91	94.60	98.84	96.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
- Test kmac_stress_all_with_rand_reset has 33 failures.
  - 0.kmac_stress_all_with_rand_reset.107822294700890946302745700836856208430119477249933785377011765070619618248394
    Line 413, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10356110729 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10356110729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.kmac_stress_all_with_rand_reset.8203002651235847787201172598283736110147738072228979785022063994499596100554
    Line 548, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20778625821 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20778625821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*]

has 4 failures:

Test kmac_app has 4 failures.

1.kmac_app.48543220934037601259174821441417244262341565886309269536044006253630842874733
Line 895, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_app/latest/run.log

  UVM_FATAL @ 22357411665 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (192 [0xc0] vs 213 [0xd5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 22357411665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_app.27248893723067958340848957831089591075106767218706118438159774544070548886858
Line 773, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_app/latest/run.log

  UVM_FATAL @ 10433828055 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (72 [0x48] vs 62 [0x3e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 10433828055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 9.kmac_stress_all_with_rand_reset.56099220805993676645186975983307464685503170598885993885882490172871240414124
    Line 632, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11841431140 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 11841431140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.kmac_stress_all_with_rand_reset.45249544133103357066157736730303243471827515642402372931471925170003768399876
    Line 275, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/35.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 670985234 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 670985234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 2 failures.
  - 6.kmac_error.89069041385138086871137146103223788882635878686133099939155146120079411596741
    Line 895, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.kmac_error.12243666960899891155181926973776429916536694527284286674280149826446831233229
    Line 813, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/47.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```