LC_CTRL Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	10.130s	145.155us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.070s	42.943us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.090s	57.424us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.920s	334.615us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.160s	16.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.480s	31.940us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.090s	57.424us	20	20	100.00
		lc_ctrl_csr_aliasing	1.160s	16.197us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	15.220s	151.481us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.220s	1.245ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	10.457us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.400s	102.760us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.430s	563.023us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_prog_failure	4.400s	102.760us	50	50	100.00
		lc_ctrl_errors	20.430s	563.023us	50	50	100.00
		lc_ctrl_security_escalation	15.870s	2.362ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.640m	4.921ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	33.520s	1.245ms	20	20	100.00
		lc_ctrl_jtag_errors	1.349m	5.807ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	16.910s	802.465us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.320s	1.066ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	33.520s	1.245ms	20	20	100.00
		lc_ctrl_jtag_errors	1.349m	5.807ms	20	20	100.00
		lc_ctrl_jtag_access	30.090s	1.444ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.110s	1.589ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.020s	283.311us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.690s	98.193us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	52.040s	2.680ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.120s	1.411ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.970s	79.747us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.320s	148.085us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.450s	142.860us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	1.456m	4.066ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.270s	15.820us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.151m	39.368ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.360s	53.199us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.470s	136.711us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.470s	136.711us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.070s	42.943us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	57.424us	20	20	100.00
		lc_ctrl_csr_aliasing	1.160s	16.197us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	87.190us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.070s	42.943us	5	5	100.00
		lc_ctrl_csr_rw	1.090s	57.424us	20	20	100.00
		lc_ctrl_csr_aliasing	1.160s	16.197us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.960s	87.190us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
		lc_ctrl_tl_intg_err	4.030s	116.739us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.030s	116.739us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.220s	1.245ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.017m	281.579us	50	50	100.00
		lc_ctrl_sec_cm	1.103m	920.825us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.870s	2.362ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	15.220s	151.481us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.320s	1.066ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.000s	473.210us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.000s	473.210us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	21.120s	1.106ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	24.160s	1.391ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	24.160s	1.391ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	26.676m	143.004ms	6	50	12.00
V3		TOTAL			6	50	12.00
		TOTAL			986	1030	95.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.93	97.18	95.08	91.98	97.67	95.88	98.73	95.00

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 31 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 31 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.2243047122
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5f864c02-7898-470f-9db1-8b076ed739f6
```
  - 1.lc_ctrl_stress_all_with_rand_reset.3991183415
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:b6e1989c-d9c5-4cb2-8ae6-a4e1c4518e26
```
  - ... and 29 more failures.
Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 6 failures.
  - 5.lc_ctrl_stress_all_with_rand_reset.517738521
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e355884e-42ff-4c68-b598-6f2affccebc1
```
  - 9.lc_ctrl_stress_all_with_rand_reset.666493301
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:e2ab137f-d935-4ad8-a1aa-8ab52c95f28d
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 3 failures:

Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

4.lc_ctrl_stress_all_with_rand_reset.1743027776
Line 976, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1697708052 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 1697708052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.lc_ctrl_stress_all_with_rand_reset.3164936928
Line 47660, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 143004331969 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 143004331969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 2 failures:

Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

47.lc_ctrl_stress_all_with_rand_reset.2487467895
Line 9171, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 18257484566 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x140a3a0c
  UVM_INFO @ 18257484566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.lc_ctrl_stress_all_with_rand_reset.2511673119
Line 3239, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 3662495627 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x1a9aea00
  UVM_INFO @ 3662495627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.lc_ctrl_stress_all_with_rand_reset.2691357250
    Line 3547, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2946785264 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 533321800 [0x1fc9d848]) Regname: lc_ctrl_reg_block.otp_vendor_test_ctrl reset value: 0x0
  UVM_INFO @ 2946785264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (lc_ctrl_scoreboard.sv:239) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.lc_ctrl_stress_all_with_rand_reset.766766425
    Line 7174, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4775232076 ps: (lc_ctrl_scoreboard.sv:239) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 97, LC_St DecLcStTestLocked1
  UVM_INFO @ 4775232076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```